1 /* $NetBSD: pte.h,v 1.18 1997/05/15 22:25:45 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgements: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgements: 29 * This product includes software developed by Harvard University. 30 * This product includes software developed by the University of 31 * California, Berkeley and its contributors. 32 * 4. Neither the name of the University nor the names of its contributors 33 * may be used to endorse or promote products derived from this software 34 * without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 46 * SUCH DAMAGE. 47 * 48 * @(#)pte.h 8.1 (Berkeley) 6/11/93 49 */ 50 51 /* 52 * Sun-4 (sort of), 4c (SparcStation), and 4m Page Table Entries 53 * (Sun calls them `Page Map Entries'). 54 */ 55 56 #ifndef _LOCORE 57 /* 58 * Segment maps contain `pmeg' (Page Map Entry Group) numbers. 59 * A PMEG is simply an index that names a group of 32 (sun4) or 60 * 64 (sun4c) PTEs. 61 * Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits 62 * to hold the hardware MMU resource number. 63 */ 64 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 65 /* 66 * Region maps contain `smeg' (Segment Entry Group) numbers. 67 * An SMEG is simply an index that names a group of 64 PMEGs. 68 */ 69 typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */ 70 #endif 71 72 /* 73 * Address translation works as follows: 74 * 75 * (for sun4c and 2-level sun4) 76 * 1. test va<31:29> -- these must be 000 or 111 (or you get a fault) 77 * 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number; 78 * use this to index the segment maps, yielding a 7 or 9 bit value. 79 * (for 3-level sun4) 80 * 1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number; 81 * use this to index the region maps, yielding a 10 bit value. 82 * 2. take the value from (1) above and concatenate va<17:12> to 83 * get a `segment map entry' index. This gives a 9 bit value. 84 * (for sun4c) 85 * 3. take the value from (2) above and concatenate va<17:12> to 86 * get a `page map entry' index. This gives a 32-bit PTE. 87 * (for sun4) 88 * 3. take the value from (2 or 3) above and concatenate va<17:13> to 89 * get a `page map entry' index. This gives a 32-bit PTE. 90 ** 91 * For sun4m: 92 * 1. Use context_reg<3:0> to index the context table (located at 93 * (context_reg << 2) | ((ctx_tbl_ptr_reg >> 2) << 6) ). This 94 * gives a 32-bit page-table-descriptor (PTP). 95 * 2. Use va<31:24> to index the region table located by the PTP from (1): 96 * PTP<31:6> << 10. This gives another PTP for the segment tables 97 * 3. Use va<23:18> to index the segment table located by the PTP from (2) 98 * as follows: PTP<31:4> << 8. This gives another PTP for the page tbl. 99 * 4. Use va<17:12> to index the page table given by (3)'s PTP: 100 * PTP<31:4> << 8. This gives a 32-bit PTE. 101 * 102 * In other words: 103 * 104 * struct sun4_3_levelmmu_virtual_addr { 105 * u_int va_reg:8, (virtual region) 106 * va_seg:6, (virtual segment) 107 * va_pg:5, (virtual page within segment) 108 * va_off:13; (offset within page) 109 * }; 110 * struct sun4_virtual_addr { 111 * u_int :2, (required to be the same as bit 29) 112 * va_seg:12, (virtual segment) 113 * va_pg:5, (virtual page within segment) 114 * va_off:13; (offset within page) 115 * }; 116 * struct sun4c_virtual_addr { 117 * u_int :2, (required to be the same as bit 29) 118 * va_seg:12, (virtual segment) 119 * va_pg:6, (virtual page within segment) 120 * va_off:12; (offset within page) 121 * }; 122 * 123 * struct sun4m_virtual_addr { 124 * u_int va_reg:8, (virtual region) 125 * va_seg:6, (virtual segment within region) 126 * va_pg:6, (virtual page within segment) 127 * va_off:12; (offset within page) 128 * }; 129 * 130 * Then, given any `va': 131 * 132 * extern smeg_t regmap[16][1<<8]; (3-level MMU only) 133 * extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4) 134 * extern int ptetable[128][1<<6]; ([512][1<<5] for sun4) 135 * 136 * extern u_int s4m_ctxmap[16]; (sun4m SRMMU only) 137 * extern u_int s4m_regmap[16][1<<8]; (sun4m SRMMU only) 138 * extern u_int s4m_segmap[1<<8][1<<6]; (sun4m SRMMU only) 139 * extern u_int s4m_pagmap[1<<14][1<<6]; (sun4m SRMMU only) 140 * 141 * (the above being in the hardware, accessed as Alternate Address Spaces on 142 * all machines but the Sun4m SRMMU, in which case the tables are in physical 143 * kernel memory. In the 4m architecture, the tables are not layed out as 144 * 2-dim arrays, but are sparsely allocated as needed, and point to each 145 * other.) 146 * 147 * if (cputyp==CPU_SUN4M) // SPARC Reference MMU 148 * regptp = s4m_ctxmap[curr_ctx]; 149 * if (!(regptp & SRMMU_TEPTD)) TRAP(); 150 * segptp = *(u_int *)(((regptp & ~0x3) << 4) | va.va_reg); 151 * if (!(segptp & SRMMU_TEPTD)) TRAP(); 152 * pagptp = *(u_int *)(((segptp & ~0x3) << 4) | va.va_seg); 153 * if (!(pagptp & SRMMU_TEPTD)) TRAP(); 154 * pte = *(u_int *)(((pagptp & ~0x3) << 4) | va.va_pg); 155 * if (!(pte & SRMMU_TEPTE)) TRAP(); // like PG_V 156 * if (usermode && PTE_PROT_LEVEL(pte) > 0x5) TRAP(); 157 * if (writing && !PTE_PROT_LEVEL_ALLOWS_WRITING(pte)) TRAP(); 158 * if (!(pte & SRMMU_PG_C)) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 159 * pte |= SRMMU_PG_U; 160 * if (writing) pte |= PG_M; 161 * physaddr = ((pte & SRMMU_PG_PFNUM) << SRMMU_PGSHIFT)|va.va_off; 162 * return; 163 * if (mmu_3l) 164 * physreg = regmap[curr_ctx][va.va_reg]; 165 * physseg = segmap[physreg][va.va_seg]; 166 * else 167 * physseg = segmap[curr_ctx][va.va_seg]; 168 * pte = ptetable[physseg][va.va_pg]; 169 * if (!(pte & PG_V)) TRAP(); 170 * if (writing && !pte.pg_w) TRAP(); 171 * if (usermode && pte.pg_s) TRAP(); 172 * if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 173 * pte |= PG_U; (mark used/accessed) 174 * if (writing) pte |= PG_M; (mark modified) 175 * ptetable[physseg][va.va_pg] = pte; 176 * physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off; 177 */ 178 179 #if defined(SUN4_MMU3L) && !defined(SUN4) 180 #error "configuration error" 181 #endif 182 183 #define NBPRG (1 << 24) /* bytes per region */ 184 #define RGSHIFT 24 /* log2(NBPRG) */ 185 #define RGOFSET (NBPRG - 1) /* mask for region offset */ 186 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 187 188 #define NBPSG (1 << 18) /* bytes per segment */ 189 #define SGSHIFT 18 /* log2(NBPSG) */ 190 #define SGOFSET (NBPSG - 1) /* mask for segment offset */ 191 192 /* number of PTEs that map one segment (not number that fit in one segment!) */ 193 #if defined(SUN4) && (defined(SUN4C) || defined(SUN4M)) 194 extern int nptesg; 195 #define NPTESG nptesg /* (which someone will have to initialize) */ 196 #else 197 #define NPTESG (NBPSG / NBPG) 198 #endif 199 200 /* virtual address to virtual region number */ 201 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 202 203 /* virtual address to virtual segment number */ 204 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 205 206 /* virtual address to virtual page number, for Sun-4 and Sun-4c */ 207 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 208 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 209 #define VA_SUN4M_VPG(va) (((int)(va) >> 12) & 63) 210 211 /* virtual address to offset within page */ 212 #define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF) 213 #define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF) 214 #define VA_SUN4M_OFF(va) (((int)(va)) & 0xFFF) 215 216 /* truncate virtual address to region base */ 217 #define VA_ROUNDDOWNTOREG(va) ((int)(va) & ~RGOFSET) 218 219 /* truncate virtual address to segment base */ 220 #define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET) 221 222 /* virtual segment to virtual address (must sign extend on holy MMUs!) */ 223 #define VRTOVA(vr) ((CPU_ISSUN4M || HASSUN4_MMU3L) \ 224 ? ((int)(vr) << RGSHIFT) \ 225 : (((int)(vr) << (RGSHIFT+2)) >> 2)) 226 #define VSTOVA(vr,vs) ((CPU_ISSUN4M || HASSUN4_MMU3L) \ 227 ? (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT)) \ 228 : ((((int)(vr) << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT))) 229 230 extern int mmu_has_hole; 231 #define VA_INHOLE(va) (mmu_has_hole \ 232 ? ( (unsigned int)(((int)(va) >> PG_VSHIFT) + 1) > 1) \ 233 : 0) 234 235 /* Define the virtual address space hole */ 236 #define MMU_HOLE_START 0x20000000 237 #define MMU_HOLE_END 0xe0000000 238 239 #if defined(SUN4M) /* Optimization: sun4m, sun4c have same page */ 240 #if defined(SUN4) /* size, so they're used interchangeably */ 241 #define VA_VPG(va) (cputyp==CPU_SUN4 ? VA_SUN4_VPG(va) : VA_SUN4C_VPG(va)) 242 #define VA_OFF(VA) (cputyp==CPU_SUN4 ? VA_SUN4_OFF(va) : VA_SUN4C_OFF(va)) 243 #else 244 #define VA_VPG(va) VA_SUN4M_VPG(va) 245 #define VA_OFF(va) VA_SUN4M_OFF(va) 246 #endif /* defined SUN4 */ 247 #else /* 4m not defined */ 248 #if defined(SUN4) && defined(SUN4C) 249 #define VA_VPG(va) (cputyp==CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va)) 250 #define VA_OFF(va) (cputyp==CPU_SUN4C ? VA_SUN4C_OFF(va) : VA_SUN4_OFF(va)) 251 #endif 252 #if defined(SUN4C) && !defined(SUN4) 253 #define VA_VPG(va) VA_SUN4C_VPG(va) 254 #define VA_OFF(va) VA_SUN4C_OFF(va) 255 #endif 256 #if !defined(SUN4C) && defined(SUN4) 257 #define VA_VPG(va) VA_SUN4_VPG(va) 258 #define VA_OFF(va) VA_SUN4_OFF(va) 259 #endif 260 #endif /* defined 4m */ 261 262 /* there is no `struct pte'; we just use `int'; this is for non-4M only */ 263 #define PG_V 0x80000000 264 #define PG_PROT 0x60000000 /* both protection bits */ 265 #define PG_W 0x40000000 /* allowed to write */ 266 #define PG_S 0x20000000 /* supervisor only */ 267 #define PG_NC 0x10000000 /* non-cacheable */ 268 #define PG_TYPE 0x0c000000 /* both type bits */ 269 270 #define PG_OBMEM 0x00000000 /* on board memory */ 271 #define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */ 272 #define PG_VME16 0x08000000 /* 16-bit-data VME space */ 273 #define PG_VME32 0x0c000000 /* 32-bit-data VME space */ 274 #if defined(SUN4M) 275 #define PG_SUN4M_OBMEM 0x0 /* No type bits=>obmem on 4m */ 276 #define PG_SUN4M_OBIO 0xf /* obio maps to 0xf on 4M */ 277 #define SRMMU_PGTYPE 0xf0000000 /* Top 4 bits of pte PPN give type */ 278 #endif 279 280 #define PG_U 0x02000000 281 #define PG_M 0x01000000 282 #define PG_IOC 0x00800000 283 #define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */ 284 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 285 286 #define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */ 287 #define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */ 288 #define PG_M_SHIFT4M 5 /* shift to get SRMMU_PG_M,R on 4m */ 289 /*efine PG_NOACC 0 ** XXX */ 290 #define PG_KR 0x20000000 291 #define PG_KW 0x60000000 292 #define PG_URKR 0 293 #define PG_UW 0x40000000 294 295 #ifdef KGDB 296 /* but we will define one for gdb anyway */ 297 struct pte { 298 u_int pg_v:1, 299 pg_w:1, 300 pg_s:1, 301 pg_nc:1; 302 enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2; 303 u_int pg_u:1, 304 pg_m:1, 305 pg_mbz:5, 306 pg_pfnum:19; 307 }; 308 #if defined(SUN4M) 309 struct srmmu_pte { 310 u_int pg_pfnum:20, 311 pg_c:1, 312 pg_m:1, 313 pg_u:1; 314 enum pgprot { pprot_r_r, pprot_rw_rw, pprot_rx_rx, pprot_rwx_rwx, 315 pprot_x_x, pprot_r_rw, pprot_n_rx, pprot_n_rwx } 316 pg_prot:3; /* prot. bits: pprot_<user>_<supervisor> */ 317 u_int pg_must_be_2:2; 318 }; 319 #endif 320 #endif 321 322 /* 323 * These are needed in the register window code 324 * to check the validity of (ostensible) user stack PTEs. 325 */ 326 #define PG_VSHIFT 29 /* (va>>vshift)==0 or -1 => valid */ 327 /* XXX fix this name, it is a va shift not a pte bit shift! */ 328 329 #define PG_PROTSHIFT 29 330 #define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */ 331 #define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */ 332 333 /* %%%: Fix above and below for 4m? */ 334 335 /* static __inline int PG_VALID(void *va) { 336 register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1); 337 } */ 338 339 340 /* 341 * Here are the bit definitions for 4M/SRMMU pte's 342 */ 343 /* MMU TABLE ENTRIES */ 344 #define SRMMU_TEINVALID 0x0 /* invalid (serves as !valid bit) */ 345 #define SRMMU_TEPTD 0x1 /* Page Table Descriptor */ 346 #define SRMMU_TEPTE 0x2 /* Page Table Entry */ 347 #define SRMMU_TERES 0x3 /* reserved */ 348 #define SRMMU_TETYPE 0x3 /* mask for table entry type */ 349 /* PTE FIELDS */ 350 #define SRMMU_PPNMASK 0xFFFFFF00 351 #define SRMMU_PPNSHIFT 0x8 352 #define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */ 353 #define SRMMU_L1PPNSHFT 0x14 354 #define SRMMU_L1PPNMASK 0xFFF00000 355 #define SRMMU_L2PPNSHFT 0xE 356 #define SRMMU_L2PPNMASK 0xFC000 357 #define SRMMU_L3PPNSHFT 0x8 358 #define SRMMU_L3PPNMASK 0x3F00 359 /* PTE BITS */ 360 #define SRMMU_PG_C 0x80 /* cacheable */ 361 #define SRMMU_PG_M 0x40 /* modified (dirty) */ 362 #define SRMMU_PG_R 0x20 /* referenced */ 363 #define SRMMU_PGBITSMSK 0xE0 364 /* PTE PROTECTION */ 365 #define SRMMU_PROT_MASK 0x1C /* Mask protection bits out of pte */ 366 #define SRMMU_PROT_SHFT 0x2 367 #define PPROT_R_R 0x0 /* These are in the form: */ 368 #define PPROT_RW_RW 0x4 /* PPROT_<u>_<s> */ 369 #define PPROT_RX_RX 0x8 /* where <u> is the user-mode */ 370 #define PPROT_RWX_RWX 0xC /* permission, and <s> is the */ 371 #define PPROT_X_X 0x10 /* supervisor mode permission. */ 372 #define PPROT_R_RW 0x14 /* R=read, W=write, X=execute */ 373 #define PPROT_N_RX 0x18 /* N=none. */ 374 #define PPROT_N_RWX 0x1C 375 #define PPROT_WRITE 0x4 /* set iff write priv. allowed */ 376 #define PPROT_S 0x18 /* effective S bit */ 377 #define PPROT_U2S_OMASK 0x18 /* OR with prot. to revoke user priv */ 378 /* TABLE SIZES */ 379 #define SRMMU_L1SIZE 0x100 380 #define SRMMU_L2SIZE 0x40 381 #define SRMMU_L3SIZE 0x40 382 383 /* 384 * IOMMU PTE bits. 385 */ 386 #define IOPTE_PPN_MASK 0x07ffff00 387 #define IOPTE_PPN_SHIFT 8 388 #define IOPTE_RSVD 0x000000f1 389 #define IOPTE_WRITE 0x00000004 390 #define IOPTE_VALID 0x00000002 391