xref: /netbsd-src/sys/arch/sparc/include/psl.h (revision ce0bb6e8d2e560ecacbe865a848624f94498063b)
1 /*	$NetBSD: psl.h,v 1.6 1995/03/28 18:20:07 jtc Exp $ */
2 
3 /*
4  * Copyright (c) 1992, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This software was developed by the Computer Systems Engineering group
8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9  * contributed to Berkeley.
10  *
11  * All advertising materials mentioning features or use of this software
12  * must display the following acknowledgement:
13  *	This product includes software developed by the University of
14  *	California, Lawrence Berkeley Laboratory.
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions
18  * are met:
19  * 1. Redistributions of source code must retain the above copyright
20  *    notice, this list of conditions and the following disclaimer.
21  * 2. Redistributions in binary form must reproduce the above copyright
22  *    notice, this list of conditions and the following disclaimer in the
23  *    documentation and/or other materials provided with the distribution.
24  * 3. All advertising materials mentioning features or use of this software
25  *    must display the following acknowledgement:
26  *	This product includes software developed by the University of
27  *	California, Berkeley and its contributors.
28  * 4. Neither the name of the University nor the names of its contributors
29  *    may be used to endorse or promote products derived from this software
30  *    without specific prior written permission.
31  *
32  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42  * SUCH DAMAGE.
43  *
44  *	@(#)psl.h	8.1 (Berkeley) 6/11/93
45  */
46 
47 #ifndef PSR_IMPL
48 
49 /*
50  * SPARC Process Status Register (in psl.h for hysterical raisins).
51  *
52  * The picture in the Sun manuals looks like this:
53  *	                                     1 1
54  *	 31   28 27   24 23   20 19       14 3 2 11    8 7 6 5 4       0
55  *	+-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
56  *	|  impl |  ver  |  icc  |  reserved |E|E|  pil  |S|P|E|   CWP   |
57  *	|       |       |n z v c|           |C|F|       | |S|T|         |
58  *	+-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
59  */
60 
61 #define	PSR_IMPL	0xf0000000	/* implementation */
62 #define	PSR_VER		0x0f000000	/* version */
63 #define	PSR_ICC		0x00f00000	/* integer condition codes */
64 #define	PSR_N		0x00800000	/* negative */
65 #define	PSR_Z		0x00400000	/* zero */
66 #define	PSR_O		0x00200000	/* overflow */
67 #define	PSR_C		0x00100000	/* carry */
68 #define	PSR_EC		0x00002000	/* coprocessor enable */
69 #define	PSR_EF		0x00001000	/* FP enable */
70 #define	PSR_PIL		0x00000f00	/* interrupt level */
71 #define	PSR_S		0x00000080	/* supervisor (kernel) mode */
72 #define	PSR_PS		0x00000040	/* previous supervisor mode (traps) */
73 #define	PSR_ET		0x00000020	/* trap enable */
74 #define	PSR_CWP		0x0000001f	/* current window pointer */
75 
76 #define	PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
77 
78 #define	PIL_CLOCK	10
79 
80 #if defined(_KERNEL) && !defined(LOCORE)
81 /*
82  * GCC pseudo-functions for manipulating PSR (primarily PIL field).
83  */
84 static __inline int getpsr() {
85 	int psr;
86 
87 	__asm __volatile("rd %%psr,%0" : "=r" (psr));
88 	return (psr);
89 }
90 
91 static __inline void setpsr(int newpsr) {
92 	__asm __volatile("wr %0,0,%%psr" : : "r" (newpsr));
93 	__asm __volatile("nop");
94 	__asm __volatile("nop");
95 	__asm __volatile("nop");
96 }
97 
98 static __inline int spl0() {
99 	int psr, oldipl;
100 
101 	/*
102 	 * wrpsr xors two values: we choose old psr and old ipl here,
103 	 * which gives us the same value as the old psr but with all
104 	 * the old PIL bits turned off.
105 	 */
106 	__asm __volatile("rd %%psr,%0" : "=r" (psr));
107 	oldipl = psr & PSR_PIL;
108 	__asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
109 
110 	/*
111 	 * Three instructions must execute before we can depend
112 	 * on the bits to be changed.
113 	 */
114 	__asm __volatile("nop; nop; nop");
115 	return (oldipl);
116 }
117 
118 /*
119  * PIL 1 through 14 can use this macro.
120  * (spl0 and splhigh are special since they put all 0s or all 1s
121  * into the ipl field.)
122  */
123 #define	SPL(name, newipl) \
124 static __inline int name() { \
125 	int psr, oldipl; \
126 	__asm __volatile("rd %%psr,%0" : "=r" (psr)); \
127 	oldipl = psr & PSR_PIL; \
128 	psr &= ~oldipl; \
129 	__asm __volatile("wr %0,%1,%%psr" : : \
130 	    "r" (psr), "n" ((newipl) << 8)); \
131 	__asm __volatile("nop; nop; nop"); \
132 	return (oldipl); \
133 }
134 
135 SPL(splsoftint, 1)
136 #define	splnet	splsoftint
137 #define	splsoftclock splsoftint
138 
139 /* tty input runs at software level 6 */
140 #define	PIL_TTY	6
141 SPL(spltty, PIL_TTY)
142 
143 /* Memory allocation (must be as high as highest network or tty device) */
144 SPL(splimp, 7)
145 
146 /* audio software interrupts are at software level 4 */
147 #define	PIL_AUSOFT	4
148 SPL(splausoft, PIL_AUSOFT)
149 
150 /* floppy software interrupts are at software level 4 too */
151 #define PIL_FDSOFT	4
152 SPL(splfdsoft, PIL_FDSOFT)
153 
154 SPL(splbio, 9)
155 
156 SPL(splclock, PIL_CLOCK)
157 
158 /* fd hardware interrupts are at level 11 */
159 SPL(splfd, 11)
160 
161 /* zs hardware interrupts are at level 12 */
162 SPL(splzs, 12)
163 
164 /* audio hardware interrupts are at level 13 */
165 SPL(splaudio, 13)
166 
167 /* second sparc timer interrupts at level 14 */
168 SPL(splstatclock, 14)
169 
170 static __inline int splhigh() {
171 	int psr, oldipl;
172 
173 	__asm __volatile("rd %%psr,%0" : "=r" (psr));
174 	__asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
175 	__asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \
176 	    "r" (psr), "n" (PSR_PIL));
177 	return (oldipl);
178 }
179 
180 /* splx does not have a return value */
181 static __inline void splx(int newipl) {
182 	int psr;
183 
184 	__asm __volatile("rd %%psr,%0" : "=r" (psr));
185 	__asm __volatile("wr %0,%1,%%psr" : : \
186 	    "r" (psr & ~PSR_PIL), "rn" (newipl));
187 	__asm __volatile("nop; nop; nop");
188 }
189 #endif /* KERNEL && !LOCORE */
190 
191 #endif /* PSR_IMPL */
192