1 /* $NetBSD: instr.h,v 1.2 1994/11/20 20:53:11 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)instr.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* see also Appendix F of the SPARC version 8 document */ 48 enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem }; 49 enum IOP2 { IOP2_UNIMP, IOP2_err1, IOP2_Bicc, IOP2_err3, 50 IOP2_SETHI, IOP2_err5, IOP2_FBfcc, IOP2_CBccc }; 51 enum IOP3_reg { 52 IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR, 53 IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR, 54 IOP3_ADDX, IOP3_rerr09, IOP3_UMUL, IOP3_SMUL, 55 IOP3_SUBX, IOP3_rerr0d, IOP3_UDIV, IOP3_SDIV, 56 IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc, 57 IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc, 58 IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc, 59 IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc, 60 IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV, 61 IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA, 62 IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR, 63 IOP3_rerr2c, IOP3_rerr2d, IOP3_rerr2e, IOP3_rerr2f, 64 IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR, 65 IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2, 66 IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH, 67 IOP3_SAVE, IOP3_RESTORE, IOP3_rerr3e, IOP3_rerr3f 68 }; 69 enum IOP3_mem { 70 IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD, 71 IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD, 72 IOP3_merr08, IOP3_LDSB, IOP3_LDSH, IOP3_merr0b, 73 IOP3_merr0c, IOP3_LDSTUB, IOP3_merr0f, IOP3_SWAP, 74 IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA, 75 IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA, 76 IOP3_merr18, IOP3_LDSBA, IOP3_LDSHA, IOP3_merr1b, 77 IOP3_merr1c, IOP3_LDSTUBA, IOP3_merr1f, IOP3_SWAPA, 78 IOP3_LDF, IOP3_LDFSR, IOP3_merr22, IOP3_LDDF, 79 IOP3_STF, IOP3_STFSR, IOP3_STDFQ, IOP3_STDF, 80 IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b, 81 IOP3_merr2c, IOP3_merr2d, IOP3_merr2e, IOP3_merr2f, 82 IOP3_LFC, IOP3_LDCSR, IOP3_merr32, IOP3_LDDC, 83 IOP3_STC, IOP3_STCSR, IOP3_STDCQ, IOP3_STDC, 84 IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b, 85 IOP3_merr3c, IOP3_merr3d, IOP3_merr3e, IOP3_merr3f 86 }; 87 88 /* 89 * Integer condition codes. 90 */ 91 #define Icc_N 0x0 /* never */ 92 #define Icc_E 0x1 /* equal (equiv. zero) */ 93 #define Icc_LE 0x2 /* less or equal */ 94 #define Icc_L 0x3 /* less */ 95 #define Icc_LEU 0x4 /* less or equal unsigned */ 96 #define Icc_CS 0x5 /* carry set (equiv. less unsigned) */ 97 #define Icc_NEG 0x6 /* negative */ 98 #define Icc_VS 0x7 /* overflow set */ 99 #define Icc_A 0x8 /* always */ 100 #define Icc_NE 0x9 /* not equal (equiv. not zero) */ 101 #define Icc_G 0xa /* greater */ 102 #define Icc_GE 0xb /* greater or equal */ 103 #define Icc_GU 0xc /* greater unsigned */ 104 #define Icc_CC 0xd /* carry clear (equiv. gtr or eq unsigned) */ 105 #define Icc_POS 0xe /* positive */ 106 #define Icc_VC 0xf /* overflow clear */ 107 108 /* 109 * Integer registers. 110 */ 111 #define I_G0 0 112 #define I_G1 1 113 #define I_G2 2 114 #define I_G3 3 115 #define I_G4 4 116 #define I_G5 5 117 #define I_G6 6 118 #define I_G7 7 119 #define I_O0 8 120 #define I_O1 9 121 #define I_O2 10 122 #define I_O3 11 123 #define I_O4 12 124 #define I_O5 13 125 #define I_O6 14 126 #define I_O7 15 127 #define I_L0 16 128 #define I_L1 17 129 #define I_L2 18 130 #define I_L3 19 131 #define I_L4 20 132 #define I_L5 21 133 #define I_L6 22 134 #define I_L7 23 135 #define I_I0 24 136 #define I_I1 25 137 #define I_I2 26 138 #define I_I3 27 139 #define I_I4 28 140 #define I_I5 29 141 #define I_I6 30 142 #define I_I7 31 143 144 /* 145 * An instruction. 146 */ 147 union instr { 148 int i_int; /* as a whole */ 149 150 /* 151 * The first level of decoding is to use the top 2 bits. 152 * This gives us one of three `formats', which usually give 153 * a second level of decoding. 154 */ 155 struct { 156 u_int i_op:2; /* first-level decode */ 157 u_int :30; 158 } i_any; 159 160 /* 161 * Format 1 instructions: CALL (undifferentiated). 162 */ 163 struct { 164 u_int :2; /* 01 */ 165 int i_disp:30; /* displacement */ 166 } i_call; 167 168 /* 169 * Format 2 instructions (SETHI, UNIMP, and branches, plus illegal 170 * unused codes). 171 */ 172 struct { 173 u_int :2; /* 00 */ 174 u_int :5; 175 u_int i_op2:3; /* second-level decode */ 176 u_int :22; 177 } i_op2; 178 179 /* UNIMP, SETHI */ 180 struct { 181 u_int :2; /* 00 */ 182 u_int i_rd:5; /* destination register */ 183 u_int i_op2:3; /* opcode: UNIMP or SETHI */ 184 u_int i_imm:22; /* immediate value */ 185 } i_imm22; 186 187 /* branches: Bicc, FBfcc, CBccc */ 188 struct { 189 u_int :2; /* 00 */ 190 u_int i_annul:1; /* annul bit */ 191 u_int i_cond:4; /* condition codes */ 192 u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */ 193 int i_disp:22; /* branch displacement */ 194 } i_branch; 195 196 /* 197 * Format 3 instructions (memory reference; arithmetic, logical, 198 * shift, and other miscellaneous operations). The second-level 199 * decode almost always makes use of an `rd' and `rs1', however 200 * (see also IOP3_reg and IOP3_mem). 201 * 202 * Beyond that, the low 14 bits may be broken up in one of three 203 * different ways, if at all: 204 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem] 205 * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem] 206 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] 207 */ 208 struct { 209 u_int :2; /* 10 or 11 */ 210 u_int i_rd:5; /* destination register */ 211 u_int i_op3:6; /* second-level decode */ 212 u_int i_rs1:5; /* source register 1 */ 213 u_int i_low14:14; /* varies */ 214 } i_op3; 215 216 /* 217 * Memory forms. These set i_op=3 and use simm13 or asi layout. 218 * Memory references without an ASI should use 0, but the actual 219 * ASI field is simply ignored. 220 */ 221 struct { 222 u_int :2; /* 11 only */ 223 u_int i_rd:5; /* destination register */ 224 u_int i_op3:6; /* second-level decode (see IOP3_mem) */ 225 u_int i_i:1; /* immediate vs asi */ 226 u_int i_low13:13; /* depend on i bit */ 227 } i_loadstore; 228 229 /* 230 * Memory and register forms. 231 * These come in quite a variety and we do not 232 * attempt to break them down much. 233 */ 234 struct { 235 u_int :2; /* 10 or 11 */ 236 u_int i_rd:5; /* destination register */ 237 u_int i_op3:6; /* second-level decode */ 238 u_int i_rs1:5; /* source register 1 */ 239 u_int i_i:1; /* immediate bit (1) */ 240 int i_simm13:13; /* signed immediate */ 241 } i_simm13; 242 struct { 243 u_int :2; /* 10 or 11 */ 244 u_int i_rd:5; /* destination register */ 245 u_int i_op3:6; /* second-level decode */ 246 u_int i_rs1:5; /* source register 1 */ 247 u_int i_asi:8; /* asi */ 248 u_int i_rs2:5; /* source register 2 */ 249 } i_asi; 250 struct { 251 u_int :2; /* 10 only (register, no memory) */ 252 u_int i_rd:5; /* destination register */ 253 u_int i_op3:6; /* second-level decode (see IOP3_reg) */ 254 u_int i_rs1:5; /* source register 1 */ 255 u_int i_opf:9; /* coprocessor 3rd-level decode */ 256 u_int i_rs2:5; /* source register 2 */ 257 } i_opf; 258 259 }; 260 261 /* 262 * Internal macros for building instructions. These correspond 1-to-1 to 263 * the names above. Note that x << y | z == (x << y) | z. 264 */ 265 #define _I_ANY(op, b) ((op) << 30 | (b)) 266 267 #define _I_OP2(high, op2, low) \ 268 _I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low)) 269 #define _I_IMM22(rd, op2, imm) \ 270 _I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm)) 271 #define _I_BRANCH(a, c, op2, disp) \ 272 _I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp)) 273 #define _I_FBFCC(a, cond, disp) \ 274 _I_BRANCH(a, cond, IOP2_FBfcc, disp) 275 #define _I_CBCCC(a, cond, disp) \ 276 _I_BRANCH(a, cond, IOP2_CBccc, disp) 277 278 #define _I_SIMM(simm) (1 << 13 | ((simm) & 0x1fff)) 279 280 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \ 281 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14)) 282 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ 283 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 284 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \ 285 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13)) 286 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ 287 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 288 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ 289 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2)) 290 #define _I_OP3_R_RI(rd, op3, rs1, simm13) \ 291 _I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13)) 292 #define _I_OP3_R_RR(rd, op3, rs1, rs2) \ 293 _I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2) 294 295 #define I_CALL(d) _I_ANY(IOP_CALL, d) 296 #define I_UNIMP(v) _I_IMM22(0, IOP2_UNIMP, v) 297 #define I_BN(a, d) _I_BRANCH(a, Icc_N, IOP2_Bicc, d) 298 #define I_BE(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 299 #define I_BZ(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 300 #define I_BLE(a, d) _I_BRANCH(a, Icc_LE, IOP2_Bicc, d) 301 #define I_BL(a, d) _I_BRANCH(a, Icc_L, IOP2_Bicc, d) 302 #define I_BLEU(a, d) _I_BRANCH(a, Icc_LEU, IOP2_Bicc, d) 303 #define I_BCS(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 304 #define I_BLU(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 305 #define I_BNEG(a, d) _I_BRANCH(a, Icc_NEG, IOP2_Bicc, d) 306 #define I_BVS(a, d) _I_BRANCH(a, Icc_VS, IOP2_Bicc, d) 307 #define I_BA(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 308 #define I_B(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 309 #define I_BNE(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 310 #define I_BNZ(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 311 #define I_BG(a, d) _I_BRANCH(a, Icc_G, IOP2_Bicc, d) 312 #define I_BGE(a, d) _I_BRANCH(a, Icc_GE, IOP2_Bicc, d) 313 #define I_BGU(a, d) _I_BRANCH(a, Icc_GU, IOP2_Bicc, d) 314 #define I_BCC(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 315 #define I_BGEU(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 316 #define I_BPOS(a, d) _I_BRANCH(a, Icc_POS, IOP2_Bicc, d) 317 #define I_BVC(a, d) _I_BRANCH(a, Icc_VC, IOP2_Bicc, d) 318 #define I_SETHI(r, v) _I_IMM22(r, 4, v) 319 320 #define I_ORri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_OR, rs1, imm) 321 #define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2) 322 323 #define I_MOVi(rd, imm) _I_OP3_R_RI(rd, IOP3_OR, I_G0, imm) 324 #define I_MOVr(rd, rs) _I_OP3_R_RR(rd, IOP3_OR, I_G0, rs) 325 326 #define I_RDPSR(rd) _I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0) 327 328 #define I_JMPLri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm) 329 #define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2) 330 331 /* 332 * (Since these are sparse, we skip the enumerations for now.) 333 * FPop values. All appear in both FPop1 and FPop2 spaces, but arithmetic 334 * ops should happen only with FPop1 and comparison only with FPop2. 335 * The type sits in the low two bits; those bits are given as zero here. 336 */ 337 #define FMOV 0x00 338 #define FNEG 0x04 339 #define FABS 0x08 340 #define FSQRT 0x28 341 #define FADD 0x40 342 #define FSUB 0x44 343 #define FMUL 0x48 344 #define FDIV 0x4c 345 #define FCMP 0x50 346 #define FCMPE 0x54 347 #define FSMULD 0x68 348 #define FDMULX 0x6c 349 #define FTOS 0xc4 350 #define FTOD 0xc8 351 #define FTOX 0xcc 352 #define FTOI 0xd0 353 354 /* 355 * FPU data types. 356 */ 357 #define FTYPE_INT 0 /* data = 32-bit signed integer */ 358 #define FTYPE_SNG 1 /* data = 32-bit float */ 359 #define FTYPE_DBL 2 /* data = 64-bit double */ 360 #define FTYPE_EXT 3 /* data = 128-bit extended (quad-prec) */ 361