1 /* $NetBSD: ctlreg.h,v 1.7 1995/04/13 13:41:02 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Sun-4, 4c, and 4m control registers. (includes address space definitions 49 * and some registers in control space). 50 */ 51 52 /* 0x00 unused */ 53 /* 0x01 unused */ 54 #if defined(SUN4C) || defined(SUN4) 55 #define ASI_CONTROL 0x02 /* cache enable, context reg, etc */ 56 #define ASI_SEGMAP 0x03 /* segment maps (so we can reach each pmeg) */ 57 #define ASI_PTE 0x04 /* PTE space (pmegs) */ 58 #define ASI_REGMAP 0x06 /* region maps (3 level MMUs only) */ 59 #define ASI_HWFLUSHSEG 0x05 /* hardware assisted version of FLUSHSEG */ 60 #define ASI_HWFLUSHPG 0x06 /* hardware assisted version of FLUSHPG */ 61 #define ASI_HWFLUSHCTX 0x07 /* hardware assisted version of FLUSHCTX */ 62 #endif 63 #if defined(SUN4M) 64 #define ASI_SRMMUFP 0x03 /* ref mmu flush/probe */ 65 #define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */ 66 #define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */ 67 #define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/ 68 #define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */ 69 #define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */ 70 71 #define ASI_SRMMU 0x04 /* ref mmu registers */ 72 #define ASI_SRMMUDIAG 0x06 73 #endif 74 75 #define ASI_USERI 0x08 /* I-space (user) */ 76 #define ASI_KERNELI 0x09 /* I-space (kernel) */ 77 #define ASI_USERD 0x0a /* D-space (user) */ 78 #define ASI_KERNELD 0x0b /* D-space (kernel) */ 79 80 #if defined(SUN4C) || defined(SUN4) 81 #define ASI_FLUSHREG 0x7 /* causes hardware to flush cache region */ 82 #define ASI_FLUSHSEG 0x0c /* causes hardware to flush cache segment */ 83 #define ASI_FLUSHPG 0x0d /* causes hardware to flush cache page */ 84 #define ASI_FLUSHCTX 0x0e /* causes hardware to flush cache context */ 85 #endif 86 #if defined(SUN4) 87 #define ASI_DCACHE 0x0f /* flush data cache; not used on 4c */ 88 #endif 89 90 #if defined(SUN4M) 91 #define ASI_ICACHETAG 0x0c /* instruction cache tag */ 92 #define ASI_ICACHEDATA 0x0d /* instruction cache data */ 93 #define ASI_DCACHETAG 0x0e /* data cache tag */ 94 #define ASI_DCACHEDATA 0x0f /* data cache data */ 95 #define ASI_IDCACHELFP 0x10 /* ms2 only: flush i&d cache line (page) */ 96 #define ASI_IDCACHELFS 0x11 /* ms2 only: flush i&d cache line (seg) */ 97 #define ASI_IDCACHELFR 0x12 /* ms2 only: flush i&d cache line (reg) */ 98 #define ASI_IDCACHELFC 0x13 /* ms2 only: flush i&d cache line (ctxt) */ 99 #define ASI_IDCACHELFU 0x14 /* ms2 only: flush i&d cache line (user) */ 100 #define ASI_SRMMUTLB 0x20 /* sun ref mmu bypass, ie. direct tlb access */ 101 #define ASI_ICACHECLR 0x36 /* ms1 only: instruction cache flash clear */ 102 #define ASI_DCACHECLR 0x37 /* ms1 only: data cache clear */ 103 #define ASI_DCACHEDIAG 0x39 /* data cache diagnostic register access */ 104 #endif 105 106 #if defined(SUN4C) || defined(SUN4) 107 /* registers in the control space */ 108 #define AC_CONTEXT 0x30000000 /* context register (byte) */ 109 #define AC_SYSENABLE 0x40000000 /* system enable register (byte) */ 110 #define AC_CACHETAGS 0x80000000 /* cache tag base address */ 111 #define AC_SERIAL 0xf0000000 /* special serial port sneakiness */ 112 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 113 #endif 114 115 #if defined(SUN4) 116 #define AC_IDPROM 0x00000000 /* ID PROM */ 117 #define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */ 118 #define AC_BUS_ERR 0x60000000 /* bus error register */ 119 #define AC_DIAG_REG 0x70000000 /* diagnostic reg */ 120 #define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */ 121 #define AC_VMEINTVEC 0xe0000000 /* vme interrupt vector */ 122 123 /* XXX: does not belong here */ 124 #define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */ 125 #endif 126 127 #if defined(SUN4C) 128 #define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */ 129 #define AC_SYNC_VA 0x60000004 /* sync error virtual addr */ 130 #define AC_ASYNC_ERR 0x60000008 /* async error reg */ 131 #define AC_ASYNC_VA 0x6000000c /* async error virtual addr */ 132 #define AC_CACHEDATA 0x90000000 /* cached data */ 133 #endif 134 135 #if defined(SUN4C) || defined(SUN4) 136 /* 137 * Bits in sync error register. Reading the register clears these; 138 * otherwise they accumulate. The error(s) occurred at the virtual 139 * address stored in the sync error address register, and may have 140 * been due to, e.g., what would usually be called a page fault. 141 * Worse, the bits accumulate during instruction prefetch, so 142 * various bits can be on that should be off. 143 */ 144 #define SER_WRITE 0x8000 /* error occurred during write */ 145 #define SER_INVAL 0x80 /* PTE had PG_V off */ 146 #define SER_PROT 0x40 /* operation violated PTE prot */ 147 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 148 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 149 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 150 #define SER_SZERR 0x02 /* size error, whatever that is */ 151 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 152 153 #define SER_BITS \ 154 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 155 156 /* 157 * Bits in async error register (errors from DVMA or Sun-4 cache 158 * writeback). The corresponding bit is also set in the sync error reg. 159 * 160 * A writeback invalid error means there is a bug in the PTE manager. 161 * 162 * The word is that the async error register does not work right. 163 */ 164 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 165 #define AER_TIMEOUT 0x20 /* bus timeout */ 166 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 167 168 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 169 170 /* 171 * Bits in system enable register. 172 */ 173 #define SYSEN_DVMA 0x20 /* enable dvma */ 174 #define SYSEN_CACHE 0x10 /* enable cache */ 175 #define SYSEN_IOCACHE 0x40 /* enable IO cache */ 176 #define SYSEN_RESET 0x04 /* reset the hardware */ 177 #define SYSEN_RESETVME 0x02 /* reset the VME bus */ 178 #endif 179 180 #if defined(SUN4M) 181 #define SRMMU_PCR 0x00000000 /* processor control register */ 182 #define SRMMU_CXTPTR 0x00000100 /* context table pointer register */ 183 #define SRMMU_CXR 0x00000200 /* context register */ 184 #define SRMMU_SFSTAT 0x00000300 /* syncronous fault status reg */ 185 #define SRMMU_SFADDR 0x00000400 /* syncronous fault address reg */ 186 #define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */ 187 #endif 188