1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 43 * 44 * from: Header: ctlreg.h,v 1.6 93/04/27 14:29:07 torek Exp 45 * $Id: ctlreg.h,v 1.2 1994/05/05 07:51:25 deraadt Exp $ 46 */ 47 48 /* 49 * Sun-4, 4c, and 4m control registers. (includes address space definitions 50 * and some registers in control space). 51 */ 52 53 /* 0x00 unused */ 54 /* 0x01 unused */ 55 #if defined(SUN4C) || defined(SUN4) 56 #define ASI_CONTROL 0x02 /* cache enable, context reg, etc */ 57 #define ASI_SEGMAP 0x03 /* segment maps (so we can reach each pmeg) */ 58 #define ASI_PTE 0x04 /* PTE space (pmegs) */ 59 #define ASI_HWFLUSHSEG 0x05 /* hardware assisted version of FLUSHSEG */ 60 #define ASI_HWFLUSHPG 0x06 /* hardware assisted version of FLUSHPG */ 61 #define ASI_HWFLUSHCTX 0x07 /* hardware assisted version of FLUSHCTX */ 62 #endif 63 #if defined(SUN4M) || defined(SUN4M) 64 #define ASI_SRMMUFP 0x03 /* ref mmu flush/probe */ 65 #define ASI_SRMMU 0x04 /* ref mmu registers */ 66 #define ASI_SRMMUDIAG 0x06 67 #endif 68 69 #define ASI_USERI 0x08 /* I-space (user) */ 70 #define ASI_KERNELI 0x09 /* I-space (kernel) */ 71 #define ASI_USERD 0x0a /* D-space (user) */ 72 #define ASI_KERNELD 0x0b /* D-space (kernel) */ 73 74 #if defined(SUN4C) || defined(SUN4) 75 #define ASI_FLUSHSEG 0x0c /* causes hardware to flush cache segment */ 76 #define ASI_FLUSHPG 0x0d /* causes hardware to flush cache page */ 77 #define ASI_FLUSHCTX 0x0e /* causes hardware to flush cache context */ 78 #if defined(SUN4) 79 #define ASI_DCACHE 0x0f /* flush data cache; not used on 4c */ 80 #endif 81 #endif 82 83 #if defined(SUN4M) 84 #define ASI_ICACHETAG 0x0c /* instruction cache tag */ 85 #define ASI_ICACHEDATA 0x0d /* instruction cache data */ 86 #define ASI_DCACHETAG 0x0e /* data cache tag */ 87 #define ASI_DCACHEDATA 0x0f /* data cache data */ 88 #define ASI_IDCACHELFP 0x10 /* ms2 only: flush i&d cache line (page) */ 89 #define ASI_IDCACHELFS 0x11 /* ms2 only: flush i&d cache line (seg) */ 90 #define ASI_IDCACHELFR 0x12 /* ms2 only: flush i&d cache line (reg) */ 91 #define ASI_IDCACHELFC 0x13 /* ms2 only: flush i&d cache line (ctxt) */ 92 #define ASI_IDCACHELFU 0x14 /* ms2 only: flush i&d cache line (user) */ 93 #define ASI_SRMMUTLB 0x20 /* sun ref mmu bypass, ie. direct tlb access */ 94 #define ASI_ICACHECLR 0x36 /* ms1 only: instruction cache flash clear */ 95 #define ASI_DCACHECLR 0x37 /* ms1 only: data cache clear */ 96 #define ASI_DCACHEDIAG 0x39 /* data cache diagnostic register access */ 97 #endif 98 99 #if defined(SUN4) || defined(SUN4C) 100 /* registers in the control space */ 101 #define AC_CONTEXT 0x30000000 /* context register (byte) */ 102 #define AC_SYSENABLE 0x40000000 /* system enable register (byte) */ 103 #define AC_CACHETAGS 0x80000000 /* cache tag base address */ 104 #define AC_SERIAL 0xf0000000 /* special serial port sneakiness */ 105 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 106 #endif 107 108 #if defined(SUN4) 109 #define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */ 110 #define AC_BUS_ERR 0x60000000 /* bus error register */ 111 #define AC_DIAG_REG 0x70000000 /* diagnostic reg */ 112 #define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */ 113 #endif 114 115 #if defined(SUN4C) 116 #define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */ 117 #define AC_SYNC_VA 0x60000004 /* sync error virtual addr */ 118 #define AC_ASYNC_ERR 0x60000008 /* async error reg */ 119 #define AC_ASYNC_VA 0x6000000c /* async error virtual addr */ 120 #define AC_CACHEDATA 0x90000000 /* cached data */ 121 122 /* 123 * Bits in sync error register. Reading the register clears these; 124 * otherwise they accumulate. The error(s) occurred at the virtual 125 * address stored in the sync error address register, and may have 126 * been due to, e.g., what would usually be called a page fault. 127 * Worse, the bits accumulate during instruction prefetch, so 128 * various bits can be on that should be off. 129 */ 130 #define SER_WRITE 0x8000 /* error occurred during write */ 131 #define SER_INVAL 0x80 /* PTE had PG_V off */ 132 #define SER_PROT 0x40 /* operation violated PTE prot */ 133 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 134 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 135 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 136 #define SER_SZERR 0x02 /* size error, whatever that is */ 137 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 138 139 #define SER_BITS \ 140 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 141 142 /* 143 * Bits in async error register (errors from DVMA or Sun-4 cache 144 * writeback). The corresponding bit is also set in the sync error reg. 145 * 146 * A writeback invalid error means there is a bug in the PTE manager. 147 * 148 * The word is that the async error register does not work right. 149 */ 150 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 151 #define AER_TIMEOUT 0x20 /* bus timeout */ 152 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 153 154 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 155 156 #endif /* SUN4C */ 157 158 #if defined(SUN4) || defined(SUN4C) 159 /* 160 * Bits in system enable register. 161 */ 162 #define SYSEN_DVMA 0x20 /* enable dvma */ 163 #define SYSEN_CACHE 0x10 /* enable cache */ 164 #define SYSEN_RESET 0x04 /* reset the hardware */ 165 #endif 166 167 #if defined(SUN4M) 168 #define SRMMU_PCR 0x00000000 /* processor control register */ 169 #define SRMMU_CXTPTR 0x00000100 /* context table pointer register */ 170 #define SRMMU_CXR 0x00000200 /* context register */ 171 #define SRMMU_SFSTAT 0x00000300 /* syncronous fault status reg */ 172 #define SRMMU_SFADDR 0x00000400 /* syncronous fault address reg */ 173 #define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */ 174 #endif 175