1 /* $NetBSD: ctlreg.h,v 1.12 1996/05/16 15:57:00 abrown Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the University of 30 * California, Berkeley and its contributors. 31 * 4. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 48 */ 49 50 /* 51 * Sun4m support by Aaron Brown, Harvard University. 52 * Changes Copyright (c) 1995 The President and Fellows of Harvard College. 53 * All rights reserved. 54 */ 55 56 /* 57 * Sun 4, 4c, and 4m control registers. (includes address space definitions 58 * and some registers in control space). 59 */ 60 61 /* 62 * The Alternate address spaces. 63 */ 64 65 /* 0x00 unused */ 66 /* 0x01 unused */ 67 #define ASI_CONTROL 0x02 /* cache enable, context reg, etc */ 68 #define ASI_SEGMAP 0x03 /* [4/4c] segment maps */ 69 #define ASI_SRMMUFP 0x03 /* [4m] ref mmu flush/probe */ 70 #define ASI_PTE 0x04 /* [4/4c] PTE space (pmegs) */ 71 #define ASI_SRMMU 0x04 /* [4m] ref mmu registers */ 72 #define ASI_REGMAP 0x06 /* [4/3-level MMU ] region maps */ 73 #define ASI_HWFLUSHSEG 0x05 /* [4/4c] hardware assisted version of FLUSHSEG */ 74 #define ASI_HWFLUSHPG 0x06 /* [4/4c] hardware assisted version of FLUSHPG */ 75 #define ASI_SRMMUDIAG 0x06 /* [4m] */ 76 #define ASI_HWFLUSHCTX 0x07 /* [4/4c] hardware assisted version of FLUSHCTX */ 77 78 #define ASI_USERI 0x08 /* I-space (user) */ 79 #define ASI_KERNELI 0x09 /* I-space (kernel) */ 80 #define ASI_USERD 0x0a /* D-space (user) */ 81 #define ASI_KERNELD 0x0b /* D-space (kernel) */ 82 83 #define ASI_FLUSHREG 0x7 /* [4/4c] flush cache by region */ 84 #define ASI_FLUSHSEG 0x0c /* [4/4c] flush cache by segment */ 85 #define ASI_FLUSHPG 0x0d /* [4/4c] flush cache by page */ 86 #define ASI_FLUSHCTX 0x0e /* [4/4c] flush cache by context */ 87 88 #define ASI_DCACHE 0x0f /* [4] flush data cache */ 89 90 #define ASI_ICACHETAG 0x0c /* [4m] instruction cache tag */ 91 #define ASI_ICACHEDATA 0x0d /* [4m] instruction cache data */ 92 #define ASI_DCACHETAG 0x0e /* [4m] data cache tag */ 93 #define ASI_DCACHEDATA 0x0f /* [4m] data cache data */ 94 #define ASI_IDCACHELFP 0x10 /* [4m] ms2 only: flush i&d cache line (page) */ 95 #define ASI_IDCACHELFS 0x11 /* [4m] ms2 only: flush i&d cache line (seg) */ 96 #define ASI_IDCACHELFR 0x12 /* [4m] ms2 only: flush i&d cache line (reg) */ 97 #define ASI_IDCACHELFC 0x13 /* [4m] ms2 only: flush i&d cache line (ctxt) */ 98 #define ASI_IDCACHELFU 0x14 /* [4m] ms2 only: flush i&d cache line (user) */ 99 #define ASI_BYPASS 0x20 /* [4m] sun ref mmu bypass, 100 ie. direct phys access */ 101 #define ASI_ICACHECLR 0x36 /* [4m] ms1 only: I-cache flash clear */ 102 #define ASI_DCACHECLR 0x37 /* [4m] ms1 only: D-cache flash clear */ 103 #define ASI_DCACHEDIAG 0x39 /* [4m] data cache diagnostic register access */ 104 105 /* 106 * [4/4c] Registers in the control space (ASI_CONTROL). 107 */ 108 #define AC_IDPROM 0x00000000 /* [4] ID PROM */ 109 #define AC_CONTEXT 0x30000000 /* [4/4c] context register (byte) */ 110 #define AC_SYSENABLE 0x40000000 /* [4/4c] system enable register (byte) */ 111 #define AC_DVMA_ENABLE 0x50000000 /* [4] enable user dvma */ 112 #define AC_BUS_ERR 0x60000000 /* [4] bus error register */ 113 #define AC_SYNC_ERR 0x60000000 /* [4c] sync (memory) error reg */ 114 #define AC_SYNC_VA 0x60000004 /* [4c] sync error virtual addr */ 115 #define AC_ASYNC_ERR 0x60000008 /* [4c] async error reg */ 116 #define AC_ASYNC_VA 0x6000000c /* [4c] async error virtual addr */ 117 #define AC_DIAG_REG 0x70000000 /* [4] diagnostic reg */ 118 #define AC_CACHETAGS 0x80000000 /* [4/4c?] cache tag base address */ 119 #define AC_CACHEDATA 0x90000000 /* [4] cached data [sun4/400?] */ 120 #define AC_DVMA_MAP 0xd0000000 /* [4] user dvma map entries */ 121 #define AC_VMEINTVEC 0xe0000000 /* [4] vme interrupt vector */ 122 #define AC_SERIAL 0xf0000000 /* [4/4c] special serial port sneakiness */ 123 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 124 125 /* XXX: does not belong here */ 126 #define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */ 127 128 /* 129 * [4/4c] 130 * Bits in sync error register. Reading the register clears these; 131 * otherwise they accumulate. The error(s) occurred at the virtual 132 * address stored in the sync error address register, and may have 133 * been due to, e.g., what would usually be called a page fault. 134 * Worse, the bits accumulate during instruction prefetch, so 135 * various bits can be on that should be off. 136 */ 137 #define SER_WRITE 0x8000 /* error occurred during write */ 138 #define SER_INVAL 0x80 /* PTE had PG_V off */ 139 #define SER_PROT 0x40 /* operation violated PTE prot */ 140 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 141 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 142 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 143 #define SER_SZERR 0x02 /* [4/vme?] size error, whatever that is */ 144 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 145 146 #define SER_BITS \ 147 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 148 149 /* 150 * [4/4c] 151 * Bits in async error register (errors from DVMA or Sun-4 cache 152 * writeback). The corresponding bit is also set in the sync error reg. 153 * 154 * A writeback invalid error means there is a bug in the PTE manager. 155 * 156 * The word is that the async error register does not work right. 157 */ 158 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 159 #define AER_TIMEOUT 0x20 /* bus timeout */ 160 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 161 162 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 163 164 /* 165 * [4/4c] Bits in system enable register. 166 */ 167 #define SYSEN_DVMA 0x20 /* Enable dvma */ 168 #define SYSEN_CACHE 0x10 /* Enable cache */ 169 #define SYSEN_IOCACHE 0x40 /* Enable IO cache */ 170 #define SYSEN_VIDEO 0x08 /* Enable on-board video */ 171 #define SYSEN_RESET 0x04 /* Reset the hardware */ 172 #define SYSEN_RESETVME 0x02 /* Reset the VME bus */ 173 174 175 /* 176 * [4m] Bits in ASI_CONTROL? space, sun4m only. 177 */ 178 #define MXCC_ENABLE_ADDR 0x1c00a00 /* Enable register for MXCC */ 179 #define MXCC_ENABLE_BIT 0x4 /* Enable bit for MXCC */ 180 181 /* 182 * Bits in ASI_SRMMUFP space. 183 * Bits 8-11 determine the type of flush/probe. 184 * Address bits 12-31 hold the page frame. 185 */ 186 #define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */ 187 #define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */ 188 #define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/ 189 #define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */ 190 #define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */ 191 192 /* 193 * [4m] Registers and bits in the SPARC Reference MMU (ASI_SRMMU). 194 */ 195 #define SRMMU_PCR 0x00000000 /* Processor control register */ 196 #define SRMMU_CXTPTR 0x00000100 /* Context table pointer register */ 197 #define SRMMU_CXR 0x00000200 /* Context register */ 198 #define SRMMU_SFSTAT 0x00000300 /* Synchronous fault status reg */ 199 #define SRMMU_SFADDR 0x00000400 /* Synchronous fault address reg */ 200 #define SRMMU_AFSTAT 0x00000500 /* Asynchronous fault status reg (HS) */ 201 #define SRMMU_AFADDR 0x00000600 /* Asynchronous fault address reg (HS)*/ 202 #define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */ 203 204 /* [4m] Bits in SRMMU control register */ 205 #define SRMMU_PCR_ME 0x00000001 /* MMU Enable */ 206 #define SRMMU_PCR_NF 0x00000002 /* Fault inhibit bit */ 207 #define SRMMU_PCR_PSO 0x00000080 /* Partial Store Ordering enable */ 208 #define SRMMU_PCR_CE 0x00000100 /* HS: Cache enable bit (HyperSPARC) */ 209 #define SRMMU_PCR_DCE 0x00000100 /* SS: Data cache enable bit */ 210 #define SRMMU_PCR_ICE 0x00000200 /* SS: SuperSPARC instr. cache enable */ 211 #define SRMMU_PCR_CM 0x00000400 /* HS: Cache mode: 1 == write-back */ 212 #define SRMMU_PCR_SB 0x00000400 /* SS: Store buffer enable bit */ 213 #define SRMMU_PCR_MR 0x00000800 /* HS: Memory reflection: 1 == on */ 214 #define SRMMU_PCR_MB 0x00000800 /* SS: MBus mode: 0=MXCC, 1=no MXCC */ 215 #define SRMMU_PCR_CS 0x00001000 /* HS: cache size: 1==256k, 0==128k */ 216 #define SRMMU_PCR_PE 0x00001000 /* SS: Enable memory parity checking */ 217 #define SRMMU_PCR_C 0x00002000 /* HS: enable cache when MMU off */ 218 #define SRMMU_PCR_SSBM 0x00002000 /* SS: 1 iff booting */ 219 #define SRMMU_PCR_HSBM 0x00004000 /* HS: 1 iff booting */ 220 #define SRMMU_PCR_SSSE 0x00004000 /* SS: Coherent bus snoop enable */ 221 #define SRMMU_PCR_AC 0x00008000 /* SS: 1=cache non-MMU accesses */ 222 #define SRMMU_PCR_TC 0x00010000 /* SS: 1=cache table walks */ 223 #define SRMMU_PCR_MID 0x00078000 /* HS: MBus module ID MID<3:0> */ 224 #define SRMMU_PCR_WBE 0x00080000 /* HS: Write buffer enable */ 225 #define SRMMU_PCR_HSSE 0x00100000 /* HS: Coherent bus snoop enable */ 226 #define SRMMU_PCR_CWR 0x00200000 /* HS: Cache wrap enable */ 227 #define SRMMU_PCR_VER 0x0f000000 /* Version of MMU implementation */ 228 #define SRMMU_PCR_IMPL 0xf0000000 /* Implementation number of MMU */ 229 230 #ifdef notyet 231 #define SRMMU_PCR_INITIAL (SRMMU_PCR_ME | SRMMU_PCR_TC) 232 #endif 233 234 /* [4m] Bits in the Synchronous Fault Status Register */ 235 #define SFSR_EM 0x00020000 /* Error mode watchdog reset occurred */ 236 #define SFSR_CS 0x00010000 /* Control Space error */ 237 #define SFSR_PERR 0x00006000 /* Parity error code */ 238 #define SFSR_SB 0x00008000 /* SS: Store Buffer Error */ 239 #define SFSR_P 0x00004000 /* SS: Parity error */ 240 #define SFSR_UC 0x00001000 /* Uncorrectable error */ 241 #define SFSR_TO 0x00000800 /* S-Bus timeout */ 242 #define SFSR_BE 0x00000400 /* S-Bus bus error */ 243 #define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */ 244 #define SFSR_AT 0x000000e0 /* Access type */ 245 #define SFSR_FT 0x0000001c /* Fault type */ 246 #define SFSR_FAV 0x00000002 /* Fault Address is valid */ 247 #define SFSR_OW 0x00000001 /* Overwritten with new fault */ 248 249 #define SFSR_BITS \ 250 "\20\21CSERR\17PARITY\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\2FAV\1OW" 251 252 /* [4m] Synchronous Fault Types */ 253 #define SFSR_FT_NONE (0 << 2) /* no fault */ 254 #define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */ 255 #define SFSR_FT_PROTERR (2 << 2) /* protection fault */ 256 #define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */ 257 #define SFSR_FT_TRANSERR (4 << 2) /* translation fault */ 258 #define SFSR_FT_BUSERR (5 << 2) /* access bus error */ 259 #define SFSR_FT_INTERR (6 << 2) /* internal error */ 260 #define SFSR_FT_RESERVED (7 << 2) /* reserved */ 261 262 /* [4m] Synchronous Fault Access Types */ 263 #define SFSR_AT_LDUDATA (0 << 5) /* Load user data */ 264 #define SFSR_AT_LDSDATA (1 << 5) /* Load supervisor data */ 265 #define SFSR_AT_LDUTEXT (2 << 5) /* Load user text */ 266 #define SFSR_AT_LDSTEXT (3 << 5) /* Load supervisor text */ 267 #define SFSR_AT_STUDATA (4 << 5) /* Store user data */ 268 #define SFSR_AT_STSDATA (5 << 5) /* Store supervisor data */ 269 #define SFSR_AT_STUTEXT (6 << 5) /* Store user text */ 270 #define SFSR_AT_STSTEXT (7 << 5) /* Store supervisor text */ 271 #define SFSR_AT_SUPERVISOR (1 << 5) /* Set iff supervisor */ 272 #define SFSR_AT_TEXT (2 << 5) /* Set iff text */ 273 #define SFSR_AT_STORE (4 << 5) /* Set iff store */ 274 275 /* [4m] Synchronous Fault PT Levels */ 276 #define SFSR_LVL_0 (0 << 8) /* Context table entry */ 277 #define SFSR_LVL_1 (1 << 8) /* Region table entry */ 278 #define SFSR_LVL_2 (2 << 8) /* Segment table entry */ 279 #define SFSR_LVL_3 (3 << 8) /* Page table entry */ 280 281 /* [4m] Asynchronous Fault Status Register bits */ 282 #define AFSR_AFO 0x00000001 /* Async. fault occurred */ 283 #define AFSR_AFA 0x000000f0 /* Bits <35:32> of faulting phys addr */ 284 #define AFSR_AFA_RSHIFT 4 /* Shift to get AFA to bit 0 */ 285 #define AFSR_AFA_LSHIFT 28 /* Shift to get AFA to bit 32 */ 286 #define AFSR_BE 0x00000400 /* Bus error */ 287 #define AFSR_TO 0x00000800 /* Bus timeout */ 288 #define AFSR_UC 0x00001000 /* Uncorrectable error */ 289 #define AFSR_SE 0x00002000 /* System error */ 290 291 #define AFSR_BITS "\20\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\1AFO" 292 293 /* [4m] TLB Replacement Control Register bits */ 294 #define TLBC_DISABLE 0x00000020 /* Disable replacement counter */ 295 #define TLBC_RCNTMASK 0x0000001f /* Replacement counter (0-31) */ 296