1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 43 * 44 * from: Header: ctlreg.h,v 1.6 93/04/27 14:29:07 torek Exp 45 * $Id: ctlreg.h,v 1.1 1993/10/02 10:23:07 deraadt Exp $ 46 */ 47 48 /* 49 * Sun-4 (sort of) and 4c (Campus, i.e., SparcStation) control registers 50 * (includes address space definitions and registers in control space). 51 * 52 * Address space identifiers are 8 bits (0 through 255), but we 53 * only use four of them. 54 */ 55 56 /* 0 unused */ 57 /* 1 unused */ 58 #define ASI_CONTROL 2 /* cache enable, context reg, etc */ 59 #define ASI_SEGMAP 3 /* segment maps (so we can reach each pmeg) */ 60 #define ASI_PTE 4 /* PTE space (pmegs) */ 61 #define ASI_HWFLUSHSEG 5 /* hardware assisted version of FLUSHSEG */ 62 #define ASI_HWFLUSHPG 6 /* hardware assisted version of FLUSHPG */ 63 #define ASI_HWFLUSHCTX 7 /* hardware assisted version of FLUSHCTX */ 64 #define ASI_USERI 8 /* I-space (user) */ 65 #define ASI_KERNELI 9 /* I-space (kernel) */ 66 #define ASI_USERD 10 /* D-space (user) */ 67 #define ASI_KERNELD 11 /* D-space (kernel) */ 68 #define ASI_FLUSHSEG 12 /* causes hardware to flush cache segment */ 69 #define ASI_FLUSHPG 13 /* causes hardware to flush cache page */ 70 #define ASI_FLUSHCTX 14 /* causes hardware to flush cache context */ 71 #ifdef SUN4 72 #define ASI_DCACHE 15 /* flush data cache; not used on 4c */ 73 #endif 74 /* 16 through 255 unused (and probably wrap, but who cares?) */ 75 76 /* registers in the control space */ 77 #define AC_CONTEXT 0x30000000 /* context register (byte) */ 78 #define AC_SYSENABLE 0x40000000 /* system enable register (byte) */ 79 #define AC_CACHETAGS 0x80000000 /* cache tag base address */ 80 #define AC_SERIAL 0xf0000000 /* special serial port sneakiness */ 81 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 82 83 #ifdef SUN4 84 #define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */ 85 #define AC_BUS_ERR 0x60000000 /* bus error register */ 86 #define AC_DIAG_REG 0x70000000 /* diagnostic reg */ 87 #define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */ 88 #endif 89 90 #ifdef SUN4C 91 #define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */ 92 #define AC_SYNC_VA 0x60000004 /* sync error virtual addr */ 93 #define AC_ASYNC_ERR 0x60000008 /* async error reg */ 94 #define AC_ASYNC_VA 0x6000000c /* async error virtual addr */ 95 #define AC_CACHEDATA 0x90000000 /* cached data */ 96 97 /* 98 * Bits in sync error register. Reading the register clears these; 99 * otherwise they accumulate. The error(s) occurred at the virtual 100 * address stored in the sync error address register, and may have 101 * been due to, e.g., what would usually be called a page fault. 102 * Worse, the bits accumulate during instruction prefetch, so 103 * various bits can be on that should be off. 104 */ 105 #define SER_WRITE 0x8000 /* error occurred during write */ 106 #define SER_INVAL 0x80 /* PTE had PG_V off */ 107 #define SER_PROT 0x40 /* operation violated PTE prot */ 108 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 109 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 110 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 111 #define SER_SZERR 0x02 /* size error, whatever that is */ 112 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 113 114 #define SER_BITS \ 115 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 116 117 /* 118 * Bits in async error register (errors from DVMA or Sun-4 cache 119 * writeback). The corresponding bit is also set in the sync error reg. 120 * 121 * A writeback invalid error means there is a bug in the PTE manager. 122 * 123 * The word is that the async error register does not work right. 124 */ 125 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 126 #define AER_TIMEOUT 0x20 /* bus timeout */ 127 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 128 129 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 130 131 #endif /* SUN4C */ 132 133 /* 134 * Bits in system enable register. 135 */ 136 #define SYSEN_DVMA 0x20 /* enable dvma */ 137 #define SYSEN_CACHE 0x10 /* enable cache */ 138 #define SYSEN_RESET 0x04 /* reset the hardware */ 139