xref: /netbsd-src/sys/arch/sparc/include/cpu.h (revision ae1bfcddc410612bc8c58b807e1830becb69a24c)
1 /*
2  * Copyright (c) 1992, 1993
3  *	The Regents of the University of California.  All rights reserved.
4  *
5  * This software was developed by the Computer Systems Engineering group
6  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7  * contributed to Berkeley.
8  *
9  * All advertising materials mentioning features or use of this software
10  * must display the following acknowledgement:
11  *	This product includes software developed by the University of
12  *	California, Lawrence Berkeley Laboratory.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in the
21  *    documentation and/or other materials provided with the distribution.
22  * 3. All advertising materials mentioning features or use of this software
23  *    must display the following acknowledgement:
24  *	This product includes software developed by the University of
25  *	California, Berkeley and its contributors.
26  * 4. Neither the name of the University nor the names of its contributors
27  *    may be used to endorse or promote products derived from this software
28  *    without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40  * SUCH DAMAGE.
41  *
42  *	@(#)cpu.h	8.4 (Berkeley) 1/5/94
43  *
44  * from: Header: cpu.h,v 1.12 93/05/25 10:36:34 torek Exp  (LBL)
45  * $Id: cpu.h,v 1.7 1994/05/19 08:23:17 deraadt Exp $
46  */
47 
48 #ifndef _CPU_H_
49 #define _CPU_H_
50 
51 /*
52  * CTL_MACHDEP definitinos.
53  */
54 #define	CPU_MAXID	1	/* no valid machdep ids */
55 
56 #define	CTL_MACHDEP_NAMES { \
57 	{ 0, 0 }, \
58 }
59 
60 #ifdef KERNEL
61 /*
62  * Exported definitions unique to SPARC cpu support.
63  */
64 
65 #include <machine/psl.h>
66 #include <sparc/sparc/intreg.h>
67 
68 /*
69  * definitions of cpu-dependent requirements
70  * referenced in generic code
71  */
72 #define	COPY_SIGCODE		/* copy sigcode above user stack in exec */
73 
74 #define	cpu_exec(p)	/* nothing */
75 #define	cpu_swapin(p)	/* nothing */
76 #define	cpu_wait(p)	/* nothing */
77 
78 /*
79  * See syscall() for an explanation of the following.  Note that the
80  * locore bootstrap code follows the syscall stack protocol.  The
81  * framep argument is unused.
82  */
83 #define cpu_set_init_frame(p, fp) \
84 	(p)->p_md.md_tf = (struct trapframe *) \
85 	    ((caddr_t)(p)->p_addr + UPAGES * NBPG - sizeof(struct trapframe))
86 
87 /*
88  * Arguments to hardclock, softclock and gatherstats encapsulate the
89  * previous machine state in an opaque clockframe.  The ipl is here
90  * as well for strayintr (see locore.s:interrupt and intr.c:strayintr).
91  * Note that CLKF_INTR is valid only if CLKF_USERMODE is false.
92  */
93 struct clockframe {
94 	u_int	psr;		/* psr before interrupt, excluding PSR_ET */
95 	u_int	pc;		/* pc at interrupt */
96 	u_int	npc;		/* npc at interrupt */
97 	u_int	ipl;		/* actual interrupt priority level */
98 	u_int	fp;		/* %fp at interrupt */
99 };
100 typedef struct clockframe clockframe;
101 
102 extern int eintstack[];
103 
104 #define	CLKF_USERMODE(framep)	(((framep)->psr & PSR_PS) == 0)
105 #define	CLKF_BASEPRI(framep)	(((framep)->psr & PSR_PIL) == 0)
106 #define	CLKF_PC(framep)		((framep)->pc)
107 #define	CLKF_INTR(framep)	((framep)->fp < (u_int)eintstack)
108 
109 /*
110  * Software interrupt request `register'.
111  */
112 union sir {
113 	int	sir_any;
114 	char	sir_which[4];
115 } sir;
116 
117 #define SIR_NET		0
118 #define SIR_CLOCK	1
119 
120 #define	setsoftint()	ienab_bis(IE_L1)
121 #define setsoftnet()	(sir.sir_which[SIR_NET] = 1, setsoftint())
122 #define setsoftclock()	(sir.sir_which[SIR_CLOCK] = 1, setsoftint())
123 
124 int	want_ast;
125 
126 /*
127  * Preempt the current process if in interrupt from user mode,
128  * or after the current trap/syscall if in system mode.
129  */
130 int	want_resched;		/* resched() was called */
131 #define	need_resched()		(want_resched = 1, want_ast = 1)
132 
133 /*
134  * Give a profiling tick to the current process when the user profiling
135  * buffer pages are invalid.  On the sparc, request an ast to send us
136  * through trap(), marking the proc as needing a profiling tick.
137  */
138 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, want_ast = 1)
139 
140 /*
141  * Notify the current process (p) that it has a signal pending,
142  * process as soon as possible.
143  */
144 #define	signotify(p)		(want_ast = 1)
145 
146 /*
147  * Only one process may own the FPU state.
148  *
149  * XXX this must be per-cpu (eventually)
150  */
151 struct	proc *fpproc;		/* FPU owner */
152 int	foundfpu;		/* true => we have an FPU */
153 
154 /*
155  * Interrupt handler chains.  Interrupt handlers should return 0 for
156  * ``not me'' or 1 (``I took care of it'').  intr_establish() inserts a
157  * handler into the list.  The handler is called with its (single)
158  * argument, or with a pointer to a clockframe if ih_arg is NULL.
159  */
160 struct intrhand {
161 	int	(*ih_fun) __P((void *));
162 	void	*ih_arg;
163 	struct	intrhand *ih_next;
164 } *intrhand[15];
165 
166 void	intr_establish __P((int level, struct intrhand *));
167 
168 /*
169  * intr_fasttrap() is a lot like intr_establish, but is used for ``fast''
170  * interrupt vectors (vectors that are not shared and are handled in the
171  * trap window).  Such functions must be written in assembly.
172  */
173 void	intr_fasttrap __P((int level, void (*vec)(void)));
174 
175 /*
176  *
177  * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
178  * of the trap vector table.  The next eight bits are supplied by the
179  * hardware when the trap occurs, and the bottom four bits are always
180  * zero (so that we can shove up to 16 bytes of executable code---exactly
181  * four instructions---into each trap vector).
182  *
183  * The hardware allocates half the trap vectors to hardware and half to
184  * software.
185  *
186  * Traps have priorities assigned (lower number => higher priority).
187  */
188 
189 struct trapvec {
190 	int	tv_instr[4];		/* the four instructions */
191 };
192 extern struct trapvec trapbase[256];	/* the 256 vectors */
193 
194 #endif /* KERNEL */
195 #endif /* _CPU_H_ */
196