1 /* $NetBSD: cpu.h,v 1.87 2009/10/21 21:12:02 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #ifdef _KERNEL 56 /* 57 * Exported definitions unique to SPARC cpu support. 58 */ 59 60 #if defined(_KERNEL_OPT) 61 #include "opt_multiprocessor.h" 62 #include "opt_lockdebug.h" 63 #include "opt_sparc_arch.h" 64 #endif 65 66 #include <machine/intr.h> 67 #include <machine/psl.h> 68 #include <sparc/sparc/cpuvar.h> 69 #include <sparc/sparc/intreg.h> 70 71 /* 72 * definitions of cpu-dependent requirements 73 * referenced in generic code 74 */ 75 #define curcpu() (cpuinfo.ci_self) 76 #define curlwp (cpuinfo.ci_curlwp) 77 #define CPU_IS_PRIMARY(ci) ((ci)->master) 78 79 #define cpu_number() (cpuinfo.ci_cpuid) 80 void cpu_proc_fork(struct proc *, struct proc *); 81 82 #if defined(MULTIPROCESSOR) 83 void cpu_boot_secondary_processors(void); 84 #endif 85 86 /* 87 * Arguments to hardclock, softclock and statclock encapsulate the 88 * previous machine state in an opaque clockframe. The ipl is here 89 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 90 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 91 */ 92 struct clockframe { 93 u_int psr; /* psr before interrupt, excluding PSR_ET */ 94 u_int pc; /* pc at interrupt */ 95 u_int npc; /* npc at interrupt */ 96 u_int ipl; /* actual interrupt priority level */ 97 u_int fp; /* %fp at interrupt */ 98 }; 99 typedef struct clockframe clockframe; 100 101 extern int eintstack[]; 102 103 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 104 #define CLKF_LOPRI(framep,n) (((framep)->psr & PSR_PIL) < (n) << 8) 105 #define CLKF_PC(framep) ((framep)->pc) 106 #if defined(MULTIPROCESSOR) 107 #define CLKF_INTR(framep) \ 108 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 109 (framep)->fp < (u_int)cpuinfo.eintstack) 110 #else 111 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 112 #endif 113 114 void sparc_softintr_init(void); 115 116 /* 117 * Preempt the current process on the target CPU if in interrupt from 118 * user mode, or after the current trap/syscall if in system mode. 119 */ 120 #define cpu_need_resched(ci, flags) do { \ 121 (ci)->ci_want_resched = 1; \ 122 (ci)->ci_want_ast = 1; \ 123 \ 124 /* Just interrupt the target CPU, so it can notice its AST */ \ 125 if (((flags) & RESCHED_IMMED) || (ci)->ci_cpuid != cpu_number()) \ 126 XCALL0(sparc_noop, 1U << (ci)->ci_cpuid); \ 127 } while (/*CONSTCOND*/0) 128 129 /* 130 * Give a profiling tick to the current process when the user profiling 131 * buffer pages are invalid. On the sparc, request an ast to send us 132 * through trap(), marking the proc as needing a profiling tick. 133 */ 134 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.ci_want_ast = 1) 135 136 /* 137 * Notify the current process (p) that it has a signal pending, 138 * process as soon as possible. 139 */ 140 #define cpu_signotify(l) do { \ 141 (l)->l_cpu->ci_want_ast = 1; \ 142 \ 143 /* Just interrupt the target CPU, so it can notice its AST */ \ 144 if ((l)->l_cpu->ci_cpuid != cpu_number()) \ 145 XCALL0(sparc_noop, 1U << (l)->l_cpu->ci_cpuid); \ 146 } while (/*CONSTCOND*/0) 147 148 /* CPU architecture version */ 149 extern int cpu_arch; 150 151 /* Number of CPUs in the system */ 152 extern int sparc_ncpus; 153 154 /* 155 * Interrupt handler chains. Interrupt handlers should return 0 for 156 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 157 * handler into the list. The handler is called with its (single) 158 * argument, or with a pointer to a clockframe if ih_arg is NULL. 159 */ 160 extern struct intrhand { 161 int (*ih_fun)(void *); 162 void *ih_arg; 163 struct intrhand *ih_next; 164 int ih_classipl; 165 } *intrhand[15]; 166 167 void intr_establish(int, int, struct intrhand *, void (*)(void)); 168 void intr_disestablish(int, struct intrhand *); 169 170 void intr_lock_kernel(void); 171 void intr_unlock_kernel(void); 172 173 /* disksubr.c */ 174 struct dkbad; 175 int isbad(struct dkbad *, int, int, int); 176 177 /* machdep.c */ 178 int ldcontrolb(void *); 179 void dumpconf(void); 180 void * reserve_dumppages(void *); 181 void wcopy(const void *, void *, u_int); 182 void wzero(void *, u_int); 183 184 /* clock.c */ 185 struct timeval; 186 void lo_microtime(struct timeval *); 187 void schedintr(void *); 188 189 /* locore.s */ 190 struct fpstate; 191 void savefpstate(struct fpstate *); 192 void loadfpstate(struct fpstate *); 193 int probeget(void *, int); 194 void write_all_windows(void); 195 void write_user_windows(void); 196 void lwp_trampoline(void); 197 void lwp_setfunc_trampoline(void); 198 struct pcb; 199 void snapshot(struct pcb *); 200 struct frame *getfp(void); 201 int xldcontrolb(void *, struct pcb *); 202 void copywords(const void *, void *, size_t); 203 void qcopy(const void *, void *, size_t); 204 void qzero(void *, size_t); 205 206 /* trap.c */ 207 void kill_user_windows(struct lwp *); 208 int rwindow_save(struct lwp *); 209 210 /* cons.c */ 211 int cnrom(void); 212 213 /* zs.c */ 214 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 215 #ifdef KGDB 216 void zs_kgdb_init(void); 217 #endif 218 219 /* fb.c */ 220 void fb_unblank(void); 221 222 /* kgdb_stub.c */ 223 #ifdef KGDB 224 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 225 void kgdb_connect(int); 226 void kgdb_panic(void); 227 #endif 228 229 /* emul.c */ 230 struct trapframe; 231 int fixalign(struct lwp *, struct trapframe *); 232 int emulinstr(int, struct trapframe *); 233 234 /* cpu.c */ 235 void mp_pause_cpus(void); 236 void mp_resume_cpus(void); 237 void mp_halt_cpus(void); 238 #ifdef DDB 239 void mp_pause_cpus_ddb(void); 240 void mp_resume_cpus_ddb(void); 241 #endif 242 243 /* intr.c */ 244 u_int setitr(u_int); 245 u_int getitr(void); 246 247 248 /* 249 * 250 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 251 * of the trap vector table. The next eight bits are supplied by the 252 * hardware when the trap occurs, and the bottom four bits are always 253 * zero (so that we can shove up to 16 bytes of executable code---exactly 254 * four instructions---into each trap vector). 255 * 256 * The hardware allocates half the trap vectors to hardware and half to 257 * software. 258 * 259 * Traps have priorities assigned (lower number => higher priority). 260 */ 261 262 struct trapvec { 263 int tv_instr[4]; /* the four instructions */ 264 }; 265 266 extern struct trapvec *trapbase; /* the 256 vectors */ 267 268 #endif /* _KERNEL */ 269 #endif /* _CPU_H_ */ 270