1 /* $NetBSD: cpu.h,v 1.82 2007/10/17 19:57:13 garbled Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #define CTL_MACHDEP_NAMES { \ 56 { 0, 0 }, \ 57 { "booted_kernel", CTLTYPE_STRING }, \ 58 { "booted_device", CTLTYPE_STRING }, \ 59 { "boot_args", CTLTYPE_STRING }, \ 60 { "cpu_arch", CTLTYPE_INT }, \ 61 } 62 63 #ifdef _KERNEL 64 /* 65 * Exported definitions unique to SPARC cpu support. 66 */ 67 68 #if defined(_KERNEL_OPT) 69 #include "opt_multiprocessor.h" 70 #include "opt_lockdebug.h" 71 #include "opt_sparc_arch.h" 72 #endif 73 74 #include <machine/intr.h> 75 #include <machine/psl.h> 76 #include <sparc/sparc/cpuvar.h> 77 #include <sparc/sparc/intreg.h> 78 79 /* 80 * definitions of cpu-dependent requirements 81 * referenced in generic code 82 */ 83 #define curcpu() (cpuinfo.ci_self) 84 #define curlwp (cpuinfo.ci_curlwp) 85 #define CPU_IS_PRIMARY(ci) ((ci)->master) 86 87 #define cpu_swapin(p) /* nothing */ 88 #define cpu_swapout(p) /* nothing */ 89 #define cpu_number() (cpuinfo.ci_cpuid) 90 void cpu_proc_fork(struct proc *, struct proc *); 91 92 #if defined(MULTIPROCESSOR) 93 void cpu_boot_secondary_processors(void); 94 #endif 95 96 /* 97 * Arguments to hardclock, softclock and statclock encapsulate the 98 * previous machine state in an opaque clockframe. The ipl is here 99 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 100 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 101 */ 102 struct clockframe { 103 u_int psr; /* psr before interrupt, excluding PSR_ET */ 104 u_int pc; /* pc at interrupt */ 105 u_int npc; /* npc at interrupt */ 106 u_int ipl; /* actual interrupt priority level */ 107 u_int fp; /* %fp at interrupt */ 108 }; 109 typedef struct clockframe clockframe; 110 111 extern int eintstack[]; 112 113 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 114 #define CLKF_LOPRI(framep,n) (((framep)->psr & PSR_PIL) < (n) << 8) 115 #define CLKF_PC(framep) ((framep)->pc) 116 #if defined(MULTIPROCESSOR) 117 #define CLKF_INTR(framep) \ 118 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 119 (framep)->fp < (u_int)cpuinfo.eintstack) 120 #else 121 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 122 #endif 123 124 void softintr_init(void); 125 extern void *softnet_cookie; 126 127 #define setsoftnet() softintr_schedule(softnet_cookie); 128 129 /* 130 * Preempt the current process on the target CPU if in interrupt from 131 * user mode, or after the current trap/syscall if in system mode. 132 */ 133 #define cpu_need_resched(ci, flags) do { \ 134 (ci)->ci_want_resched = 1; \ 135 (ci)->ci_want_ast = 1; \ 136 \ 137 /* Just interrupt the target CPU, so it can notice its AST */ \ 138 if (((flags) & RESCHED_IMMED) || (ci)->ci_cpuid != cpu_number()) \ 139 XCALL0(sparc_noop, 1U << (ci)->ci_cpuid); \ 140 } while (/*CONSTCOND*/0) 141 142 /* 143 * Give a profiling tick to the current process when the user profiling 144 * buffer pages are invalid. On the sparc, request an ast to send us 145 * through trap(), marking the proc as needing a profiling tick. 146 */ 147 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.ci_want_ast = 1) 148 149 /* 150 * Notify the current process (p) that it has a signal pending, 151 * process as soon as possible. 152 */ 153 #define cpu_signotify(l) do { \ 154 struct cpu_info *_ci = (l)->l_cpu; \ 155 _ci->ci_want_ast = 1; \ 156 \ 157 /* Just interrupt the target CPU, so it can notice its AST */ \ 158 if (_ci->ci_cpuid != cpu_number()) \ 159 XCALL0(sparc_noop, 1U << _ci->ci_cpuid); \ 160 } while (/*CONSTCOND*/0) 161 162 /* CPU architecture version */ 163 extern int cpu_arch; 164 165 /* Number of CPUs in the system */ 166 extern int sparc_ncpus; 167 168 /* 169 * Interrupt handler chains. Interrupt handlers should return 0 for 170 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 171 * handler into the list. The handler is called with its (single) 172 * argument, or with a pointer to a clockframe if ih_arg is NULL. 173 */ 174 extern struct intrhand { 175 int (*ih_fun)(void *); 176 void *ih_arg; 177 struct intrhand *ih_next; 178 int ih_classipl; 179 } *intrhand[15]; 180 181 void intr_establish(int, int, struct intrhand *, void (*)(void)); 182 void intr_disestablish(int, struct intrhand *); 183 184 void intr_lock_kernel(void); 185 void intr_unlock_kernel(void); 186 187 /* disksubr.c */ 188 struct dkbad; 189 int isbad(struct dkbad *, int, int, int); 190 191 /* machdep.c */ 192 int ldcontrolb(void *); 193 void dumpconf(void); 194 void * reserve_dumppages(void *); 195 void wcopy(const void *, void *, u_int); 196 void wzero(void *, u_int); 197 198 /* clock.c */ 199 struct timeval; 200 void lo_microtime(struct timeval *); 201 void schedintr(void *); 202 203 /* locore.s */ 204 struct fpstate; 205 void savefpstate(struct fpstate *); 206 void loadfpstate(struct fpstate *); 207 int probeget(void *, int); 208 void write_all_windows(void); 209 void write_user_windows(void); 210 void lwp_trampoline(void); 211 struct pcb; 212 void snapshot(struct pcb *); 213 struct frame *getfp(void); 214 int xldcontrolb(void *, struct pcb *); 215 void copywords(const void *, void *, size_t); 216 void qcopy(const void *, void *, size_t); 217 void qzero(void *, size_t); 218 219 /* trap.c */ 220 void kill_user_windows(struct lwp *); 221 int rwindow_save(struct lwp *); 222 223 /* cons.c */ 224 int cnrom(void); 225 226 /* zs.c */ 227 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 228 #ifdef KGDB 229 void zs_kgdb_init(void); 230 #endif 231 232 /* fb.c */ 233 void fb_unblank(void); 234 235 /* kgdb_stub.c */ 236 #ifdef KGDB 237 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 238 void kgdb_connect(int); 239 void kgdb_panic(void); 240 #endif 241 242 /* emul.c */ 243 struct trapframe; 244 int fixalign(struct lwp *, struct trapframe *); 245 int emulinstr(int, struct trapframe *); 246 247 /* cpu.c */ 248 void mp_pause_cpus(void); 249 void mp_resume_cpus(void); 250 void mp_halt_cpus(void); 251 #ifdef DDB 252 void mp_pause_cpus_ddb(void); 253 void mp_resume_cpus_ddb(void); 254 #endif 255 256 /* intr.c */ 257 u_int setitr(u_int); 258 u_int getitr(void); 259 260 261 /* 262 * 263 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 264 * of the trap vector table. The next eight bits are supplied by the 265 * hardware when the trap occurs, and the bottom four bits are always 266 * zero (so that we can shove up to 16 bytes of executable code---exactly 267 * four instructions---into each trap vector). 268 * 269 * The hardware allocates half the trap vectors to hardware and half to 270 * software. 271 * 272 * Traps have priorities assigned (lower number => higher priority). 273 */ 274 275 struct trapvec { 276 int tv_instr[4]; /* the four instructions */ 277 }; 278 279 extern struct trapvec *trapbase; /* the 256 vectors */ 280 281 #endif /* _KERNEL */ 282 #endif /* _CPU_H_ */ 283