1 /* $NetBSD: cpu.h,v 1.109 2021/01/24 07:36:54 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 54 /* 55 * Exported definitions unique to SPARC cpu support. 56 */ 57 58 /* 59 * Sun-4 and Sun-4c virtual address cache. 60 * 61 * Sun-4 virtual caches come in two flavors, write-through (Sun-4c) 62 * and write-back (Sun-4). The write-back caches are much faster 63 * but require a bit more care. 64 * 65 * This is exported via sysctl so be careful changing it. 66 */ 67 enum vactype { VAC_UNKNOWN, VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK }; 68 69 /* 70 * Cache control information. 71 * 72 * This is exported via sysctl so be careful changing it. 73 */ 74 75 struct cacheinfo { 76 int c_totalsize; /* total size, in bytes */ 77 /* if split, MAX(icache,dcache) */ 78 int c_enabled; /* true => cache is enabled */ 79 int c_hwflush; /* true => have hardware flush */ 80 int c_linesize; /* line size, in bytes */ 81 /* if split, MIN(icache,dcache) */ 82 int c_l2linesize; /* log2(linesize) */ 83 int c_nlines; /* precomputed # of lines to flush */ 84 int c_physical; /* true => cache has physical 85 address tags */ 86 int c_associativity; /* # of "buckets" in cache line */ 87 int c_split; /* true => cache is split */ 88 89 int ic_totalsize; /* instruction cache */ 90 int ic_enabled; 91 int ic_linesize; 92 int ic_l2linesize; 93 int ic_nlines; 94 int ic_associativity; 95 96 int dc_totalsize; /* data cache */ 97 int dc_enabled; 98 int dc_linesize; 99 int dc_l2linesize; 100 int dc_nlines; 101 int dc_associativity; 102 103 int ec_totalsize; /* external cache info */ 104 int ec_enabled; 105 int ec_linesize; 106 int ec_l2linesize; 107 int ec_nlines; 108 int ec_associativity; 109 110 enum vactype c_vactype; 111 112 int c_flags; 113 #define CACHE_PAGETABLES 0x1 /* caching pagetables OK on (sun4m) */ 114 #define CACHE_TRAPPAGEBUG 0x2 /* trap page can't be cached (sun4) */ 115 #define CACHE_MANDATORY 0x4 /* if cache is on, don't use 116 uncached access */ 117 }; 118 119 /* Things needed by crash or the kernel */ 120 #if defined(_KERNEL) || defined(_KMEMUSER) 121 122 #if defined(_KERNEL_OPT) 123 #include "opt_multiprocessor.h" 124 #include "opt_lockdebug.h" 125 #include "opt_sparc_arch.h" 126 #endif 127 128 #include <sys/cpu_data.h> 129 #include <sys/evcnt.h> 130 131 #include <machine/intr.h> 132 #include <machine/psl.h> 133 134 #if defined(_KERNEL) 135 #include <sparc/sparc/cpuvar.h> 136 #include <sparc/sparc/intreg.h> 137 #endif 138 139 struct trapframe; 140 141 /* 142 * Message structure for Inter Processor Communication in MP systems 143 */ 144 struct xpmsg { 145 volatile int tag; 146 #define XPMSG15_PAUSECPU 1 147 #define XPMSG_FUNC 4 148 #define XPMSG_FTRP 5 149 150 volatile union { 151 /* 152 * Cross call: ask to run (*func)(arg0,arg1,arg2) 153 * or (*trap)(arg0,arg1,arg2). `trap' should be the 154 * address of a `fast trap' handler that executes in 155 * the trap window (see locore.s). 156 */ 157 struct xpmsg_func { 158 void (*func)(int, int, int); 159 void (*trap)(int, int, int); 160 int arg0; 161 int arg1; 162 int arg2; 163 } xpmsg_func; 164 } u; 165 volatile int received; 166 volatile int complete; 167 }; 168 169 /* 170 * The cpuinfo structure. This structure maintains information about one 171 * currently installed CPU (there may be several of these if the machine 172 * supports multiple CPUs, as on some Sun4m architectures). The information 173 * in this structure supersedes the old "cpumod", "mmumod", and similar 174 * fields. 175 */ 176 177 struct cpu_info { 178 /* 179 * Primary Inter-processor message area. Keep this aligned 180 * to a cache line boundary if possible, as the structure 181 * itself is one or less (32/64 byte) cache-line. 182 */ 183 struct xpmsg msg __aligned(64); 184 185 /* Scheduler flags */ 186 int ci_want_ast; 187 int ci_want_resched; 188 189 /* 190 * SPARC cpu_info structures live at two VAs: one global 191 * VA (so each CPU can access any other CPU's cpu_info) 192 * and an alias VA CPUINFO_VA which is the same on each 193 * CPU and maps to that CPU's cpu_info. Since the alias 194 * CPUINFO_VA is how we locate our cpu_info, we have to 195 * self-reference the global VA so that we can return it 196 * in the curcpu() macro. 197 */ 198 struct cpu_info * volatile ci_self; 199 200 int ci_cpuid; /* CPU index (see cpus[] array) */ 201 202 /* Context administration */ 203 int *ctx_tbl; /* [4m] SRMMU-edible context table */ 204 paddr_t ctx_tbl_pa; /* [4m] ctx table physical address */ 205 206 /* Cache information */ 207 struct cacheinfo cacheinfo; /* see above */ 208 209 /* various flags to workaround anomalies in chips */ 210 volatile int flags; /* see CPUFLG_xxx, below */ 211 212 /* Per processor counter register (sun4m only) */ 213 volatile struct counter_4m *counterreg_4m; 214 215 /* Per processor interrupt mask register (sun4m only) */ 216 volatile struct icr_pi *intreg_4m; 217 /* 218 * Send a IPI to (cpi). For Ross cpus we need to read 219 * the pending register to avoid a hardware bug. 220 */ 221 #define raise_ipi(cpi,lvl) do { \ 222 volatile int x; \ 223 (cpi)->intreg_4m->pi_set = PINTR_SINTRLEV(lvl); \ 224 x = (cpi)->intreg_4m->pi_pend; __USE(x); \ 225 } while (0) 226 227 int sun4_mmu3l; /* [4]: 3-level MMU present */ 228 #if defined(SUN4_MMU3L) 229 #define HASSUN4_MMU3L (cpuinfo.sun4_mmu3l) 230 #else 231 #define HASSUN4_MMU3L (0) 232 #endif 233 int ci_idepth; /* Interrupt depth */ 234 235 /* 236 * The following pointers point to processes that are somehow 237 * associated with this CPU--running on it, using its FPU, 238 * etc. 239 */ 240 struct lwp *ci_curlwp; /* CPU owner */ 241 struct lwp *ci_onproc; /* current user LWP / kthread */ 242 struct lwp *fplwp; /* FPU owner */ 243 244 int ci_mtx_count; 245 int ci_mtx_oldspl; 246 247 /* 248 * Idle PCB and Interrupt stack; 249 */ 250 void *eintstack; /* End of interrupt stack */ 251 #define INT_STACK_SIZE (128 * 128) /* 128 128-byte stack frames */ 252 void *redzone; /* DEBUG: stack red zone */ 253 #define REDSIZE (8*96) /* some room for bouncing */ 254 255 struct pcb *curpcb; /* CPU's PCB & kernel stack */ 256 257 /* locore defined: */ 258 void (*get_syncflt)(void); /* Not C-callable */ 259 int (*get_asyncflt)(u_int *, u_int *); 260 261 /* Synchronous Fault Status; temporary storage */ 262 struct { 263 int sfsr; 264 int sfva; 265 } syncfltdump; 266 267 /* 268 * Cache handling functions. 269 * Most cache flush function come in two flavours: one that 270 * acts only on the CPU it executes on, and another that 271 * uses inter-processor signals to flush the cache on 272 * all processor modules. 273 * The `ft_' versions are fast trap cache flush handlers. 274 */ 275 void (*cache_flush)(void *, u_int); 276 void (*vcache_flush_page)(int, int); 277 void (*sp_vcache_flush_page)(int, int); 278 void (*ft_vcache_flush_page)(int, int); 279 void (*vcache_flush_segment)(int, int, int); 280 void (*sp_vcache_flush_segment)(int, int, int); 281 void (*ft_vcache_flush_segment)(int, int, int); 282 void (*vcache_flush_region)(int, int); 283 void (*sp_vcache_flush_region)(int, int); 284 void (*ft_vcache_flush_region)(int, int); 285 void (*vcache_flush_context)(int); 286 void (*sp_vcache_flush_context)(int); 287 void (*ft_vcache_flush_context)(int); 288 289 /* The are helpers for (*cache_flush)() */ 290 void (*sp_vcache_flush_range)(int, int, int); 291 void (*ft_vcache_flush_range)(int, int, int); 292 293 void (*pcache_flush_page)(paddr_t, int); 294 void (*pure_vcache_flush)(void); 295 void (*cache_flush_all)(void); 296 297 /* Support for hardware-assisted page clear/copy */ 298 void (*zero_page)(paddr_t); 299 void (*copy_page)(paddr_t, paddr_t); 300 301 /* Virtual addresses for use in pmap copy_page/zero_page */ 302 void * vpage[2]; 303 int *vpage_pte[2]; /* pte location of vpage[] */ 304 305 void (*cache_enable)(void); 306 307 int cpu_type; /* Type: see CPUTYP_xxx below */ 308 309 /* Inter-processor message area (high priority but used infrequently) */ 310 struct xpmsg msg_lev15; 311 312 /* CPU information */ 313 int node; /* PROM node for this CPU */ 314 int mid; /* Module ID for MP systems */ 315 int mbus; /* 1 if CPU is on MBus */ 316 int mxcc; /* 1 if a MBus-level MXCC is present */ 317 const char *cpu_longname; /* CPU model */ 318 int cpu_impl; /* CPU implementation code */ 319 int cpu_vers; /* CPU version code */ 320 int mmu_impl; /* MMU implementation code */ 321 int mmu_vers; /* MMU version code */ 322 int master; /* 1 if this is bootup CPU */ 323 324 vaddr_t mailbox; /* VA of CPU's mailbox */ 325 326 int mmu_ncontext; /* Number of contexts supported */ 327 int mmu_nregion; /* Number of regions supported */ 328 int mmu_nsegment; /* [4/4c] Segments */ 329 int mmu_npmeg; /* [4/4c] Pmegs */ 330 331 /* XXX - we currently don't actually use the following */ 332 int arch; /* Architecture: CPU_SUN4x */ 333 int class; /* Class: SuperSPARC, microSPARC... */ 334 int classlvl; /* Iteration in class: 1, 2, etc. */ 335 int classsublvl; /* stepping in class (version) */ 336 337 int hz; /* Clock speed */ 338 339 /* FPU information */ 340 int fpupresent; /* true if FPU is present */ 341 int fpuvers; /* FPU revision */ 342 const char *fpu_name; /* FPU model */ 343 char fpu_namebuf[32];/* Buffer for FPU name, if necessary */ 344 345 /* XXX */ 346 volatile void *ci_ddb_regs; /* DDB regs */ 347 348 /* 349 * The following are function pointers to do interesting CPU-dependent 350 * things without having to do type-tests all the time 351 */ 352 353 /* bootup things: access to physical memory */ 354 u_int (*read_physmem)(u_int addr, int space); 355 void (*write_physmem)(u_int addr, u_int data); 356 void (*cache_tablewalks)(void); 357 void (*mmu_enable)(void); 358 void (*hotfix)(struct cpu_info *); 359 360 361 #if 0 362 /* hardware-assisted block operation routines */ 363 void (*hwbcopy)(const void *from, void *to, size_t len); 364 void (*hwbzero)(void *buf, size_t len); 365 366 /* routine to clear mbus-sbus buffers */ 367 void (*mbusflush)(void); 368 #endif 369 370 /* 371 * Memory error handler; parity errors, unhandled NMIs and other 372 * unrecoverable faults end up here. 373 */ 374 void (*memerr)(unsigned, u_int, u_int, struct trapframe *); 375 void (*idlespin)(void); 376 /* Module Control Registers */ 377 /*bus_space_handle_t*/ long ci_mbusport; 378 /*bus_space_handle_t*/ long ci_mxccregs; 379 380 u_int ci_tt; /* Last trap (if tracing) */ 381 382 /* 383 * Start/End VA's of this cpu_info region; we upload the other pages 384 * in this region that aren't part of the cpu_info to uvm. 385 */ 386 vaddr_t ci_free_sva1, ci_free_eva1, ci_free_sva2, ci_free_eva2; 387 388 struct evcnt ci_savefpstate; 389 struct evcnt ci_savefpstate_null; 390 struct evcnt ci_xpmsg_mutex_fail; 391 struct evcnt ci_xpmsg_mutex_fail_call; 392 struct evcnt ci_xpmsg_mutex_not_held; 393 struct evcnt ci_xpmsg_bogus; 394 struct evcnt ci_intrcnt[16]; 395 struct evcnt ci_sintrcnt[16]; 396 397 struct cpu_data ci_data; /* MI per-cpu data */ 398 }; 399 400 #endif /* _KERNEL || _KMEMUSER */ 401 402 /* Kernel only things. */ 403 #if defined(_KERNEL) 404 405 /* 406 * definitions of cpu-dependent requirements 407 * referenced in generic code 408 */ 409 #define cpuinfo (*(struct cpu_info *)CPUINFO_VA) 410 #define curcpu() (cpuinfo.ci_self) 411 #define curlwp (cpuinfo.ci_curlwp) 412 #define CPU_IS_PRIMARY(ci) ((ci)->master) 413 414 #define cpu_number() (cpuinfo.ci_cpuid) 415 416 void cpu_proc_fork(struct proc *, struct proc *); 417 418 #if defined(MULTIPROCESSOR) 419 void cpu_boot_secondary_processors(void); 420 #endif 421 422 /* 423 * Arguments to hardclock, softclock and statclock encapsulate the 424 * previous machine state in an opaque clockframe. The ipl is here 425 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 426 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 427 */ 428 struct clockframe { 429 u_int psr; /* psr before interrupt, excluding PSR_ET */ 430 u_int pc; /* pc at interrupt */ 431 u_int npc; /* npc at interrupt */ 432 u_int ipl; /* actual interrupt priority level */ 433 u_int fp; /* %fp at interrupt */ 434 }; 435 typedef struct clockframe clockframe; 436 437 extern int eintstack[]; 438 439 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 440 #define CLKF_LOPRI(framep,n) (((framep)->psr & PSR_PIL) < (n) << 8) 441 #define CLKF_PC(framep) ((framep)->pc) 442 #if defined(MULTIPROCESSOR) 443 #define CLKF_INTR(framep) \ 444 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 445 (framep)->fp < (u_int)cpuinfo.eintstack) 446 #else 447 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 448 #endif 449 450 void sparc_softintr_init(void); 451 452 /* 453 * Preempt the current process on the target CPU if in interrupt from 454 * user mode, or after the current trap/syscall if in system mode. 455 */ 456 #define cpu_need_resched(ci, l, flags) do { \ 457 __USE(flags); \ 458 (ci)->ci_want_ast = 1; \ 459 \ 460 /* Just interrupt the target CPU, so it can notice its AST */ \ 461 if ((flags & RESCHED_REMOTE) != 0) \ 462 XCALL0(sparc_noop, 1U << (ci)->ci_cpuid); \ 463 } while (/*CONSTCOND*/0) 464 465 /* 466 * Give a profiling tick to the current process when the user profiling 467 * buffer pages are invalid. On the sparc, request an ast to send us 468 * through trap(), marking the proc as needing a profiling tick. 469 */ 470 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.ci_want_ast = 1) 471 472 /* 473 * Notify the current process (p) that it has a signal pending, 474 * process as soon as possible. 475 */ 476 #define cpu_signotify(l) do { \ 477 (l)->l_cpu->ci_want_ast = 1; \ 478 \ 479 /* Just interrupt the target CPU, so it can notice its AST */ \ 480 if ((l)->l_cpu->ci_cpuid != cpu_number()) \ 481 XCALL0(sparc_noop, 1U << (l)->l_cpu->ci_cpuid); \ 482 } while (/*CONSTCOND*/0) 483 484 /* CPU architecture version */ 485 extern int cpu_arch; 486 487 /* Number of CPUs in the system */ 488 extern int sparc_ncpus; 489 490 /* Provide %pc of a lwp */ 491 #define LWP_PC(l) ((l)->l_md.md_tf->tf_pc) 492 493 /* Hardware cross-call mutex */ 494 extern kmutex_t xpmsg_mutex; 495 496 /* 497 * Interrupt handler chains. Interrupt handlers should return 0 for 498 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 499 * handler into the list. The handler is called with its (single) 500 * argument, or with a pointer to a clockframe if ih_arg is NULL. 501 * 502 * realfun/realarg are used to chain callers, usually with the 503 * biglock wrapper. 504 */ 505 extern struct intrhand { 506 int (*ih_fun)(void *); 507 void *ih_arg; 508 struct intrhand *ih_next; 509 int ih_classipl; 510 int (*ih_realfun)(void *); 511 void *ih_realarg; 512 } *intrhand[15]; 513 514 void intr_establish(int, int, struct intrhand *, void (*)(void), bool); 515 void intr_disestablish(int, struct intrhand *); 516 517 void intr_lock_kernel(void); 518 void intr_unlock_kernel(void); 519 520 /* disksubr.c */ 521 struct dkbad; 522 int isbad(struct dkbad *, int, int, int); 523 524 /* machdep.c */ 525 int ldcontrolb(void *); 526 void * reserve_dumppages(void *); 527 void wcopy(const void *, void *, u_int); 528 void wzero(void *, u_int); 529 530 /* clock.c */ 531 struct timeval; 532 void lo_microtime(struct timeval *); 533 void schedintr(void *); 534 535 /* locore.s */ 536 struct fpstate; 537 void ipi_savefpstate(struct fpstate *); 538 void savefpstate(struct fpstate *); 539 void loadfpstate(struct fpstate *); 540 int probeget(void *, int); 541 void write_all_windows(void); 542 void write_user_windows(void); 543 void lwp_trampoline(void); 544 struct pcb; 545 void snapshot(struct pcb *); 546 struct frame *getfp(void); 547 int xldcontrolb(void *, struct pcb *); 548 void copywords(const void *, void *, size_t); 549 void qcopy(const void *, void *, size_t); 550 void qzero(void *, size_t); 551 552 /* trap.c */ 553 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 554 int rwindow_save(struct lwp *); 555 556 /* cons.c */ 557 int cnrom(void); 558 559 /* zs.c */ 560 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 561 #ifdef KGDB 562 void zs_kgdb_init(void); 563 #endif 564 565 /* fb.c */ 566 void fb_unblank(void); 567 568 /* kgdb_stub.c */ 569 #ifdef KGDB 570 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 571 void kgdb_connect(int); 572 void kgdb_panic(void); 573 #endif 574 575 /* emul.c */ 576 struct trapframe; 577 int fixalign(struct lwp *, struct trapframe *, void **); 578 int emulinstr(int, struct trapframe *); 579 580 /* cpu.c */ 581 void mp_pause_cpus(void); 582 void mp_resume_cpus(void); 583 void mp_halt_cpus(void); 584 #ifdef DDB 585 void mp_pause_cpus_ddb(void); 586 void mp_resume_cpus_ddb(void); 587 #endif 588 589 /* intr.c */ 590 u_int setitr(u_int); 591 u_int getitr(void); 592 593 594 /* 595 * 596 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 597 * of the trap vector table. The next eight bits are supplied by the 598 * hardware when the trap occurs, and the bottom four bits are always 599 * zero (so that we can shove up to 16 bytes of executable code---exactly 600 * four instructions---into each trap vector). 601 * 602 * The hardware allocates half the trap vectors to hardware and half to 603 * software. 604 * 605 * Traps have priorities assigned (lower number => higher priority). 606 */ 607 608 struct trapvec { 609 int tv_instr[4]; /* the four instructions */ 610 }; 611 612 extern struct trapvec *trapbase; /* the 256 vectors */ 613 614 #endif /* _KERNEL */ 615 #endif /* _CPU_H_ */ 616