1 /* $NetBSD: cpu.h,v 1.84 2008/02/27 18:26:16 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #ifdef _KERNEL 56 /* 57 * Exported definitions unique to SPARC cpu support. 58 */ 59 60 #if defined(_KERNEL_OPT) 61 #include "opt_multiprocessor.h" 62 #include "opt_lockdebug.h" 63 #include "opt_sparc_arch.h" 64 #endif 65 66 #include <machine/intr.h> 67 #include <machine/psl.h> 68 #include <sparc/sparc/cpuvar.h> 69 #include <sparc/sparc/intreg.h> 70 71 /* 72 * definitions of cpu-dependent requirements 73 * referenced in generic code 74 */ 75 #define curcpu() (cpuinfo.ci_self) 76 #define curlwp (cpuinfo.ci_curlwp) 77 #define CPU_IS_PRIMARY(ci) ((ci)->master) 78 79 #define cpu_swapin(p) /* nothing */ 80 #define cpu_swapout(p) /* nothing */ 81 #define cpu_number() (cpuinfo.ci_cpuid) 82 void cpu_proc_fork(struct proc *, struct proc *); 83 84 #if defined(MULTIPROCESSOR) 85 void cpu_boot_secondary_processors(void); 86 #endif 87 88 /* 89 * Arguments to hardclock, softclock and statclock encapsulate the 90 * previous machine state in an opaque clockframe. The ipl is here 91 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 92 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 93 */ 94 struct clockframe { 95 u_int psr; /* psr before interrupt, excluding PSR_ET */ 96 u_int pc; /* pc at interrupt */ 97 u_int npc; /* npc at interrupt */ 98 u_int ipl; /* actual interrupt priority level */ 99 u_int fp; /* %fp at interrupt */ 100 }; 101 typedef struct clockframe clockframe; 102 103 extern int eintstack[]; 104 105 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 106 #define CLKF_LOPRI(framep,n) (((framep)->psr & PSR_PIL) < (n) << 8) 107 #define CLKF_PC(framep) ((framep)->pc) 108 #if defined(MULTIPROCESSOR) 109 #define CLKF_INTR(framep) \ 110 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 111 (framep)->fp < (u_int)cpuinfo.eintstack) 112 #else 113 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 114 #endif 115 116 void sparc_softintr_init(void); 117 118 /* 119 * Preempt the current process on the target CPU if in interrupt from 120 * user mode, or after the current trap/syscall if in system mode. 121 */ 122 #define cpu_need_resched(ci, flags) do { \ 123 (ci)->ci_want_resched = 1; \ 124 (ci)->ci_want_ast = 1; \ 125 \ 126 /* Just interrupt the target CPU, so it can notice its AST */ \ 127 if (((flags) & RESCHED_IMMED) || (ci)->ci_cpuid != cpu_number()) \ 128 XCALL0(sparc_noop, 1U << (ci)->ci_cpuid); \ 129 } while (/*CONSTCOND*/0) 130 131 /* 132 * Give a profiling tick to the current process when the user profiling 133 * buffer pages are invalid. On the sparc, request an ast to send us 134 * through trap(), marking the proc as needing a profiling tick. 135 */ 136 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.ci_want_ast = 1) 137 138 /* 139 * Notify the current process (p) that it has a signal pending, 140 * process as soon as possible. 141 */ 142 #define cpu_signotify(l) do { \ 143 struct cpu_info *_ci = (l)->l_cpu; \ 144 _ci->ci_want_ast = 1; \ 145 \ 146 /* Just interrupt the target CPU, so it can notice its AST */ \ 147 if (_ci->ci_cpuid != cpu_number()) \ 148 XCALL0(sparc_noop, 1U << _ci->ci_cpuid); \ 149 } while (/*CONSTCOND*/0) 150 151 /* CPU architecture version */ 152 extern int cpu_arch; 153 154 /* Number of CPUs in the system */ 155 extern int sparc_ncpus; 156 157 /* 158 * Interrupt handler chains. Interrupt handlers should return 0 for 159 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 160 * handler into the list. The handler is called with its (single) 161 * argument, or with a pointer to a clockframe if ih_arg is NULL. 162 */ 163 extern struct intrhand { 164 int (*ih_fun)(void *); 165 void *ih_arg; 166 struct intrhand *ih_next; 167 int ih_classipl; 168 } *intrhand[15]; 169 170 void intr_establish(int, int, struct intrhand *, void (*)(void)); 171 void intr_disestablish(int, struct intrhand *); 172 173 void intr_lock_kernel(void); 174 void intr_unlock_kernel(void); 175 176 /* disksubr.c */ 177 struct dkbad; 178 int isbad(struct dkbad *, int, int, int); 179 180 /* machdep.c */ 181 int ldcontrolb(void *); 182 void dumpconf(void); 183 void * reserve_dumppages(void *); 184 void wcopy(const void *, void *, u_int); 185 void wzero(void *, u_int); 186 187 /* clock.c */ 188 struct timeval; 189 void lo_microtime(struct timeval *); 190 void schedintr(void *); 191 192 /* locore.s */ 193 struct fpstate; 194 void savefpstate(struct fpstate *); 195 void loadfpstate(struct fpstate *); 196 int probeget(void *, int); 197 void write_all_windows(void); 198 void write_user_windows(void); 199 void lwp_trampoline(void); 200 struct pcb; 201 void snapshot(struct pcb *); 202 struct frame *getfp(void); 203 int xldcontrolb(void *, struct pcb *); 204 void copywords(const void *, void *, size_t); 205 void qcopy(const void *, void *, size_t); 206 void qzero(void *, size_t); 207 208 /* trap.c */ 209 void kill_user_windows(struct lwp *); 210 int rwindow_save(struct lwp *); 211 212 /* cons.c */ 213 int cnrom(void); 214 215 /* zs.c */ 216 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 217 #ifdef KGDB 218 void zs_kgdb_init(void); 219 #endif 220 221 /* fb.c */ 222 void fb_unblank(void); 223 224 /* kgdb_stub.c */ 225 #ifdef KGDB 226 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 227 void kgdb_connect(int); 228 void kgdb_panic(void); 229 #endif 230 231 /* emul.c */ 232 struct trapframe; 233 int fixalign(struct lwp *, struct trapframe *); 234 int emulinstr(int, struct trapframe *); 235 236 /* cpu.c */ 237 void mp_pause_cpus(void); 238 void mp_resume_cpus(void); 239 void mp_halt_cpus(void); 240 #ifdef DDB 241 void mp_pause_cpus_ddb(void); 242 void mp_resume_cpus_ddb(void); 243 #endif 244 245 /* intr.c */ 246 u_int setitr(u_int); 247 u_int getitr(void); 248 249 250 /* 251 * 252 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 253 * of the trap vector table. The next eight bits are supplied by the 254 * hardware when the trap occurs, and the bottom four bits are always 255 * zero (so that we can shove up to 16 bytes of executable code---exactly 256 * four instructions---into each trap vector). 257 * 258 * The hardware allocates half the trap vectors to hardware and half to 259 * software. 260 * 261 * Traps have priorities assigned (lower number => higher priority). 262 */ 263 264 struct trapvec { 265 int tv_instr[4]; /* the four instructions */ 266 }; 267 268 extern struct trapvec *trapbase; /* the 256 vectors */ 269 270 #endif /* _KERNEL */ 271 #endif /* _CPU_H_ */ 272