1 /* $NetBSD: bus_defs.h,v 1.1 2011/07/01 17:10:01 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _SPARC_BUS_DEFS_H_ 65 #define _SPARC_BUS_DEFS_H_ 66 67 /* 68 * Bus address and size types 69 */ 70 typedef u_long bus_space_handle_t; 71 typedef uint64_t bus_addr_t; 72 typedef u_long bus_size_t; 73 74 #define SPARC_BUS_SPACE 0 75 76 /* bus_addr_t is extended to 64-bits and has the iospace encoded in it */ 77 #define BUS_ADDR_IOSPACE(x) ((x)>>32) 78 #define BUS_ADDR_PADDR(x) ((x)&0xffffffff) 79 #define BUS_ADDR(io, pa) \ 80 ((((uint64_t)(uint32_t)(io))<<32) | (uint32_t)(pa)) 81 82 #define __BUS_SPACE_HAS_STREAM_METHODS 1 83 84 /* 85 * Access methods for bus resources and address space. 86 */ 87 typedef struct sparc_bus_space_tag *bus_space_tag_t; 88 89 struct sparc_bus_space_tag { 90 void *cookie; 91 bus_space_tag_t parent; 92 93 /* 94 * Windows onto the parent bus that this tag maps. If ranges 95 * is non-NULL, the address will be translated, and recursively 96 * mapped via the parent tag. 97 */ 98 struct openprom_range *ranges; 99 int nranges; 100 101 int (*sparc_bus_map)( 102 bus_space_tag_t, 103 bus_addr_t, 104 bus_size_t, 105 int, /*flags*/ 106 vaddr_t, /*preferred vaddr*/ 107 bus_space_handle_t *); 108 int (*sparc_bus_unmap)( 109 bus_space_tag_t, 110 bus_space_handle_t, 111 bus_size_t); 112 int (*sparc_bus_subregion)( 113 bus_space_tag_t, 114 bus_space_handle_t, 115 bus_size_t, /*offset*/ 116 bus_size_t, /*size*/ 117 bus_space_handle_t *); 118 119 void (*sparc_bus_barrier)( 120 bus_space_tag_t, 121 bus_space_handle_t, 122 bus_size_t, /*offset*/ 123 bus_size_t, /*size*/ 124 int); /*flags*/ 125 126 paddr_t (*sparc_bus_mmap)( 127 bus_space_tag_t, 128 bus_addr_t, 129 off_t, 130 int, /*prot*/ 131 int); /*flags*/ 132 133 void *(*sparc_intr_establish)( 134 bus_space_tag_t, 135 int, /*bus-specific intr*/ 136 int, /*device class level, 137 see machine/intr.h*/ 138 int (*)(void *), /*handler*/ 139 void *, /*handler arg*/ 140 void (*)(void)); /*optional fast vector*/ 141 142 uint8_t (*sparc_read_1)( 143 bus_space_tag_t space, 144 bus_space_handle_t handle, 145 bus_size_t offset); 146 147 uint16_t (*sparc_read_2)( 148 bus_space_tag_t space, 149 bus_space_handle_t handle, 150 bus_size_t offset); 151 152 uint32_t (*sparc_read_4)( 153 bus_space_tag_t space, 154 bus_space_handle_t handle, 155 bus_size_t offset); 156 157 uint64_t (*sparc_read_8)( 158 bus_space_tag_t space, 159 bus_space_handle_t handle, 160 bus_size_t offset); 161 162 void (*sparc_write_1)( 163 bus_space_tag_t space, 164 bus_space_handle_t handle, 165 bus_size_t offset, 166 uint8_t value); 167 168 void (*sparc_write_2)( 169 bus_space_tag_t space, 170 bus_space_handle_t handle, 171 bus_size_t offset, 172 uint16_t value); 173 174 void (*sparc_write_4)( 175 bus_space_tag_t space, 176 bus_space_handle_t handle, 177 bus_size_t offset, 178 uint32_t value); 179 180 void (*sparc_write_8)( 181 bus_space_tag_t space, 182 bus_space_handle_t handle, 183 bus_size_t offset, 184 uint64_t value); 185 }; 186 187 /* flags for bus space map functions */ 188 #define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */ 189 #define BUS_SPACE_MAP_BUS2 0x0200 190 #define BUS_SPACE_MAP_BUS3 0x0400 191 #define BUS_SPACE_MAP_LARGE 0x0800 /* map outside IODEV range */ 192 193 194 /* flags for bus_space_barrier() */ 195 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 196 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 197 198 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 199 200 /* 201 * Flags used in various bus DMA methods. 202 */ 203 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 204 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 205 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 206 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 207 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 208 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 209 #define BUS_DMA_BUS2 0x020 210 #define BUS_DMA_BUS3 0x040 211 #define BUS_DMA_BUS4 0x080 212 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 213 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 214 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 215 216 /* For devices that have a 24-bit address space */ 217 #define BUS_DMA_24BIT BUS_DMA_BUS1 218 219 /* Internal flag: current DVMA address is equal to the KVA buffer address */ 220 #define _BUS_DMA_DIRECTMAP BUS_DMA_BUS2 221 222 /* Forwards needed by prototypes below. */ 223 struct mbuf; 224 struct uio; 225 226 /* 227 * Operations performed by bus_dmamap_sync(). 228 */ 229 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 230 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 231 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 232 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 233 234 typedef struct sparc_bus_dma_tag *bus_dma_tag_t; 235 typedef struct sparc_bus_dmamap *bus_dmamap_t; 236 237 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 238 239 /* 240 * bus_dma_segment_t 241 * 242 * Describes a single contiguous DMA transaction. Values 243 * are suitable for programming into DMA registers. 244 */ 245 struct sparc_bus_dma_segment { 246 bus_addr_t ds_addr; /* DVMA address */ 247 bus_size_t ds_len; /* length of transfer */ 248 bus_size_t _ds_sgsize; /* size of allocated DVMA segment */ 249 void *_ds_mlist; /* page list when dmamem_alloc'ed */ 250 vaddr_t _ds_va; /* VA when dmamem_map'ed */ 251 }; 252 typedef struct sparc_bus_dma_segment bus_dma_segment_t; 253 254 255 /* 256 * bus_dma_tag_t 257 * 258 * A machine-dependent opaque type describing the implementation of 259 * DMA for a given bus. 260 */ 261 struct sparc_bus_dma_tag { 262 void *_cookie; /* cookie used in the guts */ 263 264 /* 265 * DMA mapping methods. 266 */ 267 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 268 bus_size_t, bus_size_t, int, bus_dmamap_t *); 269 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 270 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 271 bus_size_t, struct proc *, int); 272 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 273 struct mbuf *, int); 274 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 275 struct uio *, int); 276 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 277 bus_dma_segment_t *, int, bus_size_t, int); 278 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 279 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 280 bus_addr_t, bus_size_t, int); 281 282 /* 283 * DMA memory utility functions. 284 */ 285 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 286 bus_size_t, bus_dma_segment_t *, int, int *, int); 287 void (*_dmamem_free)(bus_dma_tag_t, 288 bus_dma_segment_t *, int); 289 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 290 int, size_t, void **, int); 291 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 292 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 293 int, off_t, int, int); 294 }; 295 296 /* 297 * bus_dmamap_t 298 * 299 * Describes a DMA mapping. 300 */ 301 struct sparc_bus_dmamap { 302 /* 303 * PRIVATE MEMBERS: not for use by machine-independent code. 304 */ 305 bus_size_t _dm_size; /* largest DMA transfer mappable */ 306 int _dm_segcnt; /* number of segs this map can map */ 307 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 308 bus_size_t _dm_boundary; /* don't cross this */ 309 int _dm_flags; /* misc. flags */ 310 311 void *_dm_cookie; /* cookie for bus-specific functions */ 312 313 u_long _dm_align; /* DVMA alignment; must be a 314 multiple of the page size */ 315 u_long _dm_ex_start; /* constraints on DVMA map */ 316 u_long _dm_ex_end; /* allocations; used by the VME bus 317 driver and by the IOMMU driver 318 when mapping 24-bit devices */ 319 320 /* 321 * PUBLIC MEMBERS: these are used by machine-independent code. 322 */ 323 bus_size_t dm_maxsegsz; /* largest possible segment */ 324 bus_size_t dm_mapsize; /* size of the mapping */ 325 int dm_nsegs; /* # valid segments in mapping */ 326 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 327 }; 328 329 #endif /* _SPARC_BUS_DEFS_H_ */ 330