1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_mul.c 8.1 (Berkeley) 6/11/93 43 * 44 * from: Header: fpu_mul.c,v 1.3 92/11/26 01:39:50 torek Exp 45 * $Id: fpu_mul.c,v 1.1 1993/10/02 10:22:59 deraadt Exp $ 46 */ 47 48 /* 49 * Perform an FPU multiply (return x * y). 50 */ 51 52 #include <sys/types.h> 53 54 #include <machine/reg.h> 55 56 #include <sparc/fpu/fpu_arith.h> 57 #include <sparc/fpu/fpu_emu.h> 58 59 /* 60 * The multiplication algorithm for normal numbers is as follows: 61 * 62 * The fraction of the product is built in the usual stepwise fashion. 63 * Each step consists of shifting the accumulator right one bit 64 * (maintaining any guard bits) and, if the next bit in y is set, 65 * adding the multiplicand (x) to the accumulator. Then, in any case, 66 * we advance one bit leftward in y. Algorithmically: 67 * 68 * A = 0; 69 * for (bit = 0; bit < FP_NMANT; bit++) { 70 * sticky |= A & 1, A >>= 1; 71 * if (Y & (1 << bit)) 72 * A += X; 73 * } 74 * 75 * (X and Y here represent the mantissas of x and y respectively.) 76 * The resultant accumulator (A) is the product's mantissa. It may 77 * be as large as 11.11111... in binary and hence may need to be 78 * shifted right, but at most one bit. 79 * 80 * Since we do not have efficient multiword arithmetic, we code the 81 * accumulator as four separate words, just like any other mantissa. 82 * We use local `register' variables in the hope that this is faster 83 * than memory. We keep x->fp_mant in locals for the same reason. 84 * 85 * In the algorithm above, the bits in y are inspected one at a time. 86 * We will pick them up 32 at a time and then deal with those 32, one 87 * at a time. Note, however, that we know several things about y: 88 * 89 * - the guard and round bits at the bottom are sure to be zero; 90 * 91 * - often many low bits are zero (y is often from a single or double 92 * precision source); 93 * 94 * - bit FP_NMANT-1 is set, and FP_1*2 fits in a word. 95 * 96 * We can also test for 32-zero-bits swiftly. In this case, the center 97 * part of the loop---setting sticky, shifting A, and not adding---will 98 * run 32 times without adding X to A. We can do a 32-bit shift faster 99 * by simply moving words. Since zeros are common, we optimize this case. 100 * Furthermore, since A is initially zero, we can omit the shift as well 101 * until we reach a nonzero word. 102 */ 103 struct fpn * 104 fpu_mul(fe) 105 register struct fpemu *fe; 106 { 107 register struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 108 register u_int a3, a2, a1, a0, x3, x2, x1, x0, bit, m; 109 register int sticky; 110 FPU_DECL_CARRY 111 112 /* 113 * Put the `heavier' operand on the right (see fpu_emu.h). 114 * Then we will have one of the following cases, taken in the 115 * following order: 116 * 117 * - y = NaN. Implied: if only one is a signalling NaN, y is. 118 * The result is y. 119 * - y = Inf. Implied: x != NaN (is 0, number, or Inf: the NaN 120 * case was taken care of earlier). 121 * If x = 0, the result is NaN. Otherwise the result 122 * is y, with its sign reversed if x is negative. 123 * - x = 0. Implied: y is 0 or number. 124 * The result is 0 (with XORed sign as usual). 125 * - other. Implied: both x and y are numbers. 126 * The result is x * y (XOR sign, multiply bits, add exponents). 127 */ 128 ORDER(x, y); 129 if (ISNAN(y)) { 130 y->fp_sign ^= x->fp_sign; 131 return (y); 132 } 133 if (ISINF(y)) { 134 if (ISZERO(x)) 135 return (fpu_newnan(fe)); 136 y->fp_sign ^= x->fp_sign; 137 return (y); 138 } 139 if (ISZERO(x)) { 140 x->fp_sign ^= y->fp_sign; 141 return (x); 142 } 143 144 /* 145 * Setup. In the code below, the mask `m' will hold the current 146 * mantissa byte from y. The variable `bit' denotes the bit 147 * within m. We also define some macros to deal with everything. 148 */ 149 x3 = x->fp_mant[3]; 150 x2 = x->fp_mant[2]; 151 x1 = x->fp_mant[1]; 152 x0 = x->fp_mant[0]; 153 sticky = a3 = a2 = a1 = a0 = 0; 154 155 #define ADD /* A += X */ \ 156 FPU_ADDS(a3, a3, x3); \ 157 FPU_ADDCS(a2, a2, x2); \ 158 FPU_ADDCS(a1, a1, x1); \ 159 FPU_ADDC(a0, a0, x0) 160 161 #define SHR1 /* A >>= 1, with sticky */ \ 162 sticky |= a3 & 1, a3 = (a3 >> 1) | (a2 << 31), \ 163 a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 164 165 #define SHR32 /* A >>= 32, with sticky */ \ 166 sticky |= a3, a3 = a2, a2 = a1, a1 = a0, a0 = 0 167 168 #define STEP /* each 1-bit step of the multiplication */ \ 169 SHR1; if (bit & m) { ADD; }; bit <<= 1 170 171 /* 172 * We are ready to begin. The multiply loop runs once for each 173 * of the four 32-bit words. Some words, however, are special. 174 * As noted above, the low order bits of Y are often zero. Even 175 * if not, the first loop can certainly skip the guard bits. 176 * The last word of y has its highest 1-bit in position FP_NMANT-1, 177 * so we stop the loop when we move past that bit. 178 */ 179 if ((m = y->fp_mant[3]) == 0) { 180 /* SHR32; */ /* unneeded since A==0 */ 181 } else { 182 bit = 1 << FP_NG; 183 do { 184 STEP; 185 } while (bit != 0); 186 } 187 if ((m = y->fp_mant[2]) == 0) { 188 SHR32; 189 } else { 190 bit = 1; 191 do { 192 STEP; 193 } while (bit != 0); 194 } 195 if ((m = y->fp_mant[1]) == 0) { 196 SHR32; 197 } else { 198 bit = 1; 199 do { 200 STEP; 201 } while (bit != 0); 202 } 203 m = y->fp_mant[0]; /* definitely != 0 */ 204 bit = 1; 205 do { 206 STEP; 207 } while (bit <= m); 208 209 /* 210 * Done with mantissa calculation. Get exponent and handle 211 * 11.111...1 case, then put result in place. We reuse x since 212 * it already has the right class (FP_NUM). 213 */ 214 m = x->fp_exp + y->fp_exp; 215 if (a0 >= FP_2) { 216 SHR1; 217 m++; 218 } 219 x->fp_sign ^= y->fp_sign; 220 x->fp_exp = m; 221 x->fp_sticky = sticky; 222 x->fp_mant[3] = a3; 223 x->fp_mant[2] = a2; 224 x->fp_mant[1] = a1; 225 x->fp_mant[0] = a0; 226 return (x); 227 } 228