1 /* $NetBSD: fpu_implode.c,v 1.11 2003/07/15 00:04:59 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.11 2003/07/15 00:04:59 lukem Exp $"); 54 55 #if defined(_KERNEL_OPT) 56 #include "opt_sparc_arch.h" 57 #endif 58 59 #include <sys/types.h> 60 #include <sys/systm.h> 61 62 #include <machine/ieee.h> 63 #include <machine/instr.h> 64 #include <machine/reg.h> 65 66 #include <sparc/fpu/fpu_arith.h> 67 #include <sparc/fpu/fpu_emu.h> 68 #include <sparc/fpu/fpu_extern.h> 69 70 static int round __P((register struct fpemu *, register struct fpn *)); 71 static int toinf __P((struct fpemu *, int)); 72 73 /* 74 * Round a number (algorithm from Motorola MC68882 manual, modified for 75 * our internal format). Set inexact exception if rounding is required. 76 * Return true iff we rounded up. 77 * 78 * After rounding, we discard the guard and round bits by shifting right 79 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 80 * This saves effort later. 81 * 82 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 83 * responsibility to fix this if necessary. 84 */ 85 static int 86 round(register struct fpemu *fe, register struct fpn *fp) 87 { 88 register u_int m0, m1, m2, m3; 89 register int gr, s; 90 91 m0 = fp->fp_mant[0]; 92 m1 = fp->fp_mant[1]; 93 m2 = fp->fp_mant[2]; 94 m3 = fp->fp_mant[3]; 95 gr = m3 & 3; 96 s = fp->fp_sticky; 97 98 /* mant >>= FP_NG */ 99 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 100 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 101 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 102 m0 >>= FP_NG; 103 104 if ((gr | s) == 0) /* result is exact: no rounding needed */ 105 goto rounddown; 106 107 fe->fe_cx |= FSR_NX; /* inexact */ 108 109 /* Go to rounddown to round down; break to round up. */ 110 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 111 112 case FSR_RD_RN: 113 default: 114 /* 115 * Round only if guard is set (gr & 2). If guard is set, 116 * but round & sticky both clear, then we want to round 117 * but have a tie, so round to even, i.e., add 1 iff odd. 118 */ 119 if ((gr & 2) == 0) 120 goto rounddown; 121 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 122 break; 123 goto rounddown; 124 125 case FSR_RD_RZ: 126 /* Round towards zero, i.e., down. */ 127 goto rounddown; 128 129 case FSR_RD_RM: 130 /* Round towards -Inf: up if negative, down if positive. */ 131 if (fp->fp_sign) 132 break; 133 goto rounddown; 134 135 case FSR_RD_RP: 136 /* Round towards +Inf: up if positive, down otherwise. */ 137 if (!fp->fp_sign) 138 break; 139 goto rounddown; 140 } 141 142 /* Bump low bit of mantissa, with carry. */ 143 FPU_ADDS(m3, m3, 1); 144 FPU_ADDCS(m2, m2, 0); 145 FPU_ADDCS(m1, m1, 0); 146 FPU_ADDC(m0, m0, 0); 147 fp->fp_mant[0] = m0; 148 fp->fp_mant[1] = m1; 149 fp->fp_mant[2] = m2; 150 fp->fp_mant[3] = m3; 151 return (1); 152 153 rounddown: 154 fp->fp_mant[0] = m0; 155 fp->fp_mant[1] = m1; 156 fp->fp_mant[2] = m2; 157 fp->fp_mant[3] = m3; 158 return (0); 159 } 160 161 /* 162 * For overflow: return true if overflow is to go to +/-Inf, according 163 * to the sign of the overflowing result. If false, overflow is to go 164 * to the largest magnitude value instead. 165 */ 166 static int 167 toinf(struct fpemu *fe, int sign) 168 { 169 int inf; 170 171 /* look at rounding direction */ 172 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 173 174 default: 175 case FSR_RD_RN: /* the nearest value is always Inf */ 176 inf = 1; 177 break; 178 179 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 180 inf = 0; 181 break; 182 183 case FSR_RD_RP: /* toward +Inf iff positive */ 184 inf = sign == 0; 185 break; 186 187 case FSR_RD_RM: /* toward -Inf iff negative */ 188 inf = sign; 189 break; 190 } 191 return (inf); 192 } 193 194 /* 195 * fpn -> int (int value returned as return value). 196 * 197 * N.B.: this conversion always rounds towards zero (this is a peculiarity 198 * of the SPARC instruction set). 199 */ 200 u_int 201 fpu_ftoi(fe, fp) 202 struct fpemu *fe; 203 register struct fpn *fp; 204 { 205 register u_int i; 206 register int sign, exp; 207 208 sign = fp->fp_sign; 209 switch (fp->fp_class) { 210 211 case FPC_ZERO: 212 return (0); 213 214 case FPC_NUM: 215 /* 216 * If exp >= 2^32, overflow. Otherwise shift value right 217 * into last mantissa word (this will not exceed 0xffffffff), 218 * shifting any guard and round bits out into the sticky 219 * bit. Then ``round'' towards zero, i.e., just set an 220 * inexact exception if sticky is set (see round()). 221 * If the result is > 0x80000000, or is positive and equals 222 * 0x80000000, overflow; otherwise the last fraction word 223 * is the result. 224 */ 225 if ((exp = fp->fp_exp) >= 32) 226 break; 227 /* NB: the following includes exp < 0 cases */ 228 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 229 fe->fe_cx |= FSR_NX; 230 i = fp->fp_mant[3]; 231 if (i >= ((u_int)0x80000000 + sign)) 232 break; 233 return (sign ? -i : i); 234 235 default: /* Inf, qNaN, sNaN */ 236 break; 237 } 238 /* overflow: replace any inexact exception with invalid */ 239 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 240 return (0x7fffffff + sign); 241 } 242 243 #ifdef SUN4U 244 /* 245 * fpn -> extended int (high bits of int value returned as return value). 246 * 247 * N.B.: this conversion always rounds towards zero (this is a peculiarity 248 * of the SPARC instruction set). 249 */ 250 u_int 251 fpu_ftox(fe, fp, res) 252 struct fpemu *fe; 253 register struct fpn *fp; 254 u_int *res; 255 { 256 register u_int64_t i; 257 register int sign, exp; 258 259 sign = fp->fp_sign; 260 switch (fp->fp_class) { 261 262 case FPC_ZERO: 263 res[1] = 0; 264 return (0); 265 266 case FPC_NUM: 267 /* 268 * If exp >= 2^64, overflow. Otherwise shift value right 269 * into last mantissa word (this will not exceed 0xffffffffffffffff), 270 * shifting any guard and round bits out into the sticky 271 * bit. Then ``round'' towards zero, i.e., just set an 272 * inexact exception if sticky is set (see round()). 273 * If the result is > 0x8000000000000000, or is positive and equals 274 * 0x8000000000000000, overflow; otherwise the last fraction word 275 * is the result. 276 */ 277 if ((exp = fp->fp_exp) >= 64) 278 break; 279 /* NB: the following includes exp < 0 cases */ 280 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 281 fe->fe_cx |= FSR_NX; 282 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 283 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 284 break; 285 if (sign) i = -i; 286 res[1] = (int)i; 287 return (i>>32); 288 289 default: /* Inf, qNaN, sNaN */ 290 break; 291 } 292 /* overflow: replace any inexact exception with invalid */ 293 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 294 return (0x7fffffffffffffffLL + sign); 295 } 296 #endif /* SUN4U */ 297 298 /* 299 * fpn -> single (32 bit single returned as return value). 300 * We assume <= 29 bits in a single-precision fraction (1.f part). 301 */ 302 u_int 303 fpu_ftos(fe, fp) 304 struct fpemu *fe; 305 register struct fpn *fp; 306 { 307 register u_int sign = fp->fp_sign << 31; 308 register int exp; 309 310 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 311 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 312 313 /* Take care of non-numbers first. */ 314 if (ISNAN(fp)) { 315 /* 316 * Preserve upper bits of NaN, per SPARC V8 appendix N. 317 * Note that fp->fp_mant[0] has the quiet bit set, 318 * even if it is classified as a signalling NaN. 319 */ 320 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 321 exp = SNG_EXP_INFNAN; 322 goto done; 323 } 324 if (ISINF(fp)) 325 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 326 if (ISZERO(fp)) 327 return (sign); 328 329 /* 330 * Normals (including subnormals). Drop all the fraction bits 331 * (including the explicit ``implied'' 1 bit) down into the 332 * single-precision range. If the number is subnormal, move 333 * the ``implied'' 1 into the explicit range as well, and shift 334 * right to introduce leading zeroes. Rounding then acts 335 * differently for normals and subnormals: the largest subnormal 336 * may round to the smallest normal (1.0 x 2^minexp), or may 337 * remain subnormal. In the latter case, signal an underflow 338 * if the result was inexact or if underflow traps are enabled. 339 * 340 * Rounding a normal, on the other hand, always produces another 341 * normal (although either way the result might be too big for 342 * single precision, and cause an overflow). If rounding a 343 * normal produces 2.0 in the fraction, we need not adjust that 344 * fraction at all, since both 1.0 and 2.0 are zero under the 345 * fraction mask. 346 * 347 * Note that the guard and round bits vanish from the number after 348 * rounding. 349 */ 350 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 351 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 352 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 353 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 354 return (sign | SNG_EXP(1) | 0); 355 if ((fe->fe_cx & FSR_NX) || 356 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 357 fe->fe_cx |= FSR_UF; 358 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 359 } 360 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 361 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 362 #ifdef DIAGNOSTIC 363 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 364 panic("fpu_ftos"); 365 #endif 366 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 367 exp++; 368 if (exp >= SNG_EXP_INFNAN) { 369 /* overflow to inf or to max single */ 370 fe->fe_cx |= FSR_OF | FSR_NX; 371 if (toinf(fe, sign)) 372 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 373 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 374 } 375 done: 376 /* phew, made it */ 377 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 378 } 379 380 /* 381 * fpn -> double (32 bit high-order result returned; 32-bit low order result 382 * left in res[1]). Assumes <= 61 bits in double precision fraction. 383 * 384 * This code mimics fpu_ftos; see it for comments. 385 */ 386 u_int 387 fpu_ftod(fe, fp, res) 388 struct fpemu *fe; 389 register struct fpn *fp; 390 u_int *res; 391 { 392 register u_int sign = fp->fp_sign << 31; 393 register int exp; 394 395 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 396 #define DBL_MASK (DBL_EXP(1) - 1) 397 398 if (ISNAN(fp)) { 399 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 400 exp = DBL_EXP_INFNAN; 401 goto done; 402 } 403 if (ISINF(fp)) { 404 sign |= DBL_EXP(DBL_EXP_INFNAN); 405 goto zero; 406 } 407 if (ISZERO(fp)) { 408 zero: res[1] = 0; 409 return (sign); 410 } 411 412 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 413 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 414 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 415 res[1] = 0; 416 return (sign | DBL_EXP(1) | 0); 417 } 418 if ((fe->fe_cx & FSR_NX) || 419 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 420 fe->fe_cx |= FSR_UF; 421 exp = 0; 422 goto done; 423 } 424 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 425 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 426 exp++; 427 if (exp >= DBL_EXP_INFNAN) { 428 fe->fe_cx |= FSR_OF | FSR_NX; 429 if (toinf(fe, sign)) { 430 res[1] = 0; 431 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 432 } 433 res[1] = ~0; 434 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 435 } 436 done: 437 res[1] = fp->fp_mant[3]; 438 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 439 } 440 441 /* 442 * fpn -> extended (32 bit high-order result returned; low-order fraction 443 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 444 * our internal format *is* extended precision, plus 2 bits for guard/round, 445 * so we can avoid a small bit of work. 446 */ 447 u_int 448 fpu_ftoq(fe, fp, res) 449 struct fpemu *fe; 450 register struct fpn *fp; 451 u_int *res; 452 { 453 register u_int sign = fp->fp_sign << 31; 454 register int exp; 455 456 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 457 #define EXT_MASK (EXT_EXP(1) - 1) 458 459 if (ISNAN(fp)) { 460 (void) fpu_shr(fp, 2); /* since we are not rounding */ 461 exp = EXT_EXP_INFNAN; 462 goto done; 463 } 464 if (ISINF(fp)) { 465 sign |= EXT_EXP(EXT_EXP_INFNAN); 466 goto zero; 467 } 468 if (ISZERO(fp)) { 469 zero: res[1] = res[2] = res[3] = 0; 470 return (sign); 471 } 472 473 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 474 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 475 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 476 res[1] = res[2] = res[3] = 0; 477 return (sign | EXT_EXP(1) | 0); 478 } 479 if ((fe->fe_cx & FSR_NX) || 480 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 481 fe->fe_cx |= FSR_UF; 482 exp = 0; 483 goto done; 484 } 485 /* Since internal == extended, no need to shift here. */ 486 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 487 exp++; 488 if (exp >= EXT_EXP_INFNAN) { 489 fe->fe_cx |= FSR_OF | FSR_NX; 490 if (toinf(fe, sign)) { 491 res[1] = res[2] = res[3] = 0; 492 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 493 } 494 res[1] = res[2] = res[3] = ~0; 495 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 496 } 497 done: 498 res[1] = fp->fp_mant[1]; 499 res[2] = fp->fp_mant[2]; 500 res[3] = fp->fp_mant[3]; 501 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 502 } 503 504 /* 505 * Implode an fpn, writing the result into the given space. 506 */ 507 void 508 fpu_implode(fe, fp, type, space) 509 struct fpemu *fe; 510 register struct fpn *fp; 511 int type; 512 register u_int *space; 513 { 514 515 DPRINTF(FPE_REG, ("\n imploding: ")); 516 DUMPFPN(FPE_REG, fp); 517 DPRINTF(FPE_REG, ("\n")); 518 519 switch (type) { 520 521 #ifdef SUN4U 522 case FTYPE_LNG: 523 space[0] = fpu_ftox(fe, fp, space); 524 break; 525 #endif /* SUN4U */ 526 527 case FTYPE_INT: 528 space[0] = fpu_ftoi(fe, fp); 529 break; 530 531 case FTYPE_SNG: 532 space[0] = fpu_ftos(fe, fp); 533 break; 534 535 case FTYPE_DBL: 536 space[0] = fpu_ftod(fe, fp, space); 537 break; 538 539 case FTYPE_EXT: 540 /* funky rounding precision options ?? */ 541 space[0] = fpu_ftoq(fe, fp, space); 542 break; 543 544 default: 545 panic("fpu_implode"); 546 } 547 #ifdef SUN4U 548 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n", 549 space[0], space[1], space[2], space[3])); 550 #else 551 DPRINTF(FPE_REG, ("fpu_implode: %x %x\n", 552 space[0], space[1])); 553 #endif 554 } 555