1 /* $NetBSD: fpu_implode.c,v 1.7 2000/08/03 18:32:08 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/ieee.h> 56 #include <machine/instr.h> 57 #include <machine/reg.h> 58 59 #include <sparc/fpu/fpu_arith.h> 60 #include <sparc/fpu/fpu_emu.h> 61 #include <sparc/fpu/fpu_extern.h> 62 63 static int round __P((register struct fpemu *, register struct fpn *)); 64 static int toinf __P((struct fpemu *, int)); 65 66 /* 67 * Round a number (algorithm from Motorola MC68882 manual, modified for 68 * our internal format). Set inexact exception if rounding is required. 69 * Return true iff we rounded up. 70 * 71 * After rounding, we discard the guard and round bits by shifting right 72 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 73 * This saves effort later. 74 * 75 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 76 * responsibility to fix this if necessary. 77 */ 78 static int 79 round(register struct fpemu *fe, register struct fpn *fp) 80 { 81 register u_int m0, m1, m2, m3; 82 register int gr, s; 83 84 m0 = fp->fp_mant[0]; 85 m1 = fp->fp_mant[1]; 86 m2 = fp->fp_mant[2]; 87 m3 = fp->fp_mant[3]; 88 gr = m3 & 3; 89 s = fp->fp_sticky; 90 91 /* mant >>= FP_NG */ 92 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 93 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 94 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 95 m0 >>= FP_NG; 96 97 if ((gr | s) == 0) /* result is exact: no rounding needed */ 98 goto rounddown; 99 100 fe->fe_cx |= FSR_NX; /* inexact */ 101 102 /* Go to rounddown to round down; break to round up. */ 103 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 104 105 case FSR_RD_RN: 106 default: 107 /* 108 * Round only if guard is set (gr & 2). If guard is set, 109 * but round & sticky both clear, then we want to round 110 * but have a tie, so round to even, i.e., add 1 iff odd. 111 */ 112 if ((gr & 2) == 0) 113 goto rounddown; 114 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 115 break; 116 goto rounddown; 117 118 case FSR_RD_RZ: 119 /* Round towards zero, i.e., down. */ 120 goto rounddown; 121 122 case FSR_RD_RM: 123 /* Round towards -Inf: up if negative, down if positive. */ 124 if (fp->fp_sign) 125 break; 126 goto rounddown; 127 128 case FSR_RD_RP: 129 /* Round towards +Inf: up if positive, down otherwise. */ 130 if (!fp->fp_sign) 131 break; 132 goto rounddown; 133 } 134 135 /* Bump low bit of mantissa, with carry. */ 136 FPU_ADDS(m3, m3, 1); 137 FPU_ADDCS(m2, m2, 0); 138 FPU_ADDCS(m1, m1, 0); 139 FPU_ADDC(m0, m0, 0); 140 fp->fp_mant[0] = m0; 141 fp->fp_mant[1] = m1; 142 fp->fp_mant[2] = m2; 143 fp->fp_mant[3] = m3; 144 return (1); 145 146 rounddown: 147 fp->fp_mant[0] = m0; 148 fp->fp_mant[1] = m1; 149 fp->fp_mant[2] = m2; 150 fp->fp_mant[3] = m3; 151 return (0); 152 } 153 154 /* 155 * For overflow: return true if overflow is to go to +/-Inf, according 156 * to the sign of the overflowing result. If false, overflow is to go 157 * to the largest magnitude value instead. 158 */ 159 static int 160 toinf(struct fpemu *fe, int sign) 161 { 162 int inf; 163 164 /* look at rounding direction */ 165 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 166 167 default: 168 case FSR_RD_RN: /* the nearest value is always Inf */ 169 inf = 1; 170 break; 171 172 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 173 inf = 0; 174 break; 175 176 case FSR_RD_RP: /* toward +Inf iff positive */ 177 inf = sign == 0; 178 break; 179 180 case FSR_RD_RM: /* toward -Inf iff negative */ 181 inf = sign; 182 break; 183 } 184 return (inf); 185 } 186 187 /* 188 * fpn -> int (int value returned as return value). 189 * 190 * N.B.: this conversion always rounds towards zero (this is a peculiarity 191 * of the SPARC instruction set). 192 */ 193 u_int 194 fpu_ftoi(fe, fp) 195 struct fpemu *fe; 196 register struct fpn *fp; 197 { 198 register u_int i; 199 register int sign, exp; 200 201 sign = fp->fp_sign; 202 switch (fp->fp_class) { 203 204 case FPC_ZERO: 205 return (0); 206 207 case FPC_NUM: 208 /* 209 * If exp >= 2^32, overflow. Otherwise shift value right 210 * into last mantissa word (this will not exceed 0xffffffff), 211 * shifting any guard and round bits out into the sticky 212 * bit. Then ``round'' towards zero, i.e., just set an 213 * inexact exception if sticky is set (see round()). 214 * If the result is > 0x80000000, or is positive and equals 215 * 0x80000000, overflow; otherwise the last fraction word 216 * is the result. 217 */ 218 if ((exp = fp->fp_exp) >= 32) 219 break; 220 /* NB: the following includes exp < 0 cases */ 221 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 222 fe->fe_cx |= FSR_NX; 223 i = fp->fp_mant[3]; 224 if (i >= ((u_int)0x80000000 + sign)) 225 break; 226 return (sign ? -i : i); 227 228 default: /* Inf, qNaN, sNaN */ 229 break; 230 } 231 /* overflow: replace any inexact exception with invalid */ 232 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 233 return (0x7fffffff + sign); 234 } 235 236 #ifdef SUN4U 237 /* 238 * fpn -> extended int (high bits of int value returned as return value). 239 * 240 * N.B.: this conversion always rounds towards zero (this is a peculiarity 241 * of the SPARC instruction set). 242 */ 243 u_int 244 fpu_ftox(fe, fp, res) 245 struct fpemu *fe; 246 register struct fpn *fp; 247 u_int *res; 248 { 249 register u_int64_t i; 250 register int sign, exp; 251 252 sign = fp->fp_sign; 253 switch (fp->fp_class) { 254 255 case FPC_ZERO: 256 res[1] = 0; 257 return (0); 258 259 case FPC_NUM: 260 /* 261 * If exp >= 2^64, overflow. Otherwise shift value right 262 * into last mantissa word (this will not exceed 0xffffffffffffffff), 263 * shifting any guard and round bits out into the sticky 264 * bit. Then ``round'' towards zero, i.e., just set an 265 * inexact exception if sticky is set (see round()). 266 * If the result is > 0x8000000000000000, or is positive and equals 267 * 0x8000000000000000, overflow; otherwise the last fraction word 268 * is the result. 269 */ 270 if ((exp = fp->fp_exp) >= 64) 271 break; 272 /* NB: the following includes exp < 0 cases */ 273 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 274 fe->fe_cx |= FSR_NX; 275 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 276 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 277 break; 278 return (sign ? -i : i); 279 280 default: /* Inf, qNaN, sNaN */ 281 break; 282 } 283 /* overflow: replace any inexact exception with invalid */ 284 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 285 return (0x7fffffffffffffffLL + sign); 286 } 287 #endif /* SUN4U */ 288 289 /* 290 * fpn -> single (32 bit single returned as return value). 291 * We assume <= 29 bits in a single-precision fraction (1.f part). 292 */ 293 u_int 294 fpu_ftos(fe, fp) 295 struct fpemu *fe; 296 register struct fpn *fp; 297 { 298 register u_int sign = fp->fp_sign << 31; 299 register int exp; 300 301 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 302 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 303 304 /* Take care of non-numbers first. */ 305 if (ISNAN(fp)) { 306 /* 307 * Preserve upper bits of NaN, per SPARC V8 appendix N. 308 * Note that fp->fp_mant[0] has the quiet bit set, 309 * even if it is classified as a signalling NaN. 310 */ 311 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 312 exp = SNG_EXP_INFNAN; 313 goto done; 314 } 315 if (ISINF(fp)) 316 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 317 if (ISZERO(fp)) 318 return (sign); 319 320 /* 321 * Normals (including subnormals). Drop all the fraction bits 322 * (including the explicit ``implied'' 1 bit) down into the 323 * single-precision range. If the number is subnormal, move 324 * the ``implied'' 1 into the explicit range as well, and shift 325 * right to introduce leading zeroes. Rounding then acts 326 * differently for normals and subnormals: the largest subnormal 327 * may round to the smallest normal (1.0 x 2^minexp), or may 328 * remain subnormal. In the latter case, signal an underflow 329 * if the result was inexact or if underflow traps are enabled. 330 * 331 * Rounding a normal, on the other hand, always produces another 332 * normal (although either way the result might be too big for 333 * single precision, and cause an overflow). If rounding a 334 * normal produces 2.0 in the fraction, we need not adjust that 335 * fraction at all, since both 1.0 and 2.0 are zero under the 336 * fraction mask. 337 * 338 * Note that the guard and round bits vanish from the number after 339 * rounding. 340 */ 341 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 342 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 343 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 344 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 345 return (sign | SNG_EXP(1) | 0); 346 if ((fe->fe_cx & FSR_NX) || 347 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 348 fe->fe_cx |= FSR_UF; 349 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 350 } 351 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 352 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 353 #ifdef DIAGNOSTIC 354 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 355 panic("fpu_ftos"); 356 #endif 357 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 358 exp++; 359 if (exp >= SNG_EXP_INFNAN) { 360 /* overflow to inf or to max single */ 361 fe->fe_cx |= FSR_OF | FSR_NX; 362 if (toinf(fe, sign)) 363 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 364 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 365 } 366 done: 367 /* phew, made it */ 368 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 369 } 370 371 /* 372 * fpn -> double (32 bit high-order result returned; 32-bit low order result 373 * left in res[1]). Assumes <= 61 bits in double precision fraction. 374 * 375 * This code mimics fpu_ftos; see it for comments. 376 */ 377 u_int 378 fpu_ftod(fe, fp, res) 379 struct fpemu *fe; 380 register struct fpn *fp; 381 u_int *res; 382 { 383 register u_int sign = fp->fp_sign << 31; 384 register int exp; 385 386 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 387 #define DBL_MASK (DBL_EXP(1) - 1) 388 389 if (ISNAN(fp)) { 390 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 391 exp = DBL_EXP_INFNAN; 392 goto done; 393 } 394 if (ISINF(fp)) { 395 sign |= DBL_EXP(DBL_EXP_INFNAN); 396 goto zero; 397 } 398 if (ISZERO(fp)) { 399 zero: res[1] = 0; 400 return (sign); 401 } 402 403 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 404 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 405 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 406 res[1] = 0; 407 return (sign | DBL_EXP(1) | 0); 408 } 409 if ((fe->fe_cx & FSR_NX) || 410 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 411 fe->fe_cx |= FSR_UF; 412 exp = 0; 413 goto done; 414 } 415 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 416 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 417 exp++; 418 if (exp >= DBL_EXP_INFNAN) { 419 fe->fe_cx |= FSR_OF | FSR_NX; 420 if (toinf(fe, sign)) { 421 res[1] = 0; 422 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 423 } 424 res[1] = ~0; 425 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 426 } 427 done: 428 res[1] = fp->fp_mant[3]; 429 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 430 } 431 432 /* 433 * fpn -> extended (32 bit high-order result returned; low-order fraction 434 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 435 * our internal format *is* extended precision, plus 2 bits for guard/round, 436 * so we can avoid a small bit of work. 437 */ 438 u_int 439 fpu_ftoq(fe, fp, res) 440 struct fpemu *fe; 441 register struct fpn *fp; 442 u_int *res; 443 { 444 register u_int sign = fp->fp_sign << 31; 445 register int exp; 446 447 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 448 #define EXT_MASK (EXT_EXP(1) - 1) 449 450 if (ISNAN(fp)) { 451 (void) fpu_shr(fp, 2); /* since we are not rounding */ 452 exp = EXT_EXP_INFNAN; 453 goto done; 454 } 455 if (ISINF(fp)) { 456 sign |= EXT_EXP(EXT_EXP_INFNAN); 457 goto zero; 458 } 459 if (ISZERO(fp)) { 460 zero: res[1] = res[2] = res[3] = 0; 461 return (sign); 462 } 463 464 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 465 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 466 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 467 res[1] = res[2] = res[3] = 0; 468 return (sign | EXT_EXP(1) | 0); 469 } 470 if ((fe->fe_cx & FSR_NX) || 471 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 472 fe->fe_cx |= FSR_UF; 473 exp = 0; 474 goto done; 475 } 476 /* Since internal == extended, no need to shift here. */ 477 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 478 exp++; 479 if (exp >= EXT_EXP_INFNAN) { 480 fe->fe_cx |= FSR_OF | FSR_NX; 481 if (toinf(fe, sign)) { 482 res[1] = res[2] = res[3] = 0; 483 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 484 } 485 res[1] = res[2] = res[3] = ~0; 486 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 487 } 488 done: 489 res[1] = fp->fp_mant[1]; 490 res[2] = fp->fp_mant[2]; 491 res[3] = fp->fp_mant[3]; 492 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 493 } 494 495 /* 496 * Implode an fpn, writing the result into the given space. 497 */ 498 void 499 fpu_implode(fe, fp, type, space) 500 struct fpemu *fe; 501 register struct fpn *fp; 502 int type; 503 register u_int *space; 504 { 505 506 switch (type) { 507 508 #ifdef SUN4U 509 case FTYPE_LNG: 510 space[0] = fpu_ftox(fe, fp, space); 511 break; 512 #endif /* SUN4U */ 513 514 case FTYPE_INT: 515 space[0] = fpu_ftoi(fe, fp); 516 break; 517 518 case FTYPE_SNG: 519 space[0] = fpu_ftos(fe, fp); 520 break; 521 522 case FTYPE_DBL: 523 space[0] = fpu_ftod(fe, fp, space); 524 break; 525 526 case FTYPE_EXT: 527 /* funky rounding precision options ?? */ 528 space[0] = fpu_ftoq(fe, fp, space); 529 break; 530 531 default: 532 panic("fpu_implode"); 533 } 534 } 535