1 /* $NetBSD: fpu_implode.c,v 1.3 1996/03/14 19:41:59 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/ieee.h> 56 #include <machine/instr.h> 57 #include <machine/reg.h> 58 59 #include <sparc/fpu/fpu_arith.h> 60 #include <sparc/fpu/fpu_emu.h> 61 #include <sparc/fpu/fpu_extern.h> 62 63 static int round __P((register struct fpemu *, register struct fpn *)); 64 static int toinf __P((struct fpemu *, int)); 65 66 /* 67 * Round a number (algorithm from Motorola MC68882 manual, modified for 68 * our internal format). Set inexact exception if rounding is required. 69 * Return true iff we rounded up. 70 * 71 * After rounding, we discard the guard and round bits by shifting right 72 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 73 * This saves effort later. 74 * 75 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 76 * responsibility to fix this if necessary. 77 */ 78 static int 79 round(register struct fpemu *fe, register struct fpn *fp) 80 { 81 register u_int m0, m1, m2, m3; 82 register int gr, s; 83 84 m0 = fp->fp_mant[0]; 85 m1 = fp->fp_mant[1]; 86 m2 = fp->fp_mant[2]; 87 m3 = fp->fp_mant[3]; 88 gr = m3 & 3; 89 s = fp->fp_sticky; 90 91 /* mant >>= FP_NG */ 92 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 93 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 94 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 95 m0 >>= FP_NG; 96 97 if ((gr | s) == 0) /* result is exact: no rounding needed */ 98 goto rounddown; 99 100 fe->fe_cx |= FSR_NX; /* inexact */ 101 102 /* Go to rounddown to round down; break to round up. */ 103 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 104 105 case FSR_RD_RN: 106 default: 107 /* 108 * Round only if guard is set (gr & 2). If guard is set, 109 * but round & sticky both clear, then we want to round 110 * but have a tie, so round to even, i.e., add 1 iff odd. 111 */ 112 if ((gr & 2) == 0) 113 goto rounddown; 114 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 115 break; 116 goto rounddown; 117 118 case FSR_RD_RZ: 119 /* Round towards zero, i.e., down. */ 120 goto rounddown; 121 122 case FSR_RD_RM: 123 /* Round towards -Inf: up if negative, down if positive. */ 124 if (fp->fp_sign) 125 break; 126 goto rounddown; 127 128 case FSR_RD_RP: 129 /* Round towards +Inf: up if positive, down otherwise. */ 130 if (!fp->fp_sign) 131 break; 132 goto rounddown; 133 } 134 135 /* Bump low bit of mantissa, with carry. */ 136 #ifdef sparc /* ``cheating'' (left out FPU_DECL_CARRY; know this is faster) */ 137 FPU_ADDS(m3, m3, 1); 138 FPU_ADDCS(m2, m2, 0); 139 FPU_ADDCS(m1, m1, 0); 140 FPU_ADDC(m0, m0, 0); 141 #else 142 if (++m3 == 0 && ++m2 == 0 && ++m1 == 0) 143 m0++; 144 #endif 145 fp->fp_mant[0] = m0; 146 fp->fp_mant[1] = m1; 147 fp->fp_mant[2] = m2; 148 fp->fp_mant[3] = m3; 149 return (1); 150 151 rounddown: 152 fp->fp_mant[0] = m0; 153 fp->fp_mant[1] = m1; 154 fp->fp_mant[2] = m2; 155 fp->fp_mant[3] = m3; 156 return (0); 157 } 158 159 /* 160 * For overflow: return true if overflow is to go to +/-Inf, according 161 * to the sign of the overflowing result. If false, overflow is to go 162 * to the largest magnitude value instead. 163 */ 164 static int 165 toinf(struct fpemu *fe, int sign) 166 { 167 int inf; 168 169 /* look at rounding direction */ 170 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 171 172 default: 173 case FSR_RD_RN: /* the nearest value is always Inf */ 174 inf = 1; 175 break; 176 177 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 178 inf = 0; 179 break; 180 181 case FSR_RD_RP: /* toward +Inf iff positive */ 182 inf = sign == 0; 183 break; 184 185 case FSR_RD_RM: /* toward -Inf iff negative */ 186 inf = sign; 187 break; 188 } 189 return (inf); 190 } 191 192 /* 193 * fpn -> int (int value returned as return value). 194 * 195 * N.B.: this conversion always rounds towards zero (this is a peculiarity 196 * of the SPARC instruction set). 197 */ 198 u_int 199 fpu_ftoi(fe, fp) 200 struct fpemu *fe; 201 register struct fpn *fp; 202 { 203 register u_int i; 204 register int sign, exp; 205 206 sign = fp->fp_sign; 207 switch (fp->fp_class) { 208 209 case FPC_ZERO: 210 return (0); 211 212 case FPC_NUM: 213 /* 214 * If exp >= 2^32, overflow. Otherwise shift value right 215 * into last mantissa word (this will not exceed 0xffffffff), 216 * shifting any guard and round bits out into the sticky 217 * bit. Then ``round'' towards zero, i.e., just set an 218 * inexact exception if sticky is set (see round()). 219 * If the result is > 0x80000000, or is positive and equals 220 * 0x80000000, overflow; otherwise the last fraction word 221 * is the result. 222 */ 223 if ((exp = fp->fp_exp) >= 32) 224 break; 225 /* NB: the following includes exp < 0 cases */ 226 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 227 fe->fe_cx |= FSR_NX; 228 i = fp->fp_mant[3]; 229 if (i >= ((u_int)0x80000000 + sign)) 230 break; 231 return (sign ? -i : i); 232 233 default: /* Inf, qNaN, sNaN */ 234 break; 235 } 236 /* overflow: replace any inexact exception with invalid */ 237 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 238 return (0x7fffffff + sign); 239 } 240 241 /* 242 * fpn -> single (32 bit single returned as return value). 243 * We assume <= 29 bits in a single-precision fraction (1.f part). 244 */ 245 u_int 246 fpu_ftos(fe, fp) 247 struct fpemu *fe; 248 register struct fpn *fp; 249 { 250 register u_int sign = fp->fp_sign << 31; 251 register int exp; 252 253 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 254 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 255 256 /* Take care of non-numbers first. */ 257 if (ISNAN(fp)) { 258 /* 259 * Preserve upper bits of NaN, per SPARC V8 appendix N. 260 * Note that fp->fp_mant[0] has the quiet bit set, 261 * even if it is classified as a signalling NaN. 262 */ 263 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 264 exp = SNG_EXP_INFNAN; 265 goto done; 266 } 267 if (ISINF(fp)) 268 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 269 if (ISZERO(fp)) 270 return (sign); 271 272 /* 273 * Normals (including subnormals). Drop all the fraction bits 274 * (including the explicit ``implied'' 1 bit) down into the 275 * single-precision range. If the number is subnormal, move 276 * the ``implied'' 1 into the explicit range as well, and shift 277 * right to introduce leading zeroes. Rounding then acts 278 * differently for normals and subnormals: the largest subnormal 279 * may round to the smallest normal (1.0 x 2^minexp), or may 280 * remain subnormal. In the latter case, signal an underflow 281 * if the result was inexact or if underflow traps are enabled. 282 * 283 * Rounding a normal, on the other hand, always produces another 284 * normal (although either way the result might be too big for 285 * single precision, and cause an overflow). If rounding a 286 * normal produces 2.0 in the fraction, we need not adjust that 287 * fraction at all, since both 1.0 and 2.0 are zero under the 288 * fraction mask. 289 * 290 * Note that the guard and round bits vanish from the number after 291 * rounding. 292 */ 293 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 294 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 295 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 296 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 297 return (sign | SNG_EXP(1) | 0); 298 if ((fe->fe_cx & FSR_NX) || 299 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 300 fe->fe_cx |= FSR_UF; 301 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 302 } 303 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 304 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 305 #ifdef DIAGNOSTIC 306 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 307 panic("fpu_ftos"); 308 #endif 309 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 310 exp++; 311 if (exp >= SNG_EXP_INFNAN) { 312 /* overflow to inf or to max single */ 313 fe->fe_cx |= FSR_OF | FSR_NX; 314 if (toinf(fe, sign)) 315 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 316 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 317 } 318 done: 319 /* phew, made it */ 320 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 321 } 322 323 /* 324 * fpn -> double (32 bit high-order result returned; 32-bit low order result 325 * left in res[1]). Assumes <= 61 bits in double precision fraction. 326 * 327 * This code mimics fpu_ftos; see it for comments. 328 */ 329 u_int 330 fpu_ftod(fe, fp, res) 331 struct fpemu *fe; 332 register struct fpn *fp; 333 u_int *res; 334 { 335 register u_int sign = fp->fp_sign << 31; 336 register int exp; 337 338 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 339 #define DBL_MASK (DBL_EXP(1) - 1) 340 341 if (ISNAN(fp)) { 342 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 343 exp = DBL_EXP_INFNAN; 344 goto done; 345 } 346 if (ISINF(fp)) { 347 sign |= DBL_EXP(DBL_EXP_INFNAN); 348 goto zero; 349 } 350 if (ISZERO(fp)) { 351 zero: res[1] = 0; 352 return (sign); 353 } 354 355 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 356 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 357 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 358 res[1] = 0; 359 return (sign | DBL_EXP(1) | 0); 360 } 361 if ((fe->fe_cx & FSR_NX) || 362 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 363 fe->fe_cx |= FSR_UF; 364 exp = 0; 365 goto done; 366 } 367 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 368 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 369 exp++; 370 if (exp >= DBL_EXP_INFNAN) { 371 fe->fe_cx |= FSR_OF | FSR_NX; 372 if (toinf(fe, sign)) { 373 res[1] = 0; 374 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 375 } 376 res[1] = ~0; 377 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 378 } 379 done: 380 res[1] = fp->fp_mant[3]; 381 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 382 } 383 384 /* 385 * fpn -> extended (32 bit high-order result returned; low-order fraction 386 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 387 * our internal format *is* extended precision, plus 2 bits for guard/round, 388 * so we can avoid a small bit of work. 389 */ 390 u_int 391 fpu_ftox(fe, fp, res) 392 struct fpemu *fe; 393 register struct fpn *fp; 394 u_int *res; 395 { 396 register u_int sign = fp->fp_sign << 31; 397 register int exp; 398 399 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 400 #define EXT_MASK (EXT_EXP(1) - 1) 401 402 if (ISNAN(fp)) { 403 (void) fpu_shr(fp, 2); /* since we are not rounding */ 404 exp = EXT_EXP_INFNAN; 405 goto done; 406 } 407 if (ISINF(fp)) { 408 sign |= EXT_EXP(EXT_EXP_INFNAN); 409 goto zero; 410 } 411 if (ISZERO(fp)) { 412 zero: res[1] = res[2] = res[3] = 0; 413 return (sign); 414 } 415 416 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 417 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 418 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 419 res[1] = res[2] = res[3] = 0; 420 return (sign | EXT_EXP(1) | 0); 421 } 422 if ((fe->fe_cx & FSR_NX) || 423 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 424 fe->fe_cx |= FSR_UF; 425 exp = 0; 426 goto done; 427 } 428 /* Since internal == extended, no need to shift here. */ 429 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 430 exp++; 431 if (exp >= EXT_EXP_INFNAN) { 432 fe->fe_cx |= FSR_OF | FSR_NX; 433 if (toinf(fe, sign)) { 434 res[1] = res[2] = res[3] = 0; 435 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 436 } 437 res[1] = res[2] = res[3] = ~0; 438 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 439 } 440 done: 441 res[1] = fp->fp_mant[1]; 442 res[2] = fp->fp_mant[2]; 443 res[3] = fp->fp_mant[3]; 444 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 445 } 446 447 /* 448 * Implode an fpn, writing the result into the given space. 449 */ 450 void 451 fpu_implode(fe, fp, type, space) 452 struct fpemu *fe; 453 register struct fpn *fp; 454 int type; 455 register u_int *space; 456 { 457 458 switch (type) { 459 460 case FTYPE_INT: 461 space[0] = fpu_ftoi(fe, fp); 462 break; 463 464 case FTYPE_SNG: 465 space[0] = fpu_ftos(fe, fp); 466 break; 467 468 case FTYPE_DBL: 469 space[0] = fpu_ftod(fe, fp, space); 470 break; 471 472 case FTYPE_EXT: 473 /* funky rounding precision options ?? */ 474 space[0] = fpu_ftox(fe, fp, space); 475 break; 476 477 default: 478 panic("fpu_implode"); 479 } 480 } 481