1 /* $NetBSD: fpu_implode.c,v 1.9 2001/12/04 00:05:05 darrenr Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #if defined(_KERNEL_OPT) 53 #include "opt_sparc_arch.h" 54 #endif 55 56 #include <sys/types.h> 57 #include <sys/systm.h> 58 59 #include <machine/ieee.h> 60 #include <machine/instr.h> 61 #include <machine/reg.h> 62 63 #include <sparc/fpu/fpu_arith.h> 64 #include <sparc/fpu/fpu_emu.h> 65 #include <sparc/fpu/fpu_extern.h> 66 67 static int round __P((register struct fpemu *, register struct fpn *)); 68 static int toinf __P((struct fpemu *, int)); 69 70 /* 71 * Round a number (algorithm from Motorola MC68882 manual, modified for 72 * our internal format). Set inexact exception if rounding is required. 73 * Return true iff we rounded up. 74 * 75 * After rounding, we discard the guard and round bits by shifting right 76 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 77 * This saves effort later. 78 * 79 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 80 * responsibility to fix this if necessary. 81 */ 82 static int 83 round(register struct fpemu *fe, register struct fpn *fp) 84 { 85 register u_int m0, m1, m2, m3; 86 register int gr, s; 87 88 m0 = fp->fp_mant[0]; 89 m1 = fp->fp_mant[1]; 90 m2 = fp->fp_mant[2]; 91 m3 = fp->fp_mant[3]; 92 gr = m3 & 3; 93 s = fp->fp_sticky; 94 95 /* mant >>= FP_NG */ 96 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 97 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 98 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 99 m0 >>= FP_NG; 100 101 if ((gr | s) == 0) /* result is exact: no rounding needed */ 102 goto rounddown; 103 104 fe->fe_cx |= FSR_NX; /* inexact */ 105 106 /* Go to rounddown to round down; break to round up. */ 107 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 108 109 case FSR_RD_RN: 110 default: 111 /* 112 * Round only if guard is set (gr & 2). If guard is set, 113 * but round & sticky both clear, then we want to round 114 * but have a tie, so round to even, i.e., add 1 iff odd. 115 */ 116 if ((gr & 2) == 0) 117 goto rounddown; 118 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 119 break; 120 goto rounddown; 121 122 case FSR_RD_RZ: 123 /* Round towards zero, i.e., down. */ 124 goto rounddown; 125 126 case FSR_RD_RM: 127 /* Round towards -Inf: up if negative, down if positive. */ 128 if (fp->fp_sign) 129 break; 130 goto rounddown; 131 132 case FSR_RD_RP: 133 /* Round towards +Inf: up if positive, down otherwise. */ 134 if (!fp->fp_sign) 135 break; 136 goto rounddown; 137 } 138 139 /* Bump low bit of mantissa, with carry. */ 140 FPU_ADDS(m3, m3, 1); 141 FPU_ADDCS(m2, m2, 0); 142 FPU_ADDCS(m1, m1, 0); 143 FPU_ADDC(m0, m0, 0); 144 fp->fp_mant[0] = m0; 145 fp->fp_mant[1] = m1; 146 fp->fp_mant[2] = m2; 147 fp->fp_mant[3] = m3; 148 return (1); 149 150 rounddown: 151 fp->fp_mant[0] = m0; 152 fp->fp_mant[1] = m1; 153 fp->fp_mant[2] = m2; 154 fp->fp_mant[3] = m3; 155 return (0); 156 } 157 158 /* 159 * For overflow: return true if overflow is to go to +/-Inf, according 160 * to the sign of the overflowing result. If false, overflow is to go 161 * to the largest magnitude value instead. 162 */ 163 static int 164 toinf(struct fpemu *fe, int sign) 165 { 166 int inf; 167 168 /* look at rounding direction */ 169 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 170 171 default: 172 case FSR_RD_RN: /* the nearest value is always Inf */ 173 inf = 1; 174 break; 175 176 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 177 inf = 0; 178 break; 179 180 case FSR_RD_RP: /* toward +Inf iff positive */ 181 inf = sign == 0; 182 break; 183 184 case FSR_RD_RM: /* toward -Inf iff negative */ 185 inf = sign; 186 break; 187 } 188 return (inf); 189 } 190 191 /* 192 * fpn -> int (int value returned as return value). 193 * 194 * N.B.: this conversion always rounds towards zero (this is a peculiarity 195 * of the SPARC instruction set). 196 */ 197 u_int 198 fpu_ftoi(fe, fp) 199 struct fpemu *fe; 200 register struct fpn *fp; 201 { 202 register u_int i; 203 register int sign, exp; 204 205 sign = fp->fp_sign; 206 switch (fp->fp_class) { 207 208 case FPC_ZERO: 209 return (0); 210 211 case FPC_NUM: 212 /* 213 * If exp >= 2^32, overflow. Otherwise shift value right 214 * into last mantissa word (this will not exceed 0xffffffff), 215 * shifting any guard and round bits out into the sticky 216 * bit. Then ``round'' towards zero, i.e., just set an 217 * inexact exception if sticky is set (see round()). 218 * If the result is > 0x80000000, or is positive and equals 219 * 0x80000000, overflow; otherwise the last fraction word 220 * is the result. 221 */ 222 if ((exp = fp->fp_exp) >= 32) 223 break; 224 /* NB: the following includes exp < 0 cases */ 225 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 226 fe->fe_cx |= FSR_NX; 227 i = fp->fp_mant[3]; 228 if (i >= ((u_int)0x80000000 + sign)) 229 break; 230 return (sign ? -i : i); 231 232 default: /* Inf, qNaN, sNaN */ 233 break; 234 } 235 /* overflow: replace any inexact exception with invalid */ 236 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 237 return (0x7fffffff + sign); 238 } 239 240 #ifdef SUN4U 241 /* 242 * fpn -> extended int (high bits of int value returned as return value). 243 * 244 * N.B.: this conversion always rounds towards zero (this is a peculiarity 245 * of the SPARC instruction set). 246 */ 247 u_int 248 fpu_ftox(fe, fp, res) 249 struct fpemu *fe; 250 register struct fpn *fp; 251 u_int *res; 252 { 253 register u_int64_t i; 254 register int sign, exp; 255 256 sign = fp->fp_sign; 257 switch (fp->fp_class) { 258 259 case FPC_ZERO: 260 res[1] = 0; 261 return (0); 262 263 case FPC_NUM: 264 /* 265 * If exp >= 2^64, overflow. Otherwise shift value right 266 * into last mantissa word (this will not exceed 0xffffffffffffffff), 267 * shifting any guard and round bits out into the sticky 268 * bit. Then ``round'' towards zero, i.e., just set an 269 * inexact exception if sticky is set (see round()). 270 * If the result is > 0x8000000000000000, or is positive and equals 271 * 0x8000000000000000, overflow; otherwise the last fraction word 272 * is the result. 273 */ 274 if ((exp = fp->fp_exp) >= 64) 275 break; 276 /* NB: the following includes exp < 0 cases */ 277 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 278 fe->fe_cx |= FSR_NX; 279 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 280 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 281 break; 282 return (sign ? -i : i); 283 284 default: /* Inf, qNaN, sNaN */ 285 break; 286 } 287 /* overflow: replace any inexact exception with invalid */ 288 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 289 return (0x7fffffffffffffffLL + sign); 290 } 291 #endif /* SUN4U */ 292 293 /* 294 * fpn -> single (32 bit single returned as return value). 295 * We assume <= 29 bits in a single-precision fraction (1.f part). 296 */ 297 u_int 298 fpu_ftos(fe, fp) 299 struct fpemu *fe; 300 register struct fpn *fp; 301 { 302 register u_int sign = fp->fp_sign << 31; 303 register int exp; 304 305 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 306 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 307 308 /* Take care of non-numbers first. */ 309 if (ISNAN(fp)) { 310 /* 311 * Preserve upper bits of NaN, per SPARC V8 appendix N. 312 * Note that fp->fp_mant[0] has the quiet bit set, 313 * even if it is classified as a signalling NaN. 314 */ 315 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 316 exp = SNG_EXP_INFNAN; 317 goto done; 318 } 319 if (ISINF(fp)) 320 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 321 if (ISZERO(fp)) 322 return (sign); 323 324 /* 325 * Normals (including subnormals). Drop all the fraction bits 326 * (including the explicit ``implied'' 1 bit) down into the 327 * single-precision range. If the number is subnormal, move 328 * the ``implied'' 1 into the explicit range as well, and shift 329 * right to introduce leading zeroes. Rounding then acts 330 * differently for normals and subnormals: the largest subnormal 331 * may round to the smallest normal (1.0 x 2^minexp), or may 332 * remain subnormal. In the latter case, signal an underflow 333 * if the result was inexact or if underflow traps are enabled. 334 * 335 * Rounding a normal, on the other hand, always produces another 336 * normal (although either way the result might be too big for 337 * single precision, and cause an overflow). If rounding a 338 * normal produces 2.0 in the fraction, we need not adjust that 339 * fraction at all, since both 1.0 and 2.0 are zero under the 340 * fraction mask. 341 * 342 * Note that the guard and round bits vanish from the number after 343 * rounding. 344 */ 345 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 346 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 347 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 348 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 349 return (sign | SNG_EXP(1) | 0); 350 if ((fe->fe_cx & FSR_NX) || 351 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 352 fe->fe_cx |= FSR_UF; 353 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 354 } 355 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 356 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 357 #ifdef DIAGNOSTIC 358 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 359 panic("fpu_ftos"); 360 #endif 361 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 362 exp++; 363 if (exp >= SNG_EXP_INFNAN) { 364 /* overflow to inf or to max single */ 365 fe->fe_cx |= FSR_OF | FSR_NX; 366 if (toinf(fe, sign)) 367 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 368 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 369 } 370 done: 371 /* phew, made it */ 372 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 373 } 374 375 /* 376 * fpn -> double (32 bit high-order result returned; 32-bit low order result 377 * left in res[1]). Assumes <= 61 bits in double precision fraction. 378 * 379 * This code mimics fpu_ftos; see it for comments. 380 */ 381 u_int 382 fpu_ftod(fe, fp, res) 383 struct fpemu *fe; 384 register struct fpn *fp; 385 u_int *res; 386 { 387 register u_int sign = fp->fp_sign << 31; 388 register int exp; 389 390 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 391 #define DBL_MASK (DBL_EXP(1) - 1) 392 393 if (ISNAN(fp)) { 394 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 395 exp = DBL_EXP_INFNAN; 396 goto done; 397 } 398 if (ISINF(fp)) { 399 sign |= DBL_EXP(DBL_EXP_INFNAN); 400 goto zero; 401 } 402 if (ISZERO(fp)) { 403 zero: res[1] = 0; 404 return (sign); 405 } 406 407 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 408 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 409 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 410 res[1] = 0; 411 return (sign | DBL_EXP(1) | 0); 412 } 413 if ((fe->fe_cx & FSR_NX) || 414 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 415 fe->fe_cx |= FSR_UF; 416 exp = 0; 417 goto done; 418 } 419 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 420 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 421 exp++; 422 if (exp >= DBL_EXP_INFNAN) { 423 fe->fe_cx |= FSR_OF | FSR_NX; 424 if (toinf(fe, sign)) { 425 res[1] = 0; 426 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 427 } 428 res[1] = ~0; 429 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 430 } 431 done: 432 res[1] = fp->fp_mant[3]; 433 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 434 } 435 436 /* 437 * fpn -> extended (32 bit high-order result returned; low-order fraction 438 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 439 * our internal format *is* extended precision, plus 2 bits for guard/round, 440 * so we can avoid a small bit of work. 441 */ 442 u_int 443 fpu_ftoq(fe, fp, res) 444 struct fpemu *fe; 445 register struct fpn *fp; 446 u_int *res; 447 { 448 register u_int sign = fp->fp_sign << 31; 449 register int exp; 450 451 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 452 #define EXT_MASK (EXT_EXP(1) - 1) 453 454 if (ISNAN(fp)) { 455 (void) fpu_shr(fp, 2); /* since we are not rounding */ 456 exp = EXT_EXP_INFNAN; 457 goto done; 458 } 459 if (ISINF(fp)) { 460 sign |= EXT_EXP(EXT_EXP_INFNAN); 461 goto zero; 462 } 463 if (ISZERO(fp)) { 464 zero: res[1] = res[2] = res[3] = 0; 465 return (sign); 466 } 467 468 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 469 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 470 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 471 res[1] = res[2] = res[3] = 0; 472 return (sign | EXT_EXP(1) | 0); 473 } 474 if ((fe->fe_cx & FSR_NX) || 475 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 476 fe->fe_cx |= FSR_UF; 477 exp = 0; 478 goto done; 479 } 480 /* Since internal == extended, no need to shift here. */ 481 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 482 exp++; 483 if (exp >= EXT_EXP_INFNAN) { 484 fe->fe_cx |= FSR_OF | FSR_NX; 485 if (toinf(fe, sign)) { 486 res[1] = res[2] = res[3] = 0; 487 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 488 } 489 res[1] = res[2] = res[3] = ~0; 490 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 491 } 492 done: 493 res[1] = fp->fp_mant[1]; 494 res[2] = fp->fp_mant[2]; 495 res[3] = fp->fp_mant[3]; 496 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 497 } 498 499 /* 500 * Implode an fpn, writing the result into the given space. 501 */ 502 void 503 fpu_implode(fe, fp, type, space) 504 struct fpemu *fe; 505 register struct fpn *fp; 506 int type; 507 register u_int *space; 508 { 509 510 switch (type) { 511 512 #ifdef SUN4U 513 case FTYPE_LNG: 514 space[0] = fpu_ftox(fe, fp, space); 515 break; 516 #endif /* SUN4U */ 517 518 case FTYPE_INT: 519 space[0] = fpu_ftoi(fe, fp); 520 break; 521 522 case FTYPE_SNG: 523 space[0] = fpu_ftos(fe, fp); 524 break; 525 526 case FTYPE_DBL: 527 space[0] = fpu_ftod(fe, fp, space); 528 break; 529 530 case FTYPE_EXT: 531 /* funky rounding precision options ?? */ 532 space[0] = fpu_ftoq(fe, fp, space); 533 break; 534 535 default: 536 panic("fpu_implode"); 537 } 538 #ifdef SUN4U 539 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n", 540 space[0], space[1], space[2], space[3])); 541 #else 542 DPRINTF(FPE_REG, ("fpu_implode: %x %x\n", 543 space[0], space[1])); 544 #endif 545 } 546