1 /* $NetBSD: fpu_implode.c,v 1.2 1994/11/20 20:52:42 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `implode' internal format numbers into the machine's 49 * `packed binary' format. 50 */ 51 52 #include <sys/types.h> 53 54 #include <machine/ieee.h> 55 #include <machine/instr.h> 56 #include <machine/reg.h> 57 58 #include <sparc/fpu/fpu_arith.h> 59 #include <sparc/fpu/fpu_emu.h> 60 61 /* 62 * Round a number (algorithm from Motorola MC68882 manual, modified for 63 * our internal format). Set inexact exception if rounding is required. 64 * Return true iff we rounded up. 65 * 66 * After rounding, we discard the guard and round bits by shifting right 67 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 68 * This saves effort later. 69 * 70 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 71 * responsibility to fix this if necessary. 72 */ 73 static int 74 round(register struct fpemu *fe, register struct fpn *fp) 75 { 76 register u_int m0, m1, m2, m3; 77 register int gr, s, ret; 78 79 m0 = fp->fp_mant[0]; 80 m1 = fp->fp_mant[1]; 81 m2 = fp->fp_mant[2]; 82 m3 = fp->fp_mant[3]; 83 gr = m3 & 3; 84 s = fp->fp_sticky; 85 86 /* mant >>= FP_NG */ 87 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 88 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 89 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 90 m0 >>= FP_NG; 91 92 if ((gr | s) == 0) /* result is exact: no rounding needed */ 93 goto rounddown; 94 95 fe->fe_cx |= FSR_NX; /* inexact */ 96 97 /* Go to rounddown to round down; break to round up. */ 98 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 99 100 case FSR_RD_RN: 101 default: 102 /* 103 * Round only if guard is set (gr & 2). If guard is set, 104 * but round & sticky both clear, then we want to round 105 * but have a tie, so round to even, i.e., add 1 iff odd. 106 */ 107 if ((gr & 2) == 0) 108 goto rounddown; 109 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 110 break; 111 goto rounddown; 112 113 case FSR_RD_RZ: 114 /* Round towards zero, i.e., down. */ 115 goto rounddown; 116 117 case FSR_RD_RM: 118 /* Round towards -Inf: up if negative, down if positive. */ 119 if (fp->fp_sign) 120 break; 121 goto rounddown; 122 123 case FSR_RD_RP: 124 /* Round towards +Inf: up if positive, down otherwise. */ 125 if (!fp->fp_sign) 126 break; 127 goto rounddown; 128 } 129 130 /* Bump low bit of mantissa, with carry. */ 131 #ifdef sparc /* ``cheating'' (left out FPU_DECL_CARRY; know this is faster) */ 132 FPU_ADDS(m3, m3, 1); 133 FPU_ADDCS(m2, m2, 0); 134 FPU_ADDCS(m1, m1, 0); 135 FPU_ADDC(m0, m0, 0); 136 #else 137 if (++m3 == 0 && ++m2 == 0 && ++m1 == 0) 138 m0++; 139 #endif 140 fp->fp_mant[0] = m0; 141 fp->fp_mant[1] = m1; 142 fp->fp_mant[2] = m2; 143 fp->fp_mant[3] = m3; 144 return (1); 145 146 rounddown: 147 fp->fp_mant[0] = m0; 148 fp->fp_mant[1] = m1; 149 fp->fp_mant[2] = m2; 150 fp->fp_mant[3] = m3; 151 return (0); 152 } 153 154 /* 155 * For overflow: return true if overflow is to go to +/-Inf, according 156 * to the sign of the overflowing result. If false, overflow is to go 157 * to the largest magnitude value instead. 158 */ 159 static int 160 toinf(struct fpemu *fe, int sign) 161 { 162 int inf; 163 164 /* look at rounding direction */ 165 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 166 167 default: 168 case FSR_RD_RN: /* the nearest value is always Inf */ 169 inf = 1; 170 break; 171 172 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 173 inf = 0; 174 break; 175 176 case FSR_RD_RP: /* toward +Inf iff positive */ 177 inf = sign == 0; 178 break; 179 180 case FSR_RD_RM: /* toward -Inf iff negative */ 181 inf = sign; 182 break; 183 } 184 return (inf); 185 } 186 187 /* 188 * fpn -> int (int value returned as return value). 189 * 190 * N.B.: this conversion always rounds towards zero (this is a peculiarity 191 * of the SPARC instruction set). 192 */ 193 u_int 194 fpu_ftoi(fe, fp) 195 struct fpemu *fe; 196 register struct fpn *fp; 197 { 198 register u_int i; 199 register int sign, exp; 200 201 sign = fp->fp_sign; 202 switch (fp->fp_class) { 203 204 case FPC_ZERO: 205 return (0); 206 207 case FPC_NUM: 208 /* 209 * If exp >= 2^32, overflow. Otherwise shift value right 210 * into last mantissa word (this will not exceed 0xffffffff), 211 * shifting any guard and round bits out into the sticky 212 * bit. Then ``round'' towards zero, i.e., just set an 213 * inexact exception if sticky is set (see round()). 214 * If the result is > 0x80000000, or is positive and equals 215 * 0x80000000, overflow; otherwise the last fraction word 216 * is the result. 217 */ 218 if ((exp = fp->fp_exp) >= 32) 219 break; 220 /* NB: the following includes exp < 0 cases */ 221 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 222 fe->fe_cx |= FSR_NX; 223 i = fp->fp_mant[3]; 224 if (i >= ((u_int)0x80000000 + sign)) 225 break; 226 return (sign ? -i : i); 227 228 default: /* Inf, qNaN, sNaN */ 229 break; 230 } 231 /* overflow: replace any inexact exception with invalid */ 232 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 233 return (0x7fffffff + sign); 234 } 235 236 /* 237 * fpn -> single (32 bit single returned as return value). 238 * We assume <= 29 bits in a single-precision fraction (1.f part). 239 */ 240 u_int 241 fpu_ftos(fe, fp) 242 struct fpemu *fe; 243 register struct fpn *fp; 244 { 245 register u_int sign = fp->fp_sign << 31; 246 register int exp; 247 248 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 249 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 250 251 /* Take care of non-numbers first. */ 252 if (ISNAN(fp)) { 253 /* 254 * Preserve upper bits of NaN, per SPARC V8 appendix N. 255 * Note that fp->fp_mant[0] has the quiet bit set, 256 * even if it is classified as a signalling NaN. 257 */ 258 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 259 exp = SNG_EXP_INFNAN; 260 goto done; 261 } 262 if (ISINF(fp)) 263 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 264 if (ISZERO(fp)) 265 return (sign); 266 267 /* 268 * Normals (including subnormals). Drop all the fraction bits 269 * (including the explicit ``implied'' 1 bit) down into the 270 * single-precision range. If the number is subnormal, move 271 * the ``implied'' 1 into the explicit range as well, and shift 272 * right to introduce leading zeroes. Rounding then acts 273 * differently for normals and subnormals: the largest subnormal 274 * may round to the smallest normal (1.0 x 2^minexp), or may 275 * remain subnormal. In the latter case, signal an underflow 276 * if the result was inexact or if underflow traps are enabled. 277 * 278 * Rounding a normal, on the other hand, always produces another 279 * normal (although either way the result might be too big for 280 * single precision, and cause an overflow). If rounding a 281 * normal produces 2.0 in the fraction, we need not adjust that 282 * fraction at all, since both 1.0 and 2.0 are zero under the 283 * fraction mask. 284 * 285 * Note that the guard and round bits vanish from the number after 286 * rounding. 287 */ 288 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 289 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 290 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 291 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 292 return (sign | SNG_EXP(1) | 0); 293 if ((fe->fe_cx & FSR_NX) || 294 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 295 fe->fe_cx |= FSR_UF; 296 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 297 } 298 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 299 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 300 #ifdef DIAGNOSTIC 301 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 302 panic("fpu_ftos"); 303 #endif 304 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 305 exp++; 306 if (exp >= SNG_EXP_INFNAN) { 307 /* overflow to inf or to max single */ 308 fe->fe_cx |= FSR_OF | FSR_NX; 309 if (toinf(fe, sign)) 310 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 311 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 312 } 313 done: 314 /* phew, made it */ 315 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 316 } 317 318 /* 319 * fpn -> double (32 bit high-order result returned; 32-bit low order result 320 * left in res[1]). Assumes <= 61 bits in double precision fraction. 321 * 322 * This code mimics fpu_ftos; see it for comments. 323 */ 324 u_int 325 fpu_ftod(fe, fp, res) 326 struct fpemu *fe; 327 register struct fpn *fp; 328 u_int *res; 329 { 330 register u_int sign = fp->fp_sign << 31; 331 register int exp; 332 333 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 334 #define DBL_MASK (DBL_EXP(1) - 1) 335 336 if (ISNAN(fp)) { 337 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 338 exp = DBL_EXP_INFNAN; 339 goto done; 340 } 341 if (ISINF(fp)) { 342 sign |= DBL_EXP(DBL_EXP_INFNAN); 343 goto zero; 344 } 345 if (ISZERO(fp)) { 346 zero: res[1] = 0; 347 return (sign); 348 } 349 350 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 351 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 352 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 353 res[1] = 0; 354 return (sign | DBL_EXP(1) | 0); 355 } 356 if ((fe->fe_cx & FSR_NX) || 357 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 358 fe->fe_cx |= FSR_UF; 359 exp = 0; 360 goto done; 361 } 362 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 363 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 364 exp++; 365 if (exp >= DBL_EXP_INFNAN) { 366 fe->fe_cx |= FSR_OF | FSR_NX; 367 if (toinf(fe, sign)) { 368 res[1] = 0; 369 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 370 } 371 res[1] = ~0; 372 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 373 } 374 done: 375 res[1] = fp->fp_mant[3]; 376 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 377 } 378 379 /* 380 * fpn -> extended (32 bit high-order result returned; low-order fraction 381 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 382 * our internal format *is* extended precision, plus 2 bits for guard/round, 383 * so we can avoid a small bit of work. 384 */ 385 u_int 386 fpu_ftox(fe, fp, res) 387 struct fpemu *fe; 388 register struct fpn *fp; 389 u_int *res; 390 { 391 register u_int sign = fp->fp_sign << 31; 392 register int exp; 393 394 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 395 #define EXT_MASK (EXT_EXP(1) - 1) 396 397 if (ISNAN(fp)) { 398 (void) fpu_shr(fp, 2); /* since we are not rounding */ 399 exp = EXT_EXP_INFNAN; 400 goto done; 401 } 402 if (ISINF(fp)) { 403 sign |= EXT_EXP(EXT_EXP_INFNAN); 404 goto zero; 405 } 406 if (ISZERO(fp)) { 407 zero: res[1] = res[2] = res[3] = 0; 408 return (sign); 409 } 410 411 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 412 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 413 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 414 res[1] = res[2] = res[3] = 0; 415 return (sign | EXT_EXP(1) | 0); 416 } 417 if ((fe->fe_cx & FSR_NX) || 418 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 419 fe->fe_cx |= FSR_UF; 420 exp = 0; 421 goto done; 422 } 423 /* Since internal == extended, no need to shift here. */ 424 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 425 exp++; 426 if (exp >= EXT_EXP_INFNAN) { 427 fe->fe_cx |= FSR_OF | FSR_NX; 428 if (toinf(fe, sign)) { 429 res[1] = res[2] = res[3] = 0; 430 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 431 } 432 res[1] = res[2] = res[3] = ~0; 433 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 434 } 435 done: 436 res[1] = fp->fp_mant[1]; 437 res[2] = fp->fp_mant[2]; 438 res[3] = fp->fp_mant[3]; 439 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 440 } 441 442 /* 443 * Implode an fpn, writing the result into the given space. 444 */ 445 void 446 fpu_implode(fe, fp, type, space) 447 struct fpemu *fe; 448 register struct fpn *fp; 449 int type; 450 register u_int *space; 451 { 452 453 switch (type) { 454 455 case FTYPE_INT: 456 space[0] = fpu_ftoi(fe, fp); 457 break; 458 459 case FTYPE_SNG: 460 space[0] = fpu_ftos(fe, fp); 461 break; 462 463 case FTYPE_DBL: 464 space[0] = fpu_ftod(fe, fp, space); 465 break; 466 467 case FTYPE_EXT: 468 /* funky rounding precision options ?? */ 469 space[0] = fpu_ftox(fe, fp, space); 470 break; 471 472 default: 473 panic("fpu_implode"); 474 } 475 } 476