1 /* $NetBSD: fpu_explode.c,v 1.3 1996/03/14 19:41:54 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `explode' the machine's `packed binary' format numbers 49 * into our internal format. 50 */ 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/ieee.h> 56 #include <machine/instr.h> 57 #include <machine/reg.h> 58 59 #include <sparc/fpu/fpu_arith.h> 60 #include <sparc/fpu/fpu_emu.h> 61 #include <sparc/fpu/fpu_extern.h> 62 63 /* 64 * N.B.: in all of the following, we assume the FP format is 65 * 66 * --------------------------- 67 * | s | exponent | fraction | 68 * --------------------------- 69 * 70 * (which represents -1**s * 1.fraction * 2**exponent), so that the 71 * sign bit is way at the top (bit 31), the exponent is next, and 72 * then the remaining bits mark the fraction. A zero exponent means 73 * zero or denormalized (0.fraction rather than 1.fraction), and the 74 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 75 * 76 * Since the sign bit is always the topmost bit---this holds even for 77 * integers---we set that outside all the *tof functions. Each function 78 * returns the class code for the new number (but note that we use 79 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 80 */ 81 82 /* 83 * int -> fpn. 84 */ 85 int 86 fpu_itof(fp, i) 87 register struct fpn *fp; 88 register u_int i; 89 { 90 91 if (i == 0) 92 return (FPC_ZERO); 93 /* 94 * The value FP_1 represents 2^FP_LG, so set the exponent 95 * there and let normalization fix it up. Convert negative 96 * numbers to sign-and-magnitude. Note that this relies on 97 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 98 */ 99 fp->fp_exp = FP_LG; 100 fp->fp_mant[0] = (int)i < 0 ? -i : i; 101 fp->fp_mant[1] = 0; 102 fp->fp_mant[2] = 0; 103 fp->fp_mant[3] = 0; 104 fpu_norm(fp); 105 return (FPC_NUM); 106 } 107 108 #define mask(nbits) ((1 << (nbits)) - 1) 109 110 /* 111 * All external floating formats convert to internal in the same manner, 112 * as defined here. Note that only normals get an implied 1.0 inserted. 113 */ 114 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 115 if (exp == 0) { \ 116 if (allfrac == 0) \ 117 return (FPC_ZERO); \ 118 fp->fp_exp = 1 - expbias; \ 119 fp->fp_mant[0] = f0; \ 120 fp->fp_mant[1] = f1; \ 121 fp->fp_mant[2] = f2; \ 122 fp->fp_mant[3] = f3; \ 123 fpu_norm(fp); \ 124 return (FPC_NUM); \ 125 } \ 126 if (exp == (2 * expbias + 1)) { \ 127 if (allfrac == 0) \ 128 return (FPC_INF); \ 129 fp->fp_mant[0] = f0; \ 130 fp->fp_mant[1] = f1; \ 131 fp->fp_mant[2] = f2; \ 132 fp->fp_mant[3] = f3; \ 133 return (FPC_QNAN); \ 134 } \ 135 fp->fp_exp = exp - expbias; \ 136 fp->fp_mant[0] = FP_1 | f0; \ 137 fp->fp_mant[1] = f1; \ 138 fp->fp_mant[2] = f2; \ 139 fp->fp_mant[3] = f3; \ 140 return (FPC_NUM) 141 142 /* 143 * 32-bit single precision -> fpn. 144 * We assume a single occupies at most (64-FP_LG) bits in the internal 145 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 146 */ 147 int 148 fpu_stof(fp, i) 149 register struct fpn *fp; 150 register u_int i; 151 { 152 register int exp; 153 register u_int frac, f0, f1; 154 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 155 156 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 157 frac = i & mask(SNG_FRACBITS); 158 f0 = frac >> SNG_SHIFT; 159 f1 = frac << (32 - SNG_SHIFT); 160 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 161 } 162 163 /* 164 * 64-bit double -> fpn. 165 * We assume this uses at most (96-FP_LG) bits. 166 */ 167 int 168 fpu_dtof(fp, i, j) 169 register struct fpn *fp; 170 register u_int i, j; 171 { 172 register int exp; 173 register u_int frac, f0, f1, f2; 174 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 175 176 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 177 frac = i & mask(DBL_FRACBITS - 32); 178 f0 = frac >> DBL_SHIFT; 179 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 180 f2 = j << (32 - DBL_SHIFT); 181 frac |= j; 182 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 183 } 184 185 /* 186 * 128-bit extended -> fpn. 187 */ 188 int 189 fpu_xtof(fp, i, j, k, l) 190 register struct fpn *fp; 191 register u_int i, j, k, l; 192 { 193 register int exp; 194 register u_int frac, f0, f1, f2, f3; 195 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 196 197 /* 198 * Note that ext and fpn `line up', hence no shifting needed. 199 */ 200 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 201 frac = i & mask(EXT_FRACBITS - 3 * 32); 202 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 203 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 204 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 205 f3 = l << EXT_SHIFT; 206 frac |= j | k | l; 207 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 208 } 209 210 /* 211 * Explode the contents of a register / regpair / regquad. 212 * If the input is a signalling NaN, an NV (invalid) exception 213 * will be set. (Note that nothing but NV can occur until ALU 214 * operations are performed.) 215 */ 216 void 217 fpu_explode(fe, fp, type, reg) 218 register struct fpemu *fe; 219 register struct fpn *fp; 220 int type, reg; 221 { 222 register u_int s, *space; 223 224 space = &fe->fe_fpstate->fs_regs[reg]; 225 s = space[0]; 226 fp->fp_sign = s >> 31; 227 fp->fp_sticky = 0; 228 switch (type) { 229 230 case FTYPE_INT: 231 s = fpu_itof(fp, s); 232 break; 233 234 case FTYPE_SNG: 235 s = fpu_stof(fp, s); 236 break; 237 238 case FTYPE_DBL: 239 s = fpu_dtof(fp, s, space[1]); 240 break; 241 242 case FTYPE_EXT: 243 s = fpu_xtof(fp, s, space[1], space[2], space[3]); 244 break; 245 246 default: 247 panic("fpu_explode"); 248 } 249 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 250 /* 251 * Input is a signalling NaN. All operations that return 252 * an input NaN operand put it through a ``NaN conversion'', 253 * which basically just means ``turn on the quiet bit''. 254 * We do this here so that all NaNs internally look quiet 255 * (we can tell signalling ones by their class). 256 */ 257 fp->fp_mant[0] |= FP_QUIETBIT; 258 fe->fe_cx = FSR_NV; /* assert invalid operand */ 259 s = FPC_SNAN; 260 } 261 fp->fp_class = s; 262 } 263