1 /* $NetBSD: fpu_explode.c,v 1.2 1994/11/20 20:52:41 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `explode' the machine's `packed binary' format numbers 49 * into our internal format. 50 */ 51 52 #include <sys/types.h> 53 54 #include <machine/ieee.h> 55 #include <machine/instr.h> 56 #include <machine/reg.h> 57 58 #include <sparc/fpu/fpu_arith.h> 59 #include <sparc/fpu/fpu_emu.h> 60 61 /* 62 * N.B.: in all of the following, we assume the FP format is 63 * 64 * --------------------------- 65 * | s | exponent | fraction | 66 * --------------------------- 67 * 68 * (which represents -1**s * 1.fraction * 2**exponent), so that the 69 * sign bit is way at the top (bit 31), the exponent is next, and 70 * then the remaining bits mark the fraction. A zero exponent means 71 * zero or denormalized (0.fraction rather than 1.fraction), and the 72 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 73 * 74 * Since the sign bit is always the topmost bit---this holds even for 75 * integers---we set that outside all the *tof functions. Each function 76 * returns the class code for the new number (but note that we use 77 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 78 */ 79 80 /* 81 * int -> fpn. 82 */ 83 int 84 fpu_itof(fp, i) 85 register struct fpn *fp; 86 register u_int i; 87 { 88 89 if (i == 0) 90 return (FPC_ZERO); 91 /* 92 * The value FP_1 represents 2^FP_LG, so set the exponent 93 * there and let normalization fix it up. Convert negative 94 * numbers to sign-and-magnitude. Note that this relies on 95 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 96 */ 97 fp->fp_exp = FP_LG; 98 fp->fp_mant[0] = (int)i < 0 ? -i : i; 99 fp->fp_mant[1] = 0; 100 fp->fp_mant[2] = 0; 101 fp->fp_mant[3] = 0; 102 fpu_norm(fp); 103 return (FPC_NUM); 104 } 105 106 #define mask(nbits) ((1 << (nbits)) - 1) 107 108 /* 109 * All external floating formats convert to internal in the same manner, 110 * as defined here. Note that only normals get an implied 1.0 inserted. 111 */ 112 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 113 if (exp == 0) { \ 114 if (allfrac == 0) \ 115 return (FPC_ZERO); \ 116 fp->fp_exp = 1 - expbias; \ 117 fp->fp_mant[0] = f0; \ 118 fp->fp_mant[1] = f1; \ 119 fp->fp_mant[2] = f2; \ 120 fp->fp_mant[3] = f3; \ 121 fpu_norm(fp); \ 122 return (FPC_NUM); \ 123 } \ 124 if (exp == (2 * expbias + 1)) { \ 125 if (allfrac == 0) \ 126 return (FPC_INF); \ 127 fp->fp_mant[0] = f0; \ 128 fp->fp_mant[1] = f1; \ 129 fp->fp_mant[2] = f2; \ 130 fp->fp_mant[3] = f3; \ 131 return (FPC_QNAN); \ 132 } \ 133 fp->fp_exp = exp - expbias; \ 134 fp->fp_mant[0] = FP_1 | f0; \ 135 fp->fp_mant[1] = f1; \ 136 fp->fp_mant[2] = f2; \ 137 fp->fp_mant[3] = f3; \ 138 return (FPC_NUM) 139 140 /* 141 * 32-bit single precision -> fpn. 142 * We assume a single occupies at most (64-FP_LG) bits in the internal 143 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 144 */ 145 int 146 fpu_stof(fp, i) 147 register struct fpn *fp; 148 register u_int i; 149 { 150 register int exp; 151 register u_int frac, f0, f1; 152 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 153 154 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 155 frac = i & mask(SNG_FRACBITS); 156 f0 = frac >> SNG_SHIFT; 157 f1 = frac << (32 - SNG_SHIFT); 158 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 159 } 160 161 /* 162 * 64-bit double -> fpn. 163 * We assume this uses at most (96-FP_LG) bits. 164 */ 165 int 166 fpu_dtof(fp, i, j) 167 register struct fpn *fp; 168 register u_int i, j; 169 { 170 register int exp; 171 register u_int frac, f0, f1, f2; 172 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 173 174 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 175 frac = i & mask(DBL_FRACBITS - 32); 176 f0 = frac >> DBL_SHIFT; 177 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 178 f2 = j << (32 - DBL_SHIFT); 179 frac |= j; 180 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 181 } 182 183 /* 184 * 128-bit extended -> fpn. 185 */ 186 int 187 fpu_xtof(fp, i, j, k, l) 188 register struct fpn *fp; 189 register u_int i, j, k, l; 190 { 191 register int exp; 192 register u_int frac, f0, f1, f2, f3; 193 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 194 195 /* 196 * Note that ext and fpn `line up', hence no shifting needed. 197 */ 198 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 199 frac = i & mask(EXT_FRACBITS - 3 * 32); 200 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 201 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 202 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 203 f3 = l << EXT_SHIFT; 204 frac |= j | k | l; 205 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 206 } 207 208 /* 209 * Explode the contents of a register / regpair / regquad. 210 * If the input is a signalling NaN, an NV (invalid) exception 211 * will be set. (Note that nothing but NV can occur until ALU 212 * operations are performed.) 213 */ 214 void 215 fpu_explode(fe, fp, type, reg) 216 register struct fpemu *fe; 217 register struct fpn *fp; 218 int type, reg; 219 { 220 register u_int s, *space; 221 222 space = &fe->fe_fpstate->fs_regs[reg]; 223 s = space[0]; 224 fp->fp_sign = s >> 31; 225 fp->fp_sticky = 0; 226 switch (type) { 227 228 case FTYPE_INT: 229 s = fpu_itof(fp, s); 230 break; 231 232 case FTYPE_SNG: 233 s = fpu_stof(fp, s); 234 break; 235 236 case FTYPE_DBL: 237 s = fpu_dtof(fp, s, space[1]); 238 break; 239 240 case FTYPE_EXT: 241 s = fpu_xtof(fp, s, space[1], space[2], space[3]); 242 break; 243 244 default: 245 panic("fpu_explode"); 246 } 247 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 248 /* 249 * Input is a signalling NaN. All operations that return 250 * an input NaN operand put it through a ``NaN conversion'', 251 * which basically just means ``turn on the quiet bit''. 252 * We do this here so that all NaNs internally look quiet 253 * (we can tell signalling ones by their class). 254 */ 255 fp->fp_mant[0] |= FP_QUIETBIT; 256 fe->fe_cx = FSR_NV; /* assert invalid operand */ 257 s = FPC_SNAN; 258 } 259 fp->fp_class = s; 260 } 261