1 /* $NetBSD: fpu.c,v 1.18 2003/05/10 13:26:44 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 #include <sys/param.h> 48 #include <sys/proc.h> 49 #include <sys/signal.h> 50 #include <sys/systm.h> 51 #include <sys/syslog.h> 52 #include <sys/signalvar.h> 53 54 #include <machine/instr.h> 55 #include <machine/reg.h> 56 57 #include <sparc/fpu/fpu_emu.h> 58 #include <sparc/fpu/fpu_extern.h> 59 60 int fpe_debug = 0; 61 62 #ifdef DEBUG 63 /* 64 * Dump a `fpn' structure. 65 */ 66 void 67 fpu_dumpfpn(struct fpn *fp) 68 { 69 static char *class[] = { 70 "SNAN", "QNAN", "ZERO", "NUM", "INF" 71 }; 72 73 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 74 fp->fp_sign ? '-' : ' ', 75 fp->fp_mant[0], fp->fp_mant[1], 76 fp->fp_mant[2], fp->fp_mant[3], 77 fp->fp_exp); 78 } 79 #endif 80 81 /* 82 * fpu_execute returns the following error numbers (0 = no error): 83 */ 84 #define FPE 1 /* take a floating point exception */ 85 #define NOTFPU 2 /* not an FPU instruction */ 86 87 /* 88 * Translate current exceptions into `first' exception. The 89 * bits go the wrong way for ffs() (0x10 is most important, etc). 90 * There are only 5, so do it the obvious way. 91 */ 92 #define X1(x) x 93 #define X2(x) x,x 94 #define X4(x) x,x,x,x 95 #define X8(x) X4(x),X4(x) 96 #define X16(x) X8(x),X8(x) 97 98 static char cx_to_trapx[] = { 99 X1(FSR_NX), 100 X2(FSR_DZ), 101 X4(FSR_UF), 102 X8(FSR_OF), 103 X16(FSR_NV) 104 }; 105 static u_char fpu_codes[] = { 106 X1(FPE_FLTINEX_TRAP), 107 X2(FPE_FLTDIV_TRAP), 108 X4(FPE_FLTUND_TRAP), 109 X8(FPE_FLTOVF_TRAP), 110 X16(FPE_FLTOPERR_TRAP) 111 }; 112 113 /* 114 * The FPU gave us an exception. Clean up the mess. Note that the 115 * fp queue can only have FPops in it, never load/store FP registers 116 * nor FBfcc instructions. Experiments with `crashme' prove that 117 * unknown FPops do enter the queue, however. 118 */ 119 void 120 fpu_cleanup(l, fs) 121 register struct lwp *l; 122 #ifndef SUN4U 123 register struct fpstate *fs; 124 #else /* SUN4U */ 125 register struct fpstate64 *fs; 126 #endif /* SUN4U */ 127 { 128 register int i, fsr = fs->fs_fsr, error; 129 struct proc *p = l->l_proc; 130 union instr instr; 131 struct fpemu fe; 132 133 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 134 135 case FSR_TT_NONE: 136 panic("fpu_cleanup: No fault"); /* ??? */ 137 break; 138 139 case FSR_TT_IEEE: 140 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_IEEE\n")); 141 /* XXX missing trap address! */ 142 if ((i = fsr & FSR_CX) == 0) 143 panic("fpu ieee trap, but no exception"); 144 KERNEL_PROC_LOCK(l); 145 trapsignal(l, SIGFPE, fpu_codes[i - 1]); 146 KERNEL_PROC_UNLOCK(l); 147 break; /* XXX should return, but queue remains */ 148 149 case FSR_TT_UNFIN: 150 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNFIN\n")); 151 #ifdef SUN4U 152 if (fs->fs_qsize == 0) { 153 printf("fpu_cleanup: unfinished fpop"); 154 /* The book sez reexecute or emulate. */ 155 return; 156 } 157 break; 158 159 #endif /* SUN4U */ 160 case FSR_TT_UNIMP: 161 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNIMP\n")); 162 if (fs->fs_qsize == 0) 163 panic("fpu_cleanup: unimplemented fpop"); 164 break; 165 166 case FSR_TT_SEQ: 167 panic("fpu sequence error"); 168 /* NOTREACHED */ 169 170 case FSR_TT_HWERR: 171 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_HWERR\n")); 172 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 173 p->p_comm, p->p_pid); 174 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 175 KERNEL_PROC_LOCK(l); 176 trapsignal(l, SIGFPE, -1); /* ??? */ 177 KERNEL_PROC_UNLOCK(l); 178 goto out; 179 180 default: 181 printf("fsr=0x%x\n", fsr); 182 panic("fpu error"); 183 } 184 185 /* emulate the instructions left in the queue */ 186 fe.fe_fpstate = fs; 187 for (i = 0; i < fs->fs_qsize; i++) { 188 instr.i_int = fs->fs_queue[i].fq_instr; 189 if (instr.i_any.i_op != IOP_reg || 190 (instr.i_op3.i_op3 != IOP3_FPop1 && 191 instr.i_op3.i_op3 != IOP3_FPop2)) 192 panic("bogus fpu queue"); 193 error = fpu_execute(&fe, instr); 194 if (error == 0) 195 continue; 196 197 KERNEL_PROC_LOCK(l); 198 switch (error) { 199 case FPE: 200 trapsignal(l, SIGFPE, 201 fpu_codes[(fs->fs_fsr & FSR_CX) - 1]); 202 break; 203 204 case NOTFPU: 205 #ifdef SUN4U 206 #ifdef DEBUG 207 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n"); 208 #endif 209 #endif /* SUN4U */ 210 trapsignal(l, SIGILL, 0); /* ??? code? */ 211 break; 212 213 default: 214 panic("fpu_cleanup 3"); 215 /* NOTREACHED */ 216 } 217 KERNEL_PROC_UNLOCK(l); 218 /* XXX should stop here, but queue remains */ 219 } 220 out: 221 fs->fs_qsize = 0; 222 } 223 224 #ifdef notyet 225 /* 226 * If we have no FPU at all (are there any machines like this out 227 * there!?) we have to emulate each instruction, and we need a pointer 228 * to the trapframe so that we can step over them and do FBfcc's. 229 * We know the `queue' is empty, though; we just want to emulate 230 * the instruction at tf->tf_pc. 231 */ 232 fpu_emulate(l, tf, fs) 233 struct lwp *l; 234 register struct trapframe *tf; 235 #ifndef SUN4U 236 register struct fpstate *fs; 237 #else /* SUN4U */ 238 register struct fpstate64 *fs; 239 #endif /* SUN4U */ 240 { 241 242 do { 243 fetch instr from pc 244 decode 245 if (integer instr) { 246 /* 247 * We do this here, rather than earlier, to avoid 248 * losing even more badly than usual. 249 */ 250 if (l->l_addr->u_pcb.pcb_uw) { 251 write_user_windows(); 252 if (rwindow_save(l)) 253 sigexit(l, SIGILL); 254 } 255 if (loadstore) { 256 do_it; 257 pc = npc, npc += 4 258 } else if (fbfcc) { 259 do_annul_stuff; 260 } else 261 return; 262 } else if (fpu instr) { 263 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 264 error = fpu_execute(&fe, fs, instr); 265 switch (error) { 266 etc; 267 } 268 } else 269 return; 270 if (want to reschedule) 271 return; 272 } while (error == 0); 273 } 274 #endif 275 276 /* 277 * Execute an FPU instruction (one that runs entirely in the FPU; not 278 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 279 * modified to reflect the setting the hardware would have left. 280 * 281 * Note that we do not catch all illegal opcodes, so you can, for instance, 282 * multiply two integers this way. 283 */ 284 int 285 fpu_execute(fe, instr) 286 register struct fpemu *fe; 287 union instr instr; 288 { 289 register struct fpn *fp; 290 #ifndef SUN4U 291 register int opf, rs1, rs2, rd, type, mask, fsr, cx; 292 register struct fpstate *fs; 293 #else /* SUN4U */ 294 register int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 295 register struct fpstate64 *fs; 296 #endif /* SUN4U */ 297 u_int space[4]; 298 299 /* 300 * `Decode' and execute instruction. Start with no exceptions. 301 * The type of any i_opf opcode is in the bottom two bits, so we 302 * squish them out here. 303 */ 304 opf = instr.i_opf.i_opf; 305 /* 306 * The low two bits of the opf field for floating point insns usually 307 * correspond to the operation width: 308 * 309 * 0: Invalid 310 * 1: Single precision float 311 * 2: Double precision float 312 * 3: Quad precision float 313 * 314 * The exceptions are the integer to float conversion instructions. 315 * 316 * For double and quad precision, the low bit if the rs or rd field 317 * is actually the high bit of the register number. 318 */ 319 320 type = opf & 3; 321 mask = 0x3 >> (3 - type); 322 323 rs1 = instr.i_opf.i_rs1; 324 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5); 325 rs2 = instr.i_opf.i_rs2; 326 rs2 = (rs2 & ~mask) | ((rs2 & mask & 0x1) << 5); 327 rd = instr.i_opf.i_rd; 328 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 329 #ifdef DIAGNOSTIC 330 if ((rs1 | rs2 | rd) & mask) 331 /* This may be an FPU insn but it is illegal. */ 332 return (NOTFPU); 333 #endif 334 fs = fe->fe_fpstate; 335 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 336 fe->fe_cx = 0; 337 #ifdef SUN4U 338 /* 339 * Check to see if we're dealing with a fancy cmove and handle 340 * it first. 341 */ 342 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 343 switch (opf >>= 2) { 344 case FMVFC0 >> 2: 345 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n")); 346 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 347 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 348 rs1 = fs->fs_regs[rs2]; 349 goto mov; 350 case FMVFC1 >> 2: 351 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n")); 352 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 353 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 354 rs1 = fs->fs_regs[rs2]; 355 goto mov; 356 case FMVFC2 >> 2: 357 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n")); 358 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 359 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 360 rs1 = fs->fs_regs[rs2]; 361 goto mov; 362 case FMVFC3 >> 2: 363 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n")); 364 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 365 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 366 rs1 = fs->fs_regs[rs2]; 367 goto mov; 368 case FMVIC >> 2: 369 /* Presume we're curlwp */ 370 DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n")); 371 cond = (curlwp->l_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 372 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 373 rs1 = fs->fs_regs[rs2]; 374 goto mov; 375 case FMVXC >> 2: 376 /* Presume we're curlwp */ 377 DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n")); 378 cond = (curlwp->l_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 379 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 380 rs1 = fs->fs_regs[rs2]; 381 goto mov; 382 case FMVRZ >> 2: 383 /* Presume we're curlwp */ 384 DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n")); 385 rs1 = instr.i_fmovr.i_rs1; 386 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] != 0) 387 return (0); /* success */ 388 rs1 = fs->fs_regs[rs2]; 389 goto mov; 390 case FMVRLEZ >> 2: 391 /* Presume we're curlwp */ 392 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n")); 393 rs1 = instr.i_fmovr.i_rs1; 394 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] > 0) 395 return (0); /* success */ 396 rs1 = fs->fs_regs[rs2]; 397 goto mov; 398 case FMVRLZ >> 2: 399 /* Presume we're curlwp */ 400 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n")); 401 rs1 = instr.i_fmovr.i_rs1; 402 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] >= 0) 403 return (0); /* success */ 404 rs1 = fs->fs_regs[rs2]; 405 goto mov; 406 case FMVRNZ >> 2: 407 /* Presume we're curlwp */ 408 DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n")); 409 rs1 = instr.i_fmovr.i_rs1; 410 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] == 0) 411 return (0); /* success */ 412 rs1 = fs->fs_regs[rs2]; 413 goto mov; 414 case FMVRGZ >> 2: 415 /* Presume we're curlwp */ 416 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n")); 417 rs1 = instr.i_fmovr.i_rs1; 418 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] <= 0) 419 return (0); /* success */ 420 rs1 = fs->fs_regs[rs2]; 421 goto mov; 422 case FMVRGEZ >> 2: 423 /* Presume we're curlwp */ 424 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n")); 425 rs1 = instr.i_fmovr.i_rs1; 426 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] < 0) 427 return (0); /* success */ 428 rs1 = fs->fs_regs[rs2]; 429 goto mov; 430 default: 431 DPRINTF(FPE_INSN, 432 ("fpu_execute: unknown v9 FP inst %x opf %x\n", 433 instr.i_int, opf)); 434 return (NOTFPU); 435 } 436 } 437 #endif /* SUN4U */ 438 switch (opf >>= 2) { 439 440 default: 441 DPRINTF(FPE_INSN, 442 ("fpu_execute: unknown basic FP inst %x opf %x\n", 443 instr.i_int, opf)); 444 return (NOTFPU); 445 446 case FMOV >> 2: /* these should all be pretty obvious */ 447 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n")); 448 rs1 = fs->fs_regs[rs2]; 449 goto mov; 450 451 case FNEG >> 2: 452 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n")); 453 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 454 goto mov; 455 456 case FABS >> 2: 457 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 458 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 459 mov: 460 #ifndef SUN4U 461 fs->fs_regs[rd] = rs1; 462 #else /* SUN4U */ 463 i = 1<<(type-1); 464 fs->fs_regs[rd++] = rs1; 465 while (--i > 0) 466 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 467 #endif /* SUN4U */ 468 fs->fs_fsr = fe->fe_fsr; 469 return (0); /* success */ 470 471 case FSQRT >> 2: 472 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 473 fpu_explode(fe, &fe->fe_f1, type, rs2); 474 fp = fpu_sqrt(fe); 475 break; 476 477 case FADD >> 2: 478 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 479 fpu_explode(fe, &fe->fe_f1, type, rs1); 480 fpu_explode(fe, &fe->fe_f2, type, rs2); 481 fp = fpu_add(fe); 482 break; 483 484 case FSUB >> 2: 485 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 486 fpu_explode(fe, &fe->fe_f1, type, rs1); 487 fpu_explode(fe, &fe->fe_f2, type, rs2); 488 fp = fpu_sub(fe); 489 break; 490 491 case FMUL >> 2: 492 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 493 fpu_explode(fe, &fe->fe_f1, type, rs1); 494 fpu_explode(fe, &fe->fe_f2, type, rs2); 495 fp = fpu_mul(fe); 496 break; 497 498 case FDIV >> 2: 499 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 500 fpu_explode(fe, &fe->fe_f1, type, rs1); 501 fpu_explode(fe, &fe->fe_f2, type, rs2); 502 fp = fpu_div(fe); 503 break; 504 505 case FCMP >> 2: 506 DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n")); 507 fpu_explode(fe, &fe->fe_f1, type, rs1); 508 fpu_explode(fe, &fe->fe_f2, type, rs2); 509 fpu_compare(fe, 0); 510 goto cmpdone; 511 512 case FCMPE >> 2: 513 DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n")); 514 fpu_explode(fe, &fe->fe_f1, type, rs1); 515 fpu_explode(fe, &fe->fe_f2, type, rs2); 516 fpu_compare(fe, 1); 517 cmpdone: 518 /* 519 * The only possible exception here is NV; catch it 520 * early and get out, as there is no result register. 521 */ 522 cx = fe->fe_cx; 523 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 524 if (cx != 0) { 525 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 526 fs->fs_fsr = (fsr & ~FSR_FTT) | 527 (FSR_TT_IEEE << FSR_FTT_SHIFT); 528 return (FPE); 529 } 530 fsr |= FSR_NV << FSR_AX_SHIFT; 531 } 532 fs->fs_fsr = fsr; 533 return (0); 534 535 case FSMULD >> 2: 536 case FDMULX >> 2: 537 DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n")); 538 if (type == FTYPE_EXT) 539 return (NOTFPU); 540 fpu_explode(fe, &fe->fe_f1, type, rs1); 541 fpu_explode(fe, &fe->fe_f2, type, rs2); 542 type++; /* single to double, or double to quad */ 543 fp = fpu_mul(fe); 544 break; 545 546 #ifdef SUN4U 547 case FXTOS >> 2: 548 case FXTOD >> 2: 549 case FXTOQ >> 2: 550 DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n")); 551 type = FTYPE_LNG; 552 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 553 type = opf & 3; /* sneaky; depends on instruction encoding */ 554 break; 555 556 case FTOX >> 2: 557 DPRINTF(FPE_INSN, ("fpu_execute: FTOX\n")); 558 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 559 type = FTYPE_LNG; 560 /* Recalculate destination register */ 561 rd = instr.i_opf.i_rd; 562 break; 563 564 #endif /* SUN4U */ 565 case FTOI >> 2: 566 DPRINTF(FPE_INSN, ("fpu_execute: FTOI\n")); 567 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 568 type = FTYPE_INT; 569 /* Recalculate destination register */ 570 rd = instr.i_opf.i_rd; 571 break; 572 573 case FTOS >> 2: 574 case FTOD >> 2: 575 case FTOQ >> 2: 576 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 577 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 578 /* Recalculate rd with correct type info. */ 579 type = opf & 3; /* sneaky; depends on instruction encoding */ 580 mask = 0x3 >> (3 - type); 581 rd = instr.i_opf.i_rd; 582 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 583 break; 584 } 585 586 /* 587 * ALU operation is complete. Collapse the result and then check 588 * for exceptions. If we got any, and they are enabled, do not 589 * alter the destination register, just stop with an exception. 590 * Otherwise set new current exceptions and accrue. 591 */ 592 fpu_implode(fe, fp, type, space); 593 cx = fe->fe_cx; 594 fsr = fe->fe_fsr; 595 if (cx != 0) { 596 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 597 if (cx & mask) { 598 /* not accrued??? */ 599 fs->fs_fsr = (fsr & ~FSR_FTT) | 600 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 601 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 602 return (FPE); 603 } 604 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 605 } 606 fs->fs_fsr = fsr; 607 DPRINTF(FPE_REG, ("-> %c%d\n", (type == FTYPE_LNG) ? 'x' : 608 ((type == FTYPE_INT) ? 'i' : 609 ((type == FTYPE_SNG) ? 's' : 610 ((type == FTYPE_DBL) ? 'd' : 611 ((type == FTYPE_EXT) ? 'q' : '?')))), 612 rd)); 613 fs->fs_regs[rd] = space[0]; 614 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 615 fs->fs_regs[rd + 1] = space[1]; 616 if (type > FTYPE_DBL) { 617 fs->fs_regs[rd + 2] = space[2]; 618 fs->fs_regs[rd + 3] = space[3]; 619 } 620 } 621 return (0); /* success */ 622 } 623