1 /* $NetBSD: fpu.c,v 1.25 2005/11/16 23:24:44 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.25 2005/11/16 23:24:44 uwe Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/proc.h> 48 #include <sys/signal.h> 49 #include <sys/systm.h> 50 #include <sys/syslog.h> 51 #include <sys/signalvar.h> 52 53 #include <machine/instr.h> 54 #include <machine/reg.h> 55 56 #include <sparc/fpu/fpu_emu.h> 57 #include <sparc/fpu/fpu_extern.h> 58 59 int fpe_debug = 0; 60 61 #ifdef DEBUG 62 /* 63 * Dump a `fpn' structure. 64 */ 65 void 66 fpu_dumpfpn(struct fpn *fp) 67 { 68 static const char *class[] = { 69 "SNAN", "QNAN", "ZERO", "NUM", "INF" 70 }; 71 72 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 73 fp->fp_sign ? '-' : ' ', 74 fp->fp_mant[0], fp->fp_mant[1], 75 fp->fp_mant[2], fp->fp_mant[3], 76 fp->fp_exp); 77 } 78 #endif 79 80 /* 81 * fpu_execute returns the following error numbers (0 = no error): 82 */ 83 #define FPE 1 /* take a floating point exception */ 84 #define NOTFPU 2 /* not an FPU instruction */ 85 86 /* 87 * Translate current exceptions into `first' exception. The 88 * bits go the wrong way for ffs() (0x10 is most important, etc). 89 * There are only 5, so do it the obvious way. 90 */ 91 #define X1(x) x 92 #define X2(x) x,x 93 #define X4(x) x,x,x,x 94 #define X8(x) X4(x),X4(x) 95 #define X16(x) X8(x),X8(x) 96 97 static char cx_to_trapx[] = { 98 X1(FSR_NX), 99 X2(FSR_DZ), 100 X4(FSR_UF), 101 X8(FSR_OF), 102 X16(FSR_NV) 103 }; 104 static u_char fpu_codes_native[] = { 105 X1(FPE_FLTRES), 106 X2(FPE_FLTDIV), 107 X4(FPE_FLTUND), 108 X8(FPE_FLTOVF), 109 X16(FPE_FLTINV) 110 }; 111 #if defined(COMPAT_SUNOS) 112 static u_char fpu_codes_sunos[] = { 113 X1(FPE_FLTINEX_TRAP), 114 X2(FPE_FLTDIV_TRAP), 115 X4(FPE_FLTUND_TRAP), 116 X8(FPE_FLTOVF_TRAP), 117 X16(FPE_FLTOPERR_TRAP) 118 }; 119 extern struct emul emul_sunos; 120 #endif /* SUNOS_COMPAT */ 121 /* Note: SVR4(Solaris) FPE_* codes happen to be compatible with ours */ 122 123 /* 124 * The FPU gave us an exception. Clean up the mess. Note that the 125 * fp queue can only have FPops in it, never load/store FP registers 126 * nor FBfcc instructions. Experiments with `crashme' prove that 127 * unknown FPops do enter the queue, however. 128 */ 129 int 130 fpu_cleanup(l, fs) 131 struct lwp *l; 132 #ifndef SUN4U 133 struct fpstate *fs; 134 #else /* SUN4U */ 135 struct fpstate64 *fs; 136 #endif /* SUN4U */ 137 { 138 int i, fsr = fs->fs_fsr, error; 139 struct proc *p = l->l_proc; 140 union instr instr; 141 struct fpemu fe; 142 u_char *fpu_codes; 143 int code = 0; 144 145 fpu_codes = 146 #ifdef COMPAT_SUNOS 147 (p->p_emul == &emul_sunos) ? fpu_codes_sunos : 148 #endif 149 fpu_codes_native; 150 151 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 152 153 case FSR_TT_NONE: 154 panic("fpu_cleanup: No fault"); /* ??? */ 155 break; 156 157 case FSR_TT_IEEE: 158 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_IEEE\n")); 159 /* XXX missing trap address! */ 160 if ((i = fsr & FSR_CX) == 0) 161 panic("fpu ieee trap, but no exception"); 162 code = fpu_codes[i - 1]; 163 break; /* XXX should return, but queue remains */ 164 165 case FSR_TT_UNFIN: 166 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNFIN\n")); 167 #ifdef SUN4U 168 if (fs->fs_qsize == 0) { 169 printf("fpu_cleanup: unfinished fpop"); 170 /* The book sez reexecute or emulate. */ 171 return (0); 172 } 173 break; 174 175 #endif /* SUN4U */ 176 case FSR_TT_UNIMP: 177 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNIMP\n")); 178 if (fs->fs_qsize == 0) 179 panic("fpu_cleanup: unimplemented fpop"); 180 break; 181 182 case FSR_TT_SEQ: 183 panic("fpu sequence error"); 184 /* NOTREACHED */ 185 186 case FSR_TT_HWERR: 187 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_HWERR\n")); 188 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 189 p->p_comm, p->p_pid); 190 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 191 code = SI_NOINFO; 192 goto out; 193 194 default: 195 printf("fsr=0x%x\n", fsr); 196 panic("fpu error"); 197 } 198 199 /* emulate the instructions left in the queue */ 200 fe.fe_fpstate = fs; 201 for (i = 0; i < fs->fs_qsize; i++) { 202 instr.i_int = fs->fs_queue[i].fq_instr; 203 if (instr.i_any.i_op != IOP_reg || 204 (instr.i_op3.i_op3 != IOP3_FPop1 && 205 instr.i_op3.i_op3 != IOP3_FPop2)) 206 panic("bogus fpu queue"); 207 error = fpu_execute(&fe, instr); 208 if (error == 0) 209 continue; 210 211 switch (error) { 212 case FPE: 213 code = fpu_codes[(fs->fs_fsr & FSR_CX) - 1]; 214 break; 215 216 case NOTFPU: 217 #ifdef SUN4U 218 #ifdef DEBUG 219 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n"); 220 #endif 221 #endif /* SUN4U */ 222 code = SI_NOINFO; 223 break; 224 225 default: 226 panic("fpu_cleanup 3"); 227 /* NOTREACHED */ 228 } 229 /* XXX should stop here, but queue remains */ 230 } 231 out: 232 fs->fs_qsize = 0; 233 return (code); 234 } 235 236 #ifdef notyet 237 /* 238 * If we have no FPU at all (are there any machines like this out 239 * there!?) we have to emulate each instruction, and we need a pointer 240 * to the trapframe so that we can step over them and do FBfcc's. 241 * We know the `queue' is empty, though; we just want to emulate 242 * the instruction at tf->tf_pc. 243 */ 244 fpu_emulate(l, tf, fs) 245 struct lwp *l; 246 struct trapframe *tf; 247 #ifndef SUN4U 248 struct fpstate *fs; 249 #else /* SUN4U */ 250 struct fpstate64 *fs; 251 #endif /* SUN4U */ 252 { 253 254 do { 255 fetch instr from pc 256 decode 257 if (integer instr) { 258 /* 259 * We do this here, rather than earlier, to avoid 260 * losing even more badly than usual. 261 */ 262 if (l->l_addr->u_pcb.pcb_uw) { 263 write_user_windows(); 264 if (rwindow_save(l)) 265 sigexit(l, SIGILL); 266 } 267 if (loadstore) { 268 do_it; 269 pc = npc, npc += 4 270 } else if (fbfcc) { 271 do_annul_stuff; 272 } else 273 return; 274 } else if (fpu instr) { 275 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 276 error = fpu_execute(&fe, fs, instr); 277 switch (error) { 278 etc; 279 } 280 } else 281 return; 282 if (want to reschedule) 283 return; 284 } while (error == 0); 285 } 286 #endif 287 288 /* 289 * Execute an FPU instruction (one that runs entirely in the FPU; not 290 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 291 * modified to reflect the setting the hardware would have left. 292 * 293 * Note that we do not catch all illegal opcodes, so you can, for instance, 294 * multiply two integers this way. 295 */ 296 int 297 fpu_execute(struct fpemu *fe, union instr instr) 298 { 299 struct fpn *fp; 300 #ifndef SUN4U 301 int opf, rs1, rs2, rd, type, mask, fsr, cx; 302 struct fpstate *fs; 303 #else /* SUN4U */ 304 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 305 struct fpstate64 *fs; 306 #endif /* SUN4U */ 307 u_int space[4]; 308 309 /* 310 * `Decode' and execute instruction. Start with no exceptions. 311 * The type of any i_opf opcode is in the bottom two bits, so we 312 * squish them out here. 313 */ 314 opf = instr.i_opf.i_opf; 315 /* 316 * The low two bits of the opf field for floating point insns usually 317 * correspond to the operation width: 318 * 319 * 0: Invalid 320 * 1: Single precision float 321 * 2: Double precision float 322 * 3: Quad precision float 323 * 324 * The exceptions are the integer to float conversion instructions. 325 * 326 * For double and quad precision, the low bit if the rs or rd field 327 * is actually the high bit of the register number. 328 */ 329 330 type = opf & 3; 331 mask = 0x3 >> (3 - type); 332 333 rs1 = instr.i_opf.i_rs1; 334 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5); 335 rs2 = instr.i_opf.i_rs2; 336 rs2 = (rs2 & ~mask) | ((rs2 & mask & 0x1) << 5); 337 rd = instr.i_opf.i_rd; 338 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 339 #ifdef DIAGNOSTIC 340 if ((rs1 | rs2 | rd) & mask) 341 /* This may be an FPU insn but it is illegal. */ 342 return (NOTFPU); 343 #endif 344 fs = fe->fe_fpstate; 345 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 346 fe->fe_cx = 0; 347 #ifdef SUN4U 348 /* 349 * Check to see if we're dealing with a fancy cmove and handle 350 * it first. 351 */ 352 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 353 switch (opf >>= 2) { 354 case FMVFC0 >> 2: 355 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n")); 356 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 357 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 358 rs1 = fs->fs_regs[rs2]; 359 goto mov; 360 case FMVFC1 >> 2: 361 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n")); 362 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 363 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 364 rs1 = fs->fs_regs[rs2]; 365 goto mov; 366 case FMVFC2 >> 2: 367 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n")); 368 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 369 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 370 rs1 = fs->fs_regs[rs2]; 371 goto mov; 372 case FMVFC3 >> 2: 373 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n")); 374 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 375 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 376 rs1 = fs->fs_regs[rs2]; 377 goto mov; 378 case FMVIC >> 2: 379 /* Presume we're curlwp */ 380 DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n")); 381 cond = (curlwp->l_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 382 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 383 rs1 = fs->fs_regs[rs2]; 384 goto mov; 385 case FMVXC >> 2: 386 /* Presume we're curlwp */ 387 DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n")); 388 cond = (curlwp->l_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 389 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 390 rs1 = fs->fs_regs[rs2]; 391 goto mov; 392 case FMVRZ >> 2: 393 /* Presume we're curlwp */ 394 DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n")); 395 rs1 = instr.i_fmovr.i_rs1; 396 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] != 0) 397 return (0); /* success */ 398 rs1 = fs->fs_regs[rs2]; 399 goto mov; 400 case FMVRLEZ >> 2: 401 /* Presume we're curlwp */ 402 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n")); 403 rs1 = instr.i_fmovr.i_rs1; 404 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] > 0) 405 return (0); /* success */ 406 rs1 = fs->fs_regs[rs2]; 407 goto mov; 408 case FMVRLZ >> 2: 409 /* Presume we're curlwp */ 410 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n")); 411 rs1 = instr.i_fmovr.i_rs1; 412 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] >= 0) 413 return (0); /* success */ 414 rs1 = fs->fs_regs[rs2]; 415 goto mov; 416 case FMVRNZ >> 2: 417 /* Presume we're curlwp */ 418 DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n")); 419 rs1 = instr.i_fmovr.i_rs1; 420 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] == 0) 421 return (0); /* success */ 422 rs1 = fs->fs_regs[rs2]; 423 goto mov; 424 case FMVRGZ >> 2: 425 /* Presume we're curlwp */ 426 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n")); 427 rs1 = instr.i_fmovr.i_rs1; 428 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] <= 0) 429 return (0); /* success */ 430 rs1 = fs->fs_regs[rs2]; 431 goto mov; 432 case FMVRGEZ >> 2: 433 /* Presume we're curlwp */ 434 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n")); 435 rs1 = instr.i_fmovr.i_rs1; 436 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] < 0) 437 return (0); /* success */ 438 rs1 = fs->fs_regs[rs2]; 439 goto mov; 440 default: 441 DPRINTF(FPE_INSN, 442 ("fpu_execute: unknown v9 FP inst %x opf %x\n", 443 instr.i_int, opf)); 444 return (NOTFPU); 445 } 446 } 447 #endif /* SUN4U */ 448 switch (opf >>= 2) { 449 450 default: 451 DPRINTF(FPE_INSN, 452 ("fpu_execute: unknown basic FP inst %x opf %x\n", 453 instr.i_int, opf)); 454 return (NOTFPU); 455 456 case FMOV >> 2: /* these should all be pretty obvious */ 457 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n")); 458 rs1 = fs->fs_regs[rs2]; 459 goto mov; 460 461 case FNEG >> 2: 462 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n")); 463 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 464 goto mov; 465 466 case FABS >> 2: 467 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 468 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 469 mov: 470 #ifndef SUN4U 471 fs->fs_regs[rd] = rs1; 472 #else /* SUN4U */ 473 i = 1<<(type-1); 474 fs->fs_regs[rd++] = rs1; 475 while (--i > 0) 476 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 477 #endif /* SUN4U */ 478 fs->fs_fsr = fe->fe_fsr; 479 return (0); /* success */ 480 481 case FSQRT >> 2: 482 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 483 fpu_explode(fe, &fe->fe_f1, type, rs2); 484 fp = fpu_sqrt(fe); 485 break; 486 487 case FADD >> 2: 488 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 489 fpu_explode(fe, &fe->fe_f1, type, rs1); 490 fpu_explode(fe, &fe->fe_f2, type, rs2); 491 fp = fpu_add(fe); 492 break; 493 494 case FSUB >> 2: 495 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 496 fpu_explode(fe, &fe->fe_f1, type, rs1); 497 fpu_explode(fe, &fe->fe_f2, type, rs2); 498 fp = fpu_sub(fe); 499 break; 500 501 case FMUL >> 2: 502 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 503 fpu_explode(fe, &fe->fe_f1, type, rs1); 504 fpu_explode(fe, &fe->fe_f2, type, rs2); 505 fp = fpu_mul(fe); 506 break; 507 508 case FDIV >> 2: 509 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 510 fpu_explode(fe, &fe->fe_f1, type, rs1); 511 fpu_explode(fe, &fe->fe_f2, type, rs2); 512 fp = fpu_div(fe); 513 break; 514 515 case FCMP >> 2: 516 DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n")); 517 fpu_explode(fe, &fe->fe_f1, type, rs1); 518 fpu_explode(fe, &fe->fe_f2, type, rs2); 519 fpu_compare(fe, 0); 520 goto cmpdone; 521 522 case FCMPE >> 2: 523 DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n")); 524 fpu_explode(fe, &fe->fe_f1, type, rs1); 525 fpu_explode(fe, &fe->fe_f2, type, rs2); 526 fpu_compare(fe, 1); 527 cmpdone: 528 /* 529 * The only possible exception here is NV; catch it 530 * early and get out, as there is no result register. 531 */ 532 cx = fe->fe_cx; 533 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 534 if (cx != 0) { 535 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 536 fs->fs_fsr = (fsr & ~FSR_FTT) | 537 (FSR_TT_IEEE << FSR_FTT_SHIFT); 538 return (FPE); 539 } 540 fsr |= FSR_NV << FSR_AX_SHIFT; 541 } 542 fs->fs_fsr = fsr; 543 return (0); 544 545 case FSMULD >> 2: 546 case FDMULX >> 2: 547 DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n")); 548 if (type == FTYPE_EXT) 549 return (NOTFPU); 550 fpu_explode(fe, &fe->fe_f1, type, rs1); 551 fpu_explode(fe, &fe->fe_f2, type, rs2); 552 type++; /* single to double, or double to quad */ 553 fp = fpu_mul(fe); 554 break; 555 556 #ifdef SUN4U 557 case FXTOS >> 2: 558 case FXTOD >> 2: 559 case FXTOQ >> 2: 560 DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n")); 561 type = FTYPE_LNG; 562 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 563 type = opf & 3; /* sneaky; depends on instruction encoding */ 564 break; 565 566 case FTOX >> 2: 567 DPRINTF(FPE_INSN, ("fpu_execute: FTOX\n")); 568 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 569 type = FTYPE_LNG; 570 /* Recalculate destination register */ 571 rd = instr.i_opf.i_rd; 572 break; 573 574 #endif /* SUN4U */ 575 case FTOI >> 2: 576 DPRINTF(FPE_INSN, ("fpu_execute: FTOI\n")); 577 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 578 type = FTYPE_INT; 579 /* Recalculate destination register */ 580 rd = instr.i_opf.i_rd; 581 break; 582 583 case FTOS >> 2: 584 case FTOD >> 2: 585 case FTOQ >> 2: 586 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 587 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 588 /* Recalculate rd with correct type info. */ 589 type = opf & 3; /* sneaky; depends on instruction encoding */ 590 mask = 0x3 >> (3 - type); 591 rd = instr.i_opf.i_rd; 592 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 593 break; 594 } 595 596 /* 597 * ALU operation is complete. Collapse the result and then check 598 * for exceptions. If we got any, and they are enabled, do not 599 * alter the destination register, just stop with an exception. 600 * Otherwise set new current exceptions and accrue. 601 */ 602 fpu_implode(fe, fp, type, space); 603 cx = fe->fe_cx; 604 fsr = fe->fe_fsr; 605 if (cx != 0) { 606 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 607 if (cx & mask) { 608 /* not accrued??? */ 609 fs->fs_fsr = (fsr & ~FSR_FTT) | 610 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 611 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 612 return (FPE); 613 } 614 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 615 } 616 fs->fs_fsr = fsr; 617 DPRINTF(FPE_REG, ("-> %c%d\n", (type == FTYPE_LNG) ? 'x' : 618 ((type == FTYPE_INT) ? 'i' : 619 ((type == FTYPE_SNG) ? 's' : 620 ((type == FTYPE_DBL) ? 'd' : 621 ((type == FTYPE_EXT) ? 'q' : '?')))), 622 rd)); 623 fs->fs_regs[rd] = space[0]; 624 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 625 fs->fs_regs[rd + 1] = space[1]; 626 if (type > FTYPE_DBL) { 627 fs->fs_regs[rd + 2] = space[2]; 628 fs->fs_regs[rd + 3] = space[3]; 629 } 630 } 631 return (0); /* success */ 632 } 633