1 /* $NetBSD: zs.c,v 1.97 2003/01/28 12:35:35 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kgdb.h" 49 #include "opt_sparc_arch.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/device.h> 55 #include <sys/file.h> 56 #include <sys/ioctl.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> 59 #include <sys/tty.h> 60 #include <sys/time.h> 61 #include <sys/syslog.h> 62 63 #include <machine/bsd_openprom.h> 64 #include <machine/autoconf.h> 65 #include <machine/intr.h> 66 #include <machine/eeprom.h> 67 #include <machine/psl.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 73 #include <sparc/sparc/vaddrs.h> 74 #include <sparc/sparc/auxreg.h> 75 #include <sparc/sparc/auxiotwo.h> 76 #include <sparc/dev/cons.h> 77 78 #include "kbd.h" /* NKBD */ 79 #include "zs.h" /* NZS */ 80 81 /* Make life easier for the initialized arrays here. */ 82 #if NZS < 3 83 #undef NZS 84 #define NZS 3 85 #endif 86 87 /* 88 * Some warts needed by z8530tty.c - 89 * The default parity REALLY needs to be the same as the PROM uses, 90 * or you can not see messages done with printf during boot-up... 91 */ 92 int zs_def_cflag = (CREAD | CS8 | HUPCL); 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 100 101 /* The layout of this is hardware-dependent (padding, order). */ 102 struct zschan { 103 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 104 u_char zc_xxx0; 105 volatile u_char zc_data; /* data */ 106 u_char zc_xxx1; 107 }; 108 struct zsdevice { 109 /* Yes, they are backwards. */ 110 struct zschan zs_chan_b; 111 struct zschan zs_chan_a; 112 }; 113 114 /* ZS channel used as the console device (if any) */ 115 void *zs_conschan_get, *zs_conschan_put; 116 117 static u_char zs_init_reg[16] = { 118 0, /* 0: CMD (reset, etc.) */ 119 0, /* 1: No interrupts yet. */ 120 0, /* 2: IVECT */ 121 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 122 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 123 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 124 0, /* 6: TXSYNC/SYNCLO */ 125 0, /* 7: RXSYNC/SYNCHI */ 126 0, /* 8: alias for data port */ 127 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 128 0, /*10: Misc. TX/RX control bits */ 129 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 130 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 131 0, /*13: BAUDHI (default=9600) */ 132 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 133 ZSWR15_BREAK_IE, 134 }; 135 136 /* Console ops */ 137 static int zscngetc __P((dev_t)); 138 static void zscnputc __P((dev_t, int)); 139 static void zscnpollc __P((dev_t, int)); 140 141 struct consdev zs_consdev = { 142 NULL, 143 NULL, 144 zscngetc, 145 zscnputc, 146 zscnpollc, 147 NULL, 148 }; 149 150 151 /**************************************************************** 152 * Autoconfig 153 ****************************************************************/ 154 155 /* Definition of the driver for autoconfig. */ 156 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 157 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 158 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 159 static void zs_attach_obio __P((struct device *, struct device *, void *)); 160 161 #if defined(SUN4D) 162 #include <sparc/dev/bootbusvar.h> 163 164 static int zs_match_bootbus __P((struct device *, struct cfdata *, void *)); 165 static void zs_attach_bootbus __P((struct device *, struct device *, void *)); 166 167 CFATTACH_DECL(zs_bootbus, sizeof(struct zsc_softc), 168 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 169 #endif /* SUN4D */ 170 171 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 172 static int zs_print __P((void *, const char *name)); 173 174 CFATTACH_DECL(zs_mainbus, sizeof(struct zsc_softc), 175 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 176 177 CFATTACH_DECL(zs_obio, sizeof(struct zsc_softc), 178 zs_match_obio, zs_attach_obio, NULL, NULL); 179 180 extern struct cfdriver zs_cd; 181 182 /* softintr(9) cookie, shared by all instances of this driver */ 183 static void *zs_sicookie; 184 185 /* Interrupt handlers. */ 186 static int zshard __P((void *)); 187 static void zssoft __P((void *)); 188 189 static int zs_get_speed __P((struct zs_chanstate *)); 190 191 /* Console device support */ 192 static int zs_console_flags __P((int, int, int)); 193 194 /* Power management hooks */ 195 int zs_enable __P((struct zs_chanstate *)); 196 void zs_disable __P((struct zs_chanstate *)); 197 198 199 /* 200 * Is the zs chip present? 201 */ 202 static int 203 zs_match_mainbus(parent, cf, aux) 204 struct device *parent; 205 struct cfdata *cf; 206 void *aux; 207 { 208 struct mainbus_attach_args *ma = aux; 209 210 if (strcmp(cf->cf_name, ma->ma_name) != 0) 211 return (0); 212 213 return (1); 214 } 215 216 static int 217 zs_match_obio(parent, cf, aux) 218 struct device *parent; 219 struct cfdata *cf; 220 void *aux; 221 { 222 union obio_attach_args *uoba = aux; 223 struct obio4_attach_args *oba; 224 225 if (uoba->uoba_isobio4 == 0) { 226 struct sbus_attach_args *sa = &uoba->uoba_sbus; 227 228 if (strcmp(cf->cf_name, sa->sa_name) != 0) 229 return (0); 230 231 return (1); 232 } 233 234 oba = &uoba->uoba_oba4; 235 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 236 1, 0, 0, NULL, NULL)); 237 } 238 239 #if defined(SUN4D) 240 static int 241 zs_match_bootbus(parent, cf, aux) 242 struct device *parent; 243 struct cfdata *cf; 244 void *aux; 245 { 246 struct bootbus_attach_args *baa = aux; 247 248 return (strcmp(cf->cf_name, baa->ba_name) == 0); 249 } 250 #endif /* SUN4D */ 251 252 static void 253 zs_attach_mainbus(parent, self, aux) 254 struct device *parent; 255 struct device *self; 256 void *aux; 257 { 258 struct zsc_softc *zsc = (void *) self; 259 struct mainbus_attach_args *ma = aux; 260 261 zsc->zsc_bustag = ma->ma_bustag; 262 zsc->zsc_dmatag = ma->ma_dmatag; 263 zsc->zsc_promunit = PROM_getpropint(ma->ma_node, "slave", -2); 264 zsc->zsc_node = ma->ma_node; 265 266 /* 267 * For machines with zs on mainbus (all sun4c models), we expect 268 * the device registers to be mapped by the PROM. 269 */ 270 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 271 } 272 273 static void 274 zs_attach_obio(parent, self, aux) 275 struct device *parent; 276 struct device *self; 277 void *aux; 278 { 279 struct zsc_softc *zsc = (void *) self; 280 union obio_attach_args *uoba = aux; 281 282 if (uoba->uoba_isobio4 == 0) { 283 struct sbus_attach_args *sa = &uoba->uoba_sbus; 284 void *va; 285 struct zs_chanstate *cs; 286 int channel; 287 288 if (sa->sa_nintr == 0) { 289 printf(" no interrupt lines\n"); 290 return; 291 } 292 293 /* 294 * Some sun4m models (Javastations) may not map the zs device. 295 */ 296 if (sa->sa_npromvaddrs > 0) 297 va = (void *)sa->sa_promvaddr; 298 else { 299 bus_space_handle_t bh; 300 301 if (sbus_bus_map(sa->sa_bustag, 302 sa->sa_slot, 303 sa->sa_offset, 304 sa->sa_size, 305 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 306 printf(" cannot map zs registers\n"); 307 return; 308 } 309 va = (void *)bh; 310 } 311 312 /* 313 * Check if power state can be set, e.g. Tadpole 3GX 314 */ 315 if (PROM_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 316 { 317 printf (" powered via auxio2"); 318 for (channel = 0; channel < 2; channel++) { 319 cs = &zsc->zsc_cs_store[channel]; 320 cs->enable = zs_enable; 321 cs->disable = zs_disable; 322 } 323 } 324 325 zsc->zsc_bustag = sa->sa_bustag; 326 zsc->zsc_dmatag = sa->sa_dmatag; 327 zsc->zsc_promunit = PROM_getpropint(sa->sa_node, "slave", -2); 328 zsc->zsc_node = sa->sa_node; 329 zs_attach(zsc, va, sa->sa_pri); 330 } else { 331 struct obio4_attach_args *oba = &uoba->uoba_oba4; 332 bus_space_handle_t bh; 333 bus_addr_t paddr = oba->oba_paddr; 334 335 /* 336 * As for zs on mainbus, we require a PROM mapping. 337 */ 338 if (bus_space_map(oba->oba_bustag, 339 paddr, 340 sizeof(struct zsdevice), 341 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 342 &bh) != 0) { 343 printf(" cannot map zs registers\n"); 344 return; 345 } 346 zsc->zsc_bustag = oba->oba_bustag; 347 zsc->zsc_dmatag = oba->oba_dmatag; 348 /* 349 * Find prom unit by physical address 350 * We're just comparing the address (not the iospace) here 351 */ 352 paddr = BUS_ADDR_PADDR(paddr); 353 if (cpuinfo.cpu_type == CPUTYP_4_100) 354 /* 355 * On the sun4/100, the top-most 4 bits are zero 356 * on obio addresses; force them to 1's for the 357 * sake of the comparison here. 358 */ 359 paddr |= 0xf0000000; 360 zsc->zsc_promunit = 361 (paddr == 0xf1000000) ? 0 : 362 (paddr == 0xf0000000) ? 1 : 363 (paddr == 0xe0000000) ? 2 : -2; 364 365 zs_attach(zsc, (void *)bh, oba->oba_pri); 366 } 367 } 368 369 #if defined(SUN4D) 370 static void 371 zs_attach_bootbus(parent, self, aux) 372 struct device *parent; 373 struct device *self; 374 void *aux; 375 { 376 struct zsc_softc *zsc = (void *) self; 377 struct bootbus_attach_args *baa = aux; 378 void *va; 379 380 if (baa->ba_nintr == 0) { 381 printf(": no interrupt lines\n"); 382 return; 383 } 384 385 if (baa->ba_npromvaddrs > 0) 386 va = (void *) baa->ba_promvaddrs; 387 else { 388 bus_space_handle_t bh; 389 390 if (bus_space_map(baa->ba_bustag, 391 BUS_ADDR(baa->ba_slot, baa->ba_offset), 392 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 393 printf(": cannot map zs registers\n"); 394 return; 395 } 396 va = (void *) bh; 397 } 398 399 zsc->zsc_bustag = baa->ba_bustag; 400 zsc->zsc_promunit = PROM_getpropint(baa->ba_node, "slave", -2); 401 zsc->zsc_node = baa->ba_node; 402 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 403 } 404 #endif /* SUN4D */ 405 406 /* 407 * Attach a found zs. 408 * 409 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 410 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 411 */ 412 static void 413 zs_attach(zsc, zsd, pri) 414 struct zsc_softc *zsc; 415 struct zsdevice *zsd; 416 int pri; 417 { 418 struct zsc_attach_args zsc_args; 419 struct zs_chanstate *cs; 420 int s, channel; 421 static int didintr, prevpri; 422 423 if (zsd == NULL) { 424 printf("configuration incomplete\n"); 425 return; 426 } 427 428 if (!didintr) { 429 zs_sicookie = softintr_establish(IPL_SOFTSERIAL, zssoft, NULL); 430 if (zs_sicookie == NULL) { 431 printf("\n%s: cannot establish soft int handler\n", 432 zsc->zsc_dev.dv_xname); 433 return; 434 } 435 } 436 printf(" softpri %d\n", IPL_SOFTSERIAL); 437 438 /* 439 * Initialize software state for each channel. 440 */ 441 for (channel = 0; channel < 2; channel++) { 442 struct zschan *zc; 443 444 zsc_args.channel = channel; 445 cs = &zsc->zsc_cs_store[channel]; 446 zsc->zsc_cs[channel] = cs; 447 448 simple_lock_init(&cs->cs_lock); 449 cs->cs_channel = channel; 450 cs->cs_private = NULL; 451 cs->cs_ops = &zsops_null; 452 cs->cs_brg_clk = PCLK / 16; 453 454 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 455 456 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 457 zsc->zsc_node, 458 channel); 459 460 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 461 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 462 zsc_args.consdev = &zs_consdev; 463 } 464 465 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 466 zs_conschan_get = zc; 467 } 468 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 469 zs_conschan_put = zc; 470 } 471 /* Childs need to set cn_dev, etc */ 472 473 cs->cs_reg_csr = &zc->zc_csr; 474 cs->cs_reg_data = &zc->zc_data; 475 476 bcopy(zs_init_reg, cs->cs_creg, 16); 477 bcopy(zs_init_reg, cs->cs_preg, 16); 478 479 /* XXX: Consult PROM properties for this?! */ 480 cs->cs_defspeed = zs_get_speed(cs); 481 cs->cs_defcflag = zs_def_cflag; 482 483 /* Make these correspond to cs_defcflag (-crtscts) */ 484 cs->cs_rr0_dcd = ZSRR0_DCD; 485 cs->cs_rr0_cts = 0; 486 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 487 cs->cs_wr5_rts = 0; 488 489 /* 490 * Clear the master interrupt enable. 491 * The INTENA is common to both channels, 492 * so just do it on the A channel. 493 */ 494 if (channel == 0) { 495 zs_write_reg(cs, 9, 0); 496 } 497 498 /* 499 * Look for a child driver for this channel. 500 * The child attach will setup the hardware. 501 */ 502 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 503 /* No sub-driver. Just reset it. */ 504 u_char reset = (channel == 0) ? 505 ZSWR9_A_RESET : ZSWR9_B_RESET; 506 s = splzs(); 507 zs_write_reg(cs, 9, reset); 508 splx(s); 509 } 510 } 511 512 /* 513 * Now safe to install interrupt handlers. Note the arguments 514 * to the interrupt handlers aren't used. Note, we only do this 515 * once since both SCCs interrupt at the same level and vector. 516 */ 517 if (!didintr) { 518 didintr = 1; 519 prevpri = pri; 520 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 521 zshard, NULL); 522 } else if (pri != prevpri) 523 panic("broken zs interrupt scheme"); 524 525 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 526 zsc->zsc_dev.dv_xname, "intr"); 527 528 /* 529 * Set the master interrupt enable and interrupt vector. 530 * (common to both channels, do it on A) 531 */ 532 cs = zsc->zsc_cs[0]; 533 s = splhigh(); 534 /* interrupt vector */ 535 zs_write_reg(cs, 2, zs_init_reg[2]); 536 /* master interrupt control (enable) */ 537 zs_write_reg(cs, 9, zs_init_reg[9]); 538 splx(s); 539 540 #if 0 541 /* 542 * XXX: L1A hack - We would like to be able to break into 543 * the debugger during the rest of autoconfiguration, so 544 * lower interrupts just enough to let zs interrupts in. 545 * This is done after both zs devices are attached. 546 */ 547 if (zsc->zsc_promunit == 1) { 548 printf("zs1: enabling zs interrupts\n"); 549 (void)splfd(); /* XXX: splzs - 1 */ 550 } 551 #endif 552 } 553 554 static int 555 zs_print(aux, name) 556 void *aux; 557 const char *name; 558 { 559 struct zsc_attach_args *args = aux; 560 561 if (name != NULL) 562 aprint_normal("%s: ", name); 563 564 if (args->channel != -1) 565 aprint_normal(" channel %d", args->channel); 566 567 return (UNCONF); 568 } 569 570 static volatile int zssoftpending; 571 572 /* 573 * Our ZS chips all share a common, autovectored interrupt, 574 * so we have to look at all of them on each interrupt. 575 */ 576 static int 577 zshard(arg) 578 void *arg; 579 { 580 struct zsc_softc *zsc; 581 int unit, rr3, rval, softreq; 582 583 rval = softreq = 0; 584 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 585 struct zs_chanstate *cs; 586 587 zsc = zs_cd.cd_devs[unit]; 588 if (zsc == NULL) 589 continue; 590 rr3 = zsc_intr_hard(zsc); 591 /* Count up the interrupts. */ 592 if (rr3) { 593 rval |= rr3; 594 zsc->zsc_intrcnt.ev_count++; 595 } 596 if ((cs = zsc->zsc_cs[0]) != NULL) 597 softreq |= cs->cs_softreq; 598 if ((cs = zsc->zsc_cs[1]) != NULL) 599 softreq |= cs->cs_softreq; 600 } 601 602 /* We are at splzs here, so no need to lock. */ 603 if (softreq && (zssoftpending == 0)) { 604 zssoftpending = 1; 605 softintr_schedule(zs_sicookie); 606 } 607 return (rval); 608 } 609 610 /* 611 * Similar scheme as for zshard (look at all of them) 612 */ 613 static void 614 zssoft(arg) 615 void *arg; 616 { 617 struct zsc_softc *zsc; 618 int s, unit; 619 620 /* This is not the only ISR on this IPL. */ 621 if (zssoftpending == 0) 622 return; 623 624 /* 625 * The soft intr. bit will be set by zshard only if 626 * the variable zssoftpending is zero. The order of 627 * these next two statements prevents our clearing 628 * the soft intr bit just after zshard has set it. 629 */ 630 /* ienab_bic(IE_ZSSOFT); */ 631 zssoftpending = 0; 632 633 /* Make sure we call the tty layer at spltty. */ 634 s = spltty(); 635 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 636 zsc = zs_cd.cd_devs[unit]; 637 if (zsc == NULL) 638 continue; 639 (void)zsc_intr_soft(zsc); 640 } 641 splx(s); 642 } 643 644 645 /* 646 * Compute the current baud rate given a ZS channel. 647 */ 648 static int 649 zs_get_speed(cs) 650 struct zs_chanstate *cs; 651 { 652 int tconst; 653 654 tconst = zs_read_reg(cs, 12); 655 tconst |= zs_read_reg(cs, 13) << 8; 656 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 657 } 658 659 /* 660 * MD functions for setting the baud rate and control modes. 661 */ 662 int 663 zs_set_speed(cs, bps) 664 struct zs_chanstate *cs; 665 int bps; /* bits per second */ 666 { 667 int tconst, real_bps; 668 669 if (bps == 0) 670 return (0); 671 672 #ifdef DIAGNOSTIC 673 if (cs->cs_brg_clk == 0) 674 panic("zs_set_speed"); 675 #endif 676 677 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 678 if (tconst < 0) 679 return (EINVAL); 680 681 /* Convert back to make sure we can do it. */ 682 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 683 684 /* XXX - Allow some tolerance here? */ 685 if (real_bps != bps) 686 return (EINVAL); 687 688 cs->cs_preg[12] = tconst; 689 cs->cs_preg[13] = tconst >> 8; 690 691 /* Caller will stuff the pending registers. */ 692 return (0); 693 } 694 695 int 696 zs_set_modes(cs, cflag) 697 struct zs_chanstate *cs; 698 int cflag; /* bits per second */ 699 { 700 int s; 701 702 /* 703 * Output hardware flow control on the chip is horrendous: 704 * if carrier detect drops, the receiver is disabled, and if 705 * CTS drops, the transmitter is stoped IN MID CHARACTER! 706 * Therefore, NEVER set the HFC bit, and instead use the 707 * status interrupt to detect CTS changes. 708 */ 709 s = splzs(); 710 cs->cs_rr0_pps = 0; 711 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 712 cs->cs_rr0_dcd = 0; 713 if ((cflag & MDMBUF) == 0) 714 cs->cs_rr0_pps = ZSRR0_DCD; 715 } else 716 cs->cs_rr0_dcd = ZSRR0_DCD; 717 if ((cflag & CRTSCTS) != 0) { 718 cs->cs_wr5_dtr = ZSWR5_DTR; 719 cs->cs_wr5_rts = ZSWR5_RTS; 720 cs->cs_rr0_cts = ZSRR0_CTS; 721 } else if ((cflag & CDTRCTS) != 0) { 722 cs->cs_wr5_dtr = 0; 723 cs->cs_wr5_rts = ZSWR5_DTR; 724 cs->cs_rr0_cts = ZSRR0_CTS; 725 } else if ((cflag & MDMBUF) != 0) { 726 cs->cs_wr5_dtr = 0; 727 cs->cs_wr5_rts = ZSWR5_DTR; 728 cs->cs_rr0_cts = ZSRR0_DCD; 729 } else { 730 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 731 cs->cs_wr5_rts = 0; 732 cs->cs_rr0_cts = 0; 733 } 734 splx(s); 735 736 /* Caller will stuff the pending registers. */ 737 return (0); 738 } 739 740 741 /* 742 * Read or write the chip with suitable delays. 743 */ 744 745 u_char 746 zs_read_reg(cs, reg) 747 struct zs_chanstate *cs; 748 u_char reg; 749 { 750 u_char val; 751 752 *cs->cs_reg_csr = reg; 753 ZS_DELAY(); 754 val = *cs->cs_reg_csr; 755 ZS_DELAY(); 756 return (val); 757 } 758 759 void 760 zs_write_reg(cs, reg, val) 761 struct zs_chanstate *cs; 762 u_char reg, val; 763 { 764 *cs->cs_reg_csr = reg; 765 ZS_DELAY(); 766 *cs->cs_reg_csr = val; 767 ZS_DELAY(); 768 } 769 770 u_char 771 zs_read_csr(cs) 772 struct zs_chanstate *cs; 773 { 774 u_char val; 775 776 val = *cs->cs_reg_csr; 777 ZS_DELAY(); 778 return (val); 779 } 780 781 void 782 zs_write_csr(cs, val) 783 struct zs_chanstate *cs; 784 u_char val; 785 { 786 *cs->cs_reg_csr = val; 787 ZS_DELAY(); 788 } 789 790 u_char 791 zs_read_data(cs) 792 struct zs_chanstate *cs; 793 { 794 u_char val; 795 796 val = *cs->cs_reg_data; 797 ZS_DELAY(); 798 return (val); 799 } 800 801 void zs_write_data(cs, val) 802 struct zs_chanstate *cs; 803 u_char val; 804 { 805 *cs->cs_reg_data = val; 806 ZS_DELAY(); 807 } 808 809 /**************************************************************** 810 * Console support functions (Sun specific!) 811 * Note: this code is allowed to know about the layout of 812 * the chip registers, and uses that to keep things simple. 813 * XXX - I think I like the mvme167 code better. -gwr 814 ****************************************************************/ 815 816 /* 817 * Handle user request to enter kernel debugger. 818 */ 819 void 820 zs_abort(cs) 821 struct zs_chanstate *cs; 822 { 823 struct zschan *zc = zs_conschan_get; 824 int rr0; 825 826 /* Wait for end of break to avoid PROM abort. */ 827 /* XXX - Limit the wait? */ 828 do { 829 rr0 = zc->zc_csr; 830 ZS_DELAY(); 831 } while (rr0 & ZSRR0_BREAK); 832 833 #if defined(KGDB) 834 zskgdb(cs); 835 #elif defined(DDB) 836 Debugger(); 837 #else 838 printf("stopping on keyboard abort\n"); 839 callrom(); 840 #endif 841 } 842 843 int zs_getc __P((void *arg)); 844 void zs_putc __P((void *arg, int c)); 845 846 /* 847 * Polled input char. 848 */ 849 int 850 zs_getc(arg) 851 void *arg; 852 { 853 struct zschan *zc = arg; 854 int s, c, rr0; 855 u_int omid; 856 857 /* Temporarily direct interrupts at ourselves */ 858 s = splhigh(); 859 omid = setitr(cpuinfo.mid); 860 861 /* Wait for a character to arrive. */ 862 do { 863 rr0 = zc->zc_csr; 864 ZS_DELAY(); 865 } while ((rr0 & ZSRR0_RX_READY) == 0); 866 867 c = zc->zc_data; 868 ZS_DELAY(); 869 setitr(omid); 870 splx(s); 871 872 /* 873 * This is used by the kd driver to read scan codes, 874 * so don't translate '\r' ==> '\n' here... 875 */ 876 return (c); 877 } 878 879 /* 880 * Polled output char. 881 */ 882 void 883 zs_putc(arg, c) 884 void *arg; 885 int c; 886 { 887 struct zschan *zc = arg; 888 int s, rr0; 889 u_int omid; 890 891 /* Temporarily direct interrupts at ourselves */ 892 s = splhigh(); 893 omid = setitr(cpuinfo.mid); 894 895 /* Wait for transmitter to become ready. */ 896 do { 897 rr0 = zc->zc_csr; 898 ZS_DELAY(); 899 } while ((rr0 & ZSRR0_TX_READY) == 0); 900 901 /* 902 * Send the next character. 903 * Now you'd think that this could be followed by a ZS_DELAY() 904 * just like all the other chip accesses, but it turns out that 905 * the `transmit-ready' interrupt isn't de-asserted until 906 * some period of time after the register write completes 907 * (more than a couple instructions). So to avoid stray 908 * interrupts we put in the 2us delay regardless of cpu model. 909 */ 910 zc->zc_data = c; 911 delay(2); 912 913 setitr(omid); 914 splx(s); 915 } 916 917 /*****************************************************************/ 918 /* 919 * Polled console input putchar. 920 */ 921 int 922 zscngetc(dev) 923 dev_t dev; 924 { 925 return (zs_getc(zs_conschan_get)); 926 } 927 928 /* 929 * Polled console output putchar. 930 */ 931 void 932 zscnputc(dev, c) 933 dev_t dev; 934 int c; 935 { 936 zs_putc(zs_conschan_put, c); 937 } 938 939 void 940 zscnpollc(dev, on) 941 dev_t dev; 942 int on; 943 { 944 /* No action needed */ 945 } 946 947 int 948 zs_console_flags(promunit, node, channel) 949 int promunit; 950 int node; 951 int channel; 952 { 953 int cookie, flags = 0; 954 955 switch (prom_version()) { 956 case PROM_OLDMON: 957 case PROM_OBP_V0: 958 /* 959 * Use `promunit' and `channel' to derive the PROM 960 * stdio handles that correspond to this device. 961 */ 962 if (promunit == 0) 963 cookie = PROMDEV_TTYA + channel; 964 else if (promunit == 1 && channel == 0) 965 cookie = PROMDEV_KBD; 966 else 967 cookie = -1; 968 969 if (cookie == prom_stdin()) 970 flags |= ZS_HWFLAG_CONSOLE_INPUT; 971 972 /* 973 * Prevent the keyboard from matching the output device 974 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 975 */ 976 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 977 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 978 979 break; 980 981 case PROM_OBP_V2: 982 case PROM_OBP_V3: 983 case PROM_OPENFIRM: 984 985 /* 986 * Match the nodes and device arguments prepared by 987 * consinit() against our device node and channel. 988 * (The device argument is the part of the OBP path 989 * following the colon, as in `/obio/zs@0,100000:a') 990 */ 991 992 /* Default to channel 0 if there are no explicit prom args */ 993 cookie = 0; 994 995 if (node == prom_stdin_node) { 996 if (prom_stdin_args[0] != '\0') 997 /* Translate (a,b) -> (0,1) */ 998 cookie = prom_stdin_args[0] - 'a'; 999 1000 if (channel == cookie) 1001 flags |= ZS_HWFLAG_CONSOLE_INPUT; 1002 } 1003 1004 if (node == prom_stdout_node) { 1005 if (prom_stdout_args[0] != '\0') 1006 /* Translate (a,b) -> (0,1) */ 1007 cookie = prom_stdout_args[0] - 'a'; 1008 1009 if (channel == cookie) 1010 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1011 } 1012 1013 break; 1014 1015 default: 1016 break; 1017 } 1018 1019 return (flags); 1020 } 1021 1022 /* 1023 * Power management hooks for zsopen() and zsclose(). 1024 * We use them to power on/off the ports, if necessary. 1025 */ 1026 int 1027 zs_enable(cs) 1028 struct zs_chanstate *cs; 1029 { 1030 auxiotwoserialendis (ZS_ENABLE); 1031 cs->enabled = 1; 1032 return(0); 1033 } 1034 1035 void 1036 zs_disable(cs) 1037 struct zs_chanstate *cs; 1038 { 1039 auxiotwoserialendis (ZS_DISABLE); 1040 cs->enabled = 0; 1041 } 1042