1 /* $NetBSD: zs.c,v 1.104 2006/02/26 05:36:15 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.104 2006/02/26 05:36:15 thorpej Exp $"); 49 50 #include "opt_ddb.h" 51 #include "opt_kgdb.h" 52 #include "opt_sparc_arch.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/conf.h> 57 #include <sys/device.h> 58 #include <sys/file.h> 59 #include <sys/ioctl.h> 60 #include <sys/kernel.h> 61 #include <sys/proc.h> 62 #include <sys/tty.h> 63 #include <sys/time.h> 64 #include <sys/syslog.h> 65 66 #include <machine/bsd_openprom.h> 67 #include <machine/autoconf.h> 68 #include <machine/intr.h> 69 #include <machine/eeprom.h> 70 #include <machine/psl.h> 71 #include <machine/z8530var.h> 72 73 #include <dev/cons.h> 74 #include <dev/ic/z8530reg.h> 75 76 #include <sparc/sparc/vaddrs.h> 77 #include <sparc/sparc/auxreg.h> 78 #include <sparc/sparc/auxiotwo.h> 79 #include <sparc/dev/cons.h> 80 #include <dev/sun/kbd_ms_ttyvar.h> 81 82 #include "kbd.h" 83 #include "ms.h" 84 85 /* 86 * Some warts needed by z8530tty.c - 87 * The default parity REALLY needs to be the same as the PROM uses, 88 * or you can not see messages done with printf during boot-up... 89 */ 90 int zs_def_cflag = (CREAD | CS8 | HUPCL); 91 92 /* 93 * The Sun provides a 4.9152 MHz clock to the ZS chips. 94 */ 95 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 96 97 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 98 99 /* The layout of this is hardware-dependent (padding, order). */ 100 struct zschan { 101 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 102 u_char zc_xxx0; 103 volatile u_char zc_data; /* data */ 104 u_char zc_xxx1; 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 /* ZS channel used as the console device (if any) */ 113 void *zs_conschan_get, *zs_conschan_put; 114 115 static u_char zs_init_reg[16] = { 116 0, /* 0: CMD (reset, etc.) */ 117 0, /* 1: No interrupts yet. */ 118 0, /* 2: IVECT */ 119 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 120 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 121 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 122 0, /* 6: TXSYNC/SYNCLO */ 123 0, /* 7: RXSYNC/SYNCHI */ 124 0, /* 8: alias for data port */ 125 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 126 0, /*10: Misc. TX/RX control bits */ 127 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 128 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 129 0, /*13: BAUDHI (default=9600) */ 130 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 131 ZSWR15_BREAK_IE, 132 }; 133 134 /* Console ops */ 135 static int zscngetc(dev_t); 136 static void zscnputc(dev_t, int); 137 static void zscnpollc(dev_t, int); 138 139 struct consdev zs_consdev = { 140 NULL, 141 NULL, 142 zscngetc, 143 zscnputc, 144 zscnpollc, 145 NULL, 146 }; 147 148 149 /**************************************************************** 150 * Autoconfig 151 ****************************************************************/ 152 153 /* Definition of the driver for autoconfig. */ 154 static int zs_match_mainbus(struct device *, struct cfdata *, void *); 155 static int zs_match_obio(struct device *, struct cfdata *, void *); 156 static void zs_attach_mainbus(struct device *, struct device *, void *); 157 static void zs_attach_obio(struct device *, struct device *, void *); 158 159 #if defined(SUN4D) 160 #include <sparc/dev/bootbusvar.h> 161 162 static int zs_match_bootbus(struct device *, struct cfdata *, void *); 163 static void zs_attach_bootbus(struct device *, struct device *, void *); 164 165 CFATTACH_DECL(zs_bootbus, sizeof(struct zsc_softc), 166 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 167 #endif /* SUN4D */ 168 169 static void zs_attach(struct zsc_softc *, struct zsdevice *, int); 170 static int zs_print(void *, const char *name); 171 172 CFATTACH_DECL(zs_mainbus, sizeof(struct zsc_softc), 173 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 174 175 CFATTACH_DECL(zs_obio, sizeof(struct zsc_softc), 176 zs_match_obio, zs_attach_obio, NULL, NULL); 177 178 extern struct cfdriver zs_cd; 179 180 /* softintr(9) cookie, shared by all instances of this driver */ 181 static void *zs_sicookie; 182 183 /* Interrupt handlers. */ 184 static int zshard(void *); 185 static void zssoft(void *); 186 187 static int zs_get_speed(struct zs_chanstate *); 188 189 /* Console device support */ 190 static int zs_console_flags(int, int, int); 191 192 /* Power management hooks */ 193 int zs_enable(struct zs_chanstate *); 194 void zs_disable(struct zs_chanstate *); 195 196 197 /* XXX from dev/ic/z8530tty.c */ 198 extern struct tty *zstty_get_tty_from_dev(struct device *); 199 200 /* 201 * Is the zs chip present? 202 */ 203 static int 204 zs_match_mainbus(struct device *parent, struct cfdata *cf, void *aux) 205 { 206 struct mainbus_attach_args *ma = aux; 207 208 if (strcmp(cf->cf_name, ma->ma_name) != 0) 209 return (0); 210 211 return (1); 212 } 213 214 static int 215 zs_match_obio(struct device *parent, struct cfdata *cf, void *aux) 216 { 217 union obio_attach_args *uoba = aux; 218 struct obio4_attach_args *oba; 219 220 if (uoba->uoba_isobio4 == 0) { 221 struct sbus_attach_args *sa = &uoba->uoba_sbus; 222 223 if (strcmp(cf->cf_name, sa->sa_name) != 0) 224 return (0); 225 226 return (1); 227 } 228 229 oba = &uoba->uoba_oba4; 230 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 231 1, 0, 0, NULL, NULL)); 232 } 233 234 #if defined(SUN4D) 235 static int 236 zs_match_bootbus(struct device *parent, struct cfdata *cf, void *aux) 237 { 238 struct bootbus_attach_args *baa = aux; 239 240 return (strcmp(cf->cf_name, baa->ba_name) == 0); 241 } 242 #endif /* SUN4D */ 243 244 static void 245 zs_attach_mainbus(struct device *parent, struct device *self, void *aux) 246 { 247 struct zsc_softc *zsc = (void *) self; 248 struct mainbus_attach_args *ma = aux; 249 250 zsc->zsc_bustag = ma->ma_bustag; 251 zsc->zsc_dmatag = ma->ma_dmatag; 252 zsc->zsc_promunit = prom_getpropint(ma->ma_node, "slave", -2); 253 zsc->zsc_node = ma->ma_node; 254 255 /* 256 * For machines with zs on mainbus (all sun4c models), we expect 257 * the device registers to be mapped by the PROM. 258 */ 259 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 260 } 261 262 static void 263 zs_attach_obio(struct device *parent, struct device *self, void *aux) 264 { 265 struct zsc_softc *zsc = (void *) self; 266 union obio_attach_args *uoba = aux; 267 268 if (uoba->uoba_isobio4 == 0) { 269 struct sbus_attach_args *sa = &uoba->uoba_sbus; 270 void *va; 271 struct zs_chanstate *cs; 272 int channel; 273 274 if (sa->sa_nintr == 0) { 275 printf(" no interrupt lines\n"); 276 return; 277 } 278 279 /* 280 * Some sun4m models (Javastations) may not map the zs device. 281 */ 282 if (sa->sa_npromvaddrs > 0) 283 va = (void *)sa->sa_promvaddr; 284 else { 285 bus_space_handle_t bh; 286 287 if (sbus_bus_map(sa->sa_bustag, 288 sa->sa_slot, 289 sa->sa_offset, 290 sa->sa_size, 291 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 292 printf(" cannot map zs registers\n"); 293 return; 294 } 295 va = (void *)bh; 296 } 297 298 /* 299 * Check if power state can be set, e.g. Tadpole 3GX 300 */ 301 if (prom_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 302 { 303 printf (" powered via auxio2"); 304 for (channel = 0; channel < 2; channel++) { 305 cs = &zsc->zsc_cs_store[channel]; 306 cs->enable = zs_enable; 307 cs->disable = zs_disable; 308 } 309 } 310 311 zsc->zsc_bustag = sa->sa_bustag; 312 zsc->zsc_dmatag = sa->sa_dmatag; 313 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 314 zsc->zsc_node = sa->sa_node; 315 zs_attach(zsc, va, sa->sa_pri); 316 } else { 317 struct obio4_attach_args *oba = &uoba->uoba_oba4; 318 bus_space_handle_t bh; 319 bus_addr_t paddr = oba->oba_paddr; 320 321 /* 322 * As for zs on mainbus, we require a PROM mapping. 323 */ 324 if (bus_space_map(oba->oba_bustag, 325 paddr, 326 sizeof(struct zsdevice), 327 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 328 &bh) != 0) { 329 printf(" cannot map zs registers\n"); 330 return; 331 } 332 zsc->zsc_bustag = oba->oba_bustag; 333 zsc->zsc_dmatag = oba->oba_dmatag; 334 /* 335 * Find prom unit by physical address 336 * We're just comparing the address (not the iospace) here 337 */ 338 paddr = BUS_ADDR_PADDR(paddr); 339 if (cpuinfo.cpu_type == CPUTYP_4_100) 340 /* 341 * On the sun4/100, the top-most 4 bits are zero 342 * on obio addresses; force them to 1's for the 343 * sake of the comparison here. 344 */ 345 paddr |= 0xf0000000; 346 zsc->zsc_promunit = 347 (paddr == 0xf1000000) ? 0 : 348 (paddr == 0xf0000000) ? 1 : 349 (paddr == 0xe0000000) ? 2 : -2; 350 351 zs_attach(zsc, (void *)bh, oba->oba_pri); 352 } 353 } 354 355 #if defined(SUN4D) 356 static void 357 zs_attach_bootbus(struct device *parent, struct device *self, void *aux) 358 { 359 struct zsc_softc *zsc = (void *) self; 360 struct bootbus_attach_args *baa = aux; 361 void *va; 362 363 if (baa->ba_nintr == 0) { 364 printf(": no interrupt lines\n"); 365 return; 366 } 367 368 if (baa->ba_npromvaddrs > 0) 369 va = (void *) baa->ba_promvaddrs; 370 else { 371 bus_space_handle_t bh; 372 373 if (bus_space_map(baa->ba_bustag, 374 BUS_ADDR(baa->ba_slot, baa->ba_offset), 375 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 376 printf(": cannot map zs registers\n"); 377 return; 378 } 379 va = (void *) bh; 380 } 381 382 zsc->zsc_bustag = baa->ba_bustag; 383 zsc->zsc_promunit = prom_getpropint(baa->ba_node, "slave", -2); 384 zsc->zsc_node = baa->ba_node; 385 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 386 } 387 #endif /* SUN4D */ 388 389 /* 390 * Attach a found zs. 391 * 392 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 393 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 394 */ 395 static void 396 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 397 { 398 struct zsc_attach_args zsc_args; 399 struct zs_chanstate *cs; 400 int s, channel; 401 static int didintr, prevpri; 402 403 if (zsd == NULL) { 404 printf("configuration incomplete\n"); 405 return; 406 } 407 408 if (!didintr) { 409 zs_sicookie = softintr_establish(IPL_SOFTSERIAL, zssoft, NULL); 410 if (zs_sicookie == NULL) { 411 printf("\n%s: cannot establish soft int handler\n", 412 zsc->zsc_dev.dv_xname); 413 return; 414 } 415 } 416 printf(" softpri %d\n", IPL_SOFTSERIAL); 417 418 /* 419 * Initialize software state for each channel. 420 */ 421 for (channel = 0; channel < 2; channel++) { 422 struct zschan *zc; 423 struct device *child; 424 425 zsc_args.channel = channel; 426 cs = &zsc->zsc_cs_store[channel]; 427 zsc->zsc_cs[channel] = cs; 428 429 simple_lock_init(&cs->cs_lock); 430 cs->cs_channel = channel; 431 cs->cs_private = NULL; 432 cs->cs_ops = &zsops_null; 433 cs->cs_brg_clk = PCLK / 16; 434 435 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 436 437 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 438 zsc->zsc_node, 439 channel); 440 441 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 442 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 443 zsc_args.consdev = &zs_consdev; 444 } 445 446 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 447 zs_conschan_get = zc; 448 } 449 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 450 zs_conschan_put = zc; 451 } 452 /* Childs need to set cn_dev, etc */ 453 454 cs->cs_reg_csr = &zc->zc_csr; 455 cs->cs_reg_data = &zc->zc_data; 456 457 bcopy(zs_init_reg, cs->cs_creg, 16); 458 bcopy(zs_init_reg, cs->cs_preg, 16); 459 460 /* XXX: Consult PROM properties for this?! */ 461 cs->cs_defspeed = zs_get_speed(cs); 462 cs->cs_defcflag = zs_def_cflag; 463 464 /* Make these correspond to cs_defcflag (-crtscts) */ 465 cs->cs_rr0_dcd = ZSRR0_DCD; 466 cs->cs_rr0_cts = 0; 467 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 468 cs->cs_wr5_rts = 0; 469 470 /* 471 * Clear the master interrupt enable. 472 * The INTENA is common to both channels, 473 * so just do it on the A channel. 474 */ 475 if (channel == 0) { 476 zs_write_reg(cs, 9, 0); 477 } 478 479 /* 480 * Look for a child driver for this channel. 481 * The child attach will setup the hardware. 482 */ 483 484 child = config_found(&zsc->zsc_dev, &zsc_args, zs_print); 485 if (child == NULL) { 486 /* No sub-driver. Just reset it. */ 487 u_char reset = (channel == 0) ? 488 ZSWR9_A_RESET : ZSWR9_B_RESET; 489 s = splzs(); 490 zs_write_reg(cs, 9, reset); 491 splx(s); 492 } 493 #if (NKBD > 0) || (NMS > 0) 494 /* 495 * If this was a zstty it has a keyboard 496 * property on it we need to attach the 497 * sunkbd and sunms line disciplines. 498 */ 499 if ((child != NULL) 500 && (device_is_a(child, "zstty")) 501 && (prom_getproplen(zsc->zsc_node, "keyboard") == 0)) 502 { 503 struct kbd_ms_tty_attach_args kma; 504 struct tty *tp = zstty_get_tty_from_dev(child); 505 kma.kmta_tp = tp; 506 kma.kmta_dev = tp->t_dev; 507 kma.kmta_consdev = zsc_args.consdev; 508 509 /* Attach 'em if we got 'em. */ 510 #if (NKBD > 0) 511 if (channel == 0) { 512 kma.kmta_name = "keyboard"; 513 config_found(child, &kma, NULL); 514 } 515 #endif 516 #if (NMS > 0) 517 if (channel == 1) { 518 kma.kmta_name = "mouse"; 519 config_found(child, &kma, NULL); 520 } 521 #endif 522 } 523 #endif 524 } 525 526 /* 527 * Now safe to install interrupt handlers. Note the arguments 528 * to the interrupt handlers aren't used. Note, we only do this 529 * once since both SCCs interrupt at the same level and vector. 530 */ 531 if (!didintr) { 532 didintr = 1; 533 prevpri = pri; 534 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 535 zshard, NULL); 536 } else if (pri != prevpri) 537 panic("broken zs interrupt scheme"); 538 539 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 540 zsc->zsc_dev.dv_xname, "intr"); 541 542 /* 543 * Set the master interrupt enable and interrupt vector. 544 * (common to both channels, do it on A) 545 */ 546 cs = zsc->zsc_cs[0]; 547 s = splhigh(); 548 /* interrupt vector */ 549 zs_write_reg(cs, 2, zs_init_reg[2]); 550 /* master interrupt control (enable) */ 551 zs_write_reg(cs, 9, zs_init_reg[9]); 552 splx(s); 553 554 #if 0 555 /* 556 * XXX: L1A hack - We would like to be able to break into 557 * the debugger during the rest of autoconfiguration, so 558 * lower interrupts just enough to let zs interrupts in. 559 * This is done after both zs devices are attached. 560 */ 561 if (zsc->zsc_promunit == 1) { 562 printf("zs1: enabling zs interrupts\n"); 563 (void)splfd(); /* XXX: splzs - 1 */ 564 } 565 #endif 566 567 } 568 569 static int 570 zs_print(void *aux, const char *name) 571 { 572 struct zsc_attach_args *args = aux; 573 574 if (name != NULL) 575 aprint_normal("%s: ", name); 576 577 if (args->channel != -1) 578 aprint_normal(" channel %d", args->channel); 579 580 return (UNCONF); 581 } 582 583 static volatile int zssoftpending; 584 585 /* 586 * Our ZS chips all share a common, autovectored interrupt, 587 * so we have to look at all of them on each interrupt. 588 */ 589 static int 590 zshard(void *arg) 591 { 592 struct zsc_softc *zsc; 593 int unit, rr3, rval, softreq; 594 595 rval = softreq = 0; 596 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 597 struct zs_chanstate *cs; 598 599 zsc = zs_cd.cd_devs[unit]; 600 if (zsc == NULL) 601 continue; 602 rr3 = zsc_intr_hard(zsc); 603 /* Count up the interrupts. */ 604 if (rr3) { 605 rval |= rr3; 606 zsc->zsc_intrcnt.ev_count++; 607 } 608 if ((cs = zsc->zsc_cs[0]) != NULL) 609 softreq |= cs->cs_softreq; 610 if ((cs = zsc->zsc_cs[1]) != NULL) 611 softreq |= cs->cs_softreq; 612 } 613 614 /* We are at splzs here, so no need to lock. */ 615 if (softreq && (zssoftpending == 0)) { 616 zssoftpending = 1; 617 softintr_schedule(zs_sicookie); 618 } 619 return (rval); 620 } 621 622 /* 623 * Similar scheme as for zshard (look at all of them) 624 */ 625 static void 626 zssoft(void *arg) 627 { 628 struct zsc_softc *zsc; 629 int s, unit; 630 631 /* This is not the only ISR on this IPL. */ 632 if (zssoftpending == 0) 633 return; 634 635 /* 636 * The soft intr. bit will be set by zshard only if 637 * the variable zssoftpending is zero. The order of 638 * these next two statements prevents our clearing 639 * the soft intr bit just after zshard has set it. 640 */ 641 /* ienab_bic(IE_ZSSOFT); */ 642 zssoftpending = 0; 643 644 /* Make sure we call the tty layer at spltty. */ 645 s = spltty(); 646 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 647 zsc = zs_cd.cd_devs[unit]; 648 if (zsc == NULL) 649 continue; 650 (void)zsc_intr_soft(zsc); 651 } 652 splx(s); 653 } 654 655 656 /* 657 * Compute the current baud rate given a ZS channel. 658 */ 659 static int 660 zs_get_speed(struct zs_chanstate *cs) 661 { 662 int tconst; 663 664 tconst = zs_read_reg(cs, 12); 665 tconst |= zs_read_reg(cs, 13) << 8; 666 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 667 } 668 669 /* 670 * MD functions for setting the baud rate and control modes. 671 * bps - in bits per second 672 */ 673 int 674 zs_set_speed(struct zs_chanstate *cs, int bps) 675 { 676 int tconst, real_bps; 677 678 if (bps == 0) 679 return (0); 680 681 #ifdef DIAGNOSTIC 682 if (cs->cs_brg_clk == 0) 683 panic("zs_set_speed"); 684 #endif 685 686 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 687 if (tconst < 0) 688 return (EINVAL); 689 690 /* Convert back to make sure we can do it. */ 691 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 692 693 /* XXX - Allow some tolerance here? */ 694 if (real_bps != bps) 695 return (EINVAL); 696 697 cs->cs_preg[12] = tconst; 698 cs->cs_preg[13] = tconst >> 8; 699 700 /* Caller will stuff the pending registers. */ 701 return (0); 702 } 703 704 int 705 zs_set_modes(struct zs_chanstate *cs, int cflag) 706 { 707 int s; 708 709 /* 710 * Output hardware flow control on the chip is horrendous: 711 * if carrier detect drops, the receiver is disabled, and if 712 * CTS drops, the transmitter is stoped IN MID CHARACTER! 713 * Therefore, NEVER set the HFC bit, and instead use the 714 * status interrupt to detect CTS changes. 715 */ 716 s = splzs(); 717 cs->cs_rr0_pps = 0; 718 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 719 cs->cs_rr0_dcd = 0; 720 if ((cflag & MDMBUF) == 0) 721 cs->cs_rr0_pps = ZSRR0_DCD; 722 } else 723 cs->cs_rr0_dcd = ZSRR0_DCD; 724 if ((cflag & CRTSCTS) != 0) { 725 cs->cs_wr5_dtr = ZSWR5_DTR; 726 cs->cs_wr5_rts = ZSWR5_RTS; 727 cs->cs_rr0_cts = ZSRR0_CTS; 728 } else if ((cflag & CDTRCTS) != 0) { 729 cs->cs_wr5_dtr = 0; 730 cs->cs_wr5_rts = ZSWR5_DTR; 731 cs->cs_rr0_cts = ZSRR0_CTS; 732 } else if ((cflag & MDMBUF) != 0) { 733 cs->cs_wr5_dtr = 0; 734 cs->cs_wr5_rts = ZSWR5_DTR; 735 cs->cs_rr0_cts = ZSRR0_DCD; 736 } else { 737 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 738 cs->cs_wr5_rts = 0; 739 cs->cs_rr0_cts = 0; 740 } 741 splx(s); 742 743 /* Caller will stuff the pending registers. */ 744 return (0); 745 } 746 747 748 /* 749 * Read or write the chip with suitable delays. 750 */ 751 752 u_char 753 zs_read_reg(struct zs_chanstate *cs, u_char reg) 754 { 755 u_char val; 756 757 *cs->cs_reg_csr = reg; 758 ZS_DELAY(); 759 val = *cs->cs_reg_csr; 760 ZS_DELAY(); 761 return (val); 762 } 763 764 void 765 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val) 766 { 767 768 *cs->cs_reg_csr = reg; 769 ZS_DELAY(); 770 *cs->cs_reg_csr = val; 771 ZS_DELAY(); 772 } 773 774 u_char 775 zs_read_csr(struct zs_chanstate *cs) 776 { 777 u_char val; 778 779 val = *cs->cs_reg_csr; 780 ZS_DELAY(); 781 return (val); 782 } 783 784 void 785 zs_write_csr(struct zs_chanstate *cs, u_char val) 786 { 787 788 *cs->cs_reg_csr = val; 789 ZS_DELAY(); 790 } 791 792 u_char 793 zs_read_data(struct zs_chanstate *cs) 794 { 795 u_char val; 796 797 val = *cs->cs_reg_data; 798 ZS_DELAY(); 799 return (val); 800 } 801 802 void 803 zs_write_data(struct zs_chanstate *cs, u_char val) 804 { 805 806 *cs->cs_reg_data = val; 807 ZS_DELAY(); 808 } 809 810 /**************************************************************** 811 * Console support functions (Sun specific!) 812 * Note: this code is allowed to know about the layout of 813 * the chip registers, and uses that to keep things simple. 814 * XXX - I think I like the mvme167 code better. -gwr 815 ****************************************************************/ 816 817 /* 818 * Handle user request to enter kernel debugger. 819 */ 820 void 821 zs_abort(struct zs_chanstate *cs) 822 { 823 struct zschan *zc = zs_conschan_get; 824 int rr0; 825 826 /* Wait for end of break to avoid PROM abort. */ 827 /* XXX - Limit the wait? */ 828 do { 829 rr0 = zc->zc_csr; 830 ZS_DELAY(); 831 } while (rr0 & ZSRR0_BREAK); 832 833 #if defined(KGDB) 834 zskgdb(cs); 835 #elif defined(DDB) 836 Debugger(); 837 #else 838 printf("stopping on keyboard abort\n"); 839 callrom(); 840 #endif 841 } 842 843 int zs_getc(void *); 844 void zs_putc(void *, int); 845 846 /* 847 * Polled input char. 848 */ 849 int 850 zs_getc(void *arg) 851 { 852 struct zschan *zc = arg; 853 int s, c, rr0; 854 u_int omid; 855 856 /* Temporarily direct interrupts at ourselves */ 857 s = splhigh(); 858 omid = setitr(cpuinfo.mid); 859 860 /* Wait for a character to arrive. */ 861 do { 862 rr0 = zc->zc_csr; 863 ZS_DELAY(); 864 } while ((rr0 & ZSRR0_RX_READY) == 0); 865 866 c = zc->zc_data; 867 ZS_DELAY(); 868 setitr(omid); 869 splx(s); 870 871 /* 872 * This is used by the kd driver to read scan codes, 873 * so don't translate '\r' ==> '\n' here... 874 */ 875 return (c); 876 } 877 878 /* 879 * Polled output char. 880 */ 881 void 882 zs_putc(void *arg, int c) 883 { 884 struct zschan *zc = arg; 885 int s, rr0; 886 u_int omid; 887 888 /* Temporarily direct interrupts at ourselves */ 889 s = splhigh(); 890 omid = setitr(cpuinfo.mid); 891 892 /* Wait for transmitter to become ready. */ 893 do { 894 rr0 = zc->zc_csr; 895 ZS_DELAY(); 896 } while ((rr0 & ZSRR0_TX_READY) == 0); 897 898 /* 899 * Send the next character. 900 * Now you'd think that this could be followed by a ZS_DELAY() 901 * just like all the other chip accesses, but it turns out that 902 * the `transmit-ready' interrupt isn't de-asserted until 903 * some period of time after the register write completes 904 * (more than a couple instructions). So to avoid stray 905 * interrupts we put in the 2us delay regardless of CPU model. 906 */ 907 zc->zc_data = c; 908 delay(2); 909 910 setitr(omid); 911 splx(s); 912 } 913 914 /*****************************************************************/ 915 /* 916 * Polled console input putchar. 917 */ 918 static int 919 zscngetc(dev_t dev) 920 { 921 922 return (zs_getc(zs_conschan_get)); 923 } 924 925 /* 926 * Polled console output putchar. 927 */ 928 static void 929 zscnputc(dev_t dev, int c) 930 { 931 932 zs_putc(zs_conschan_put, c); 933 } 934 935 static void 936 zscnpollc(dev_t dev, int on) 937 { 938 939 /* No action needed */ 940 } 941 942 static int 943 zs_console_flags(int promunit, int node, int channel) 944 { 945 int cookie, flags = 0; 946 947 switch (prom_version()) { 948 case PROM_OLDMON: 949 case PROM_OBP_V0: 950 /* 951 * Use `promunit' and `channel' to derive the PROM 952 * stdio handles that correspond to this device. 953 */ 954 if (promunit == 0) 955 cookie = PROMDEV_TTYA + channel; 956 else if (promunit == 1 && channel == 0) 957 cookie = PROMDEV_KBD; 958 else 959 cookie = -1; 960 961 if (cookie == prom_stdin()) 962 flags |= ZS_HWFLAG_CONSOLE_INPUT; 963 964 /* 965 * Prevent the keyboard from matching the output device 966 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 967 */ 968 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 969 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 970 971 break; 972 973 case PROM_OBP_V2: 974 case PROM_OBP_V3: 975 case PROM_OPENFIRM: 976 977 /* 978 * Match the nodes and device arguments prepared by 979 * consinit() against our device node and channel. 980 * (The device argument is the part of the OBP path 981 * following the colon, as in `/obio/zs@0,100000:a') 982 */ 983 984 /* Default to channel 0 if there are no explicit prom args */ 985 cookie = 0; 986 987 if (node == prom_stdin_node) { 988 if (prom_stdin_args[0] != '\0') 989 /* Translate (a,b) -> (0,1) */ 990 cookie = prom_stdin_args[0] - 'a'; 991 992 if (channel == cookie) 993 flags |= ZS_HWFLAG_CONSOLE_INPUT; 994 } 995 996 if (node == prom_stdout_node) { 997 if (prom_stdout_args[0] != '\0') 998 /* Translate (a,b) -> (0,1) */ 999 cookie = prom_stdout_args[0] - 'a'; 1000 1001 if (channel == cookie) 1002 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1003 } 1004 1005 break; 1006 1007 default: 1008 break; 1009 } 1010 1011 return (flags); 1012 } 1013 1014 /* 1015 * Power management hooks for zsopen() and zsclose(). 1016 * We use them to power on/off the ports, if necessary. 1017 */ 1018 int 1019 zs_enable(struct zs_chanstate *cs) 1020 { 1021 1022 auxiotwoserialendis (ZS_ENABLE); 1023 cs->enabled = 1; 1024 return(0); 1025 } 1026 1027 void 1028 zs_disable(struct zs_chanstate *cs) 1029 { 1030 1031 auxiotwoserialendis (ZS_DISABLE); 1032 cs->enabled = 0; 1033 } 1034