1 /* $NetBSD: zs.c,v 1.109 2008/03/29 19:15:35 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.109 2008/03/29 19:15:35 tsutsui Exp $"); 49 50 #include "opt_ddb.h" 51 #include "opt_kgdb.h" 52 #include "opt_sparc_arch.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/conf.h> 57 #include <sys/device.h> 58 #include <sys/file.h> 59 #include <sys/ioctl.h> 60 #include <sys/kernel.h> 61 #include <sys/proc.h> 62 #include <sys/tty.h> 63 #include <sys/time.h> 64 #include <sys/syslog.h> 65 #include <sys/intr.h> 66 67 #include <machine/bsd_openprom.h> 68 #include <machine/autoconf.h> 69 #include <machine/eeprom.h> 70 #include <machine/psl.h> 71 #include <machine/z8530var.h> 72 73 #include <dev/cons.h> 74 #include <dev/ic/z8530reg.h> 75 76 #include <sparc/sparc/vaddrs.h> 77 #include <sparc/sparc/auxreg.h> 78 #include <sparc/sparc/auxiotwo.h> 79 #include <sparc/dev/cons.h> 80 #include <dev/sun/kbd_ms_ttyvar.h> 81 82 #include "kbd.h" 83 #include "ms.h" 84 #include "wskbd.h" 85 86 /* 87 * Some warts needed by z8530tty.c - 88 * The default parity REALLY needs to be the same as the PROM uses, 89 * or you can not see messages done with printf during boot-up... 90 */ 91 int zs_def_cflag = (CREAD | CS8 | HUPCL); 92 93 /* 94 * The Sun provides a 4.9152 MHz clock to the ZS chips. 95 */ 96 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 97 98 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 99 100 /* The layout of this is hardware-dependent (padding, order). */ 101 struct zschan { 102 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 103 uint8_t zc_xxx0; 104 volatile uint8_t zc_data; /* data */ 105 uint8_t zc_xxx1; 106 }; 107 struct zsdevice { 108 /* Yes, they are backwards. */ 109 struct zschan zs_chan_b; 110 struct zschan zs_chan_a; 111 }; 112 113 /* ZS channel used as the console device (if any) */ 114 void *zs_conschan_get, *zs_conschan_put; 115 116 static uint8_t zs_init_reg[16] = { 117 0, /* 0: CMD (reset, etc.) */ 118 0, /* 1: No interrupts yet. */ 119 0, /* 2: IVECT */ 120 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 121 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 122 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 123 0, /* 6: TXSYNC/SYNCLO */ 124 0, /* 7: RXSYNC/SYNCHI */ 125 0, /* 8: alias for data port */ 126 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 127 0, /*10: Misc. TX/RX control bits */ 128 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 129 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 130 0, /*13: BAUDHI (default=9600) */ 131 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 132 ZSWR15_BREAK_IE, 133 }; 134 135 /* Console ops */ 136 static int zscngetc(dev_t); 137 static void zscnputc(dev_t, int); 138 static void zscnpollc(dev_t, int); 139 140 struct consdev zs_consdev = { 141 NULL, 142 NULL, 143 zscngetc, 144 zscnputc, 145 zscnpollc, 146 NULL, 147 }; 148 149 150 /**************************************************************** 151 * Autoconfig 152 ****************************************************************/ 153 154 /* Definition of the driver for autoconfig. */ 155 static int zs_match_mainbus(device_t, cfdata_t, void *); 156 static int zs_match_obio(device_t, cfdata_t, void *); 157 static void zs_attach_mainbus(device_t, device_t, void *); 158 static void zs_attach_obio(device_t, device_t, void *); 159 160 #if defined(SUN4D) 161 #include <sparc/dev/bootbusvar.h> 162 163 static int zs_match_bootbus(device_t, cfdata_t, void *); 164 static void zs_attach_bootbus(device_t, device_t, void *); 165 166 CFATTACH_DECL_NEW(zs_bootbus, sizeof(struct zsc_softc), 167 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 168 #endif /* SUN4D */ 169 170 static void zs_attach(struct zsc_softc *, struct zsdevice *, int); 171 static int zs_print(void *, const char *name); 172 173 CFATTACH_DECL_NEW(zs_mainbus, sizeof(struct zsc_softc), 174 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 175 176 CFATTACH_DECL_NEW(zs_obio, sizeof(struct zsc_softc), 177 zs_match_obio, zs_attach_obio, NULL, NULL); 178 179 extern struct cfdriver zs_cd; 180 181 /* softintr(9) cookie, shared by all instances of this driver */ 182 static void *zs_sicookie; 183 184 /* Interrupt handlers. */ 185 static int zshard(void *); 186 static void zssoft(void *); 187 188 static int zs_get_speed(struct zs_chanstate *); 189 190 /* Console device support */ 191 static int zs_console_flags(int, int, int); 192 193 /* Power management hooks */ 194 int zs_enable(struct zs_chanstate *); 195 void zs_disable(struct zs_chanstate *); 196 197 198 /* XXX from dev/ic/z8530tty.c */ 199 extern struct tty *zstty_get_tty_from_dev(struct device *); 200 201 /* 202 * Is the zs chip present? 203 */ 204 static int 205 zs_match_mainbus(device_t parent, cfdata_t cf, void *aux) 206 { 207 struct mainbus_attach_args *ma = aux; 208 209 if (strcmp(cf->cf_name, ma->ma_name) != 0) 210 return (0); 211 212 return (1); 213 } 214 215 static int 216 zs_match_obio(device_t parent, cfdata_t cf, void *aux) 217 { 218 union obio_attach_args *uoba = aux; 219 struct obio4_attach_args *oba; 220 221 if (uoba->uoba_isobio4 == 0) { 222 struct sbus_attach_args *sa = &uoba->uoba_sbus; 223 224 if (strcmp(cf->cf_name, sa->sa_name) != 0) 225 return (0); 226 227 return (1); 228 } 229 230 oba = &uoba->uoba_oba4; 231 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 232 1, 0, 0, NULL, NULL)); 233 } 234 235 #if defined(SUN4D) 236 static int 237 zs_match_bootbus(device_t parent, cfdata_t cf, void *aux) 238 { 239 struct bootbus_attach_args *baa = aux; 240 241 return (strcmp(cf->cf_name, baa->ba_name) == 0); 242 } 243 #endif /* SUN4D */ 244 245 static void 246 zs_attach_mainbus(device_t parent, device_t self, void *aux) 247 { 248 struct zsc_softc *zsc = device_private(self); 249 struct mainbus_attach_args *ma = aux; 250 251 zsc->zsc_dev = self; 252 zsc->zsc_bustag = ma->ma_bustag; 253 zsc->zsc_dmatag = ma->ma_dmatag; 254 zsc->zsc_promunit = prom_getpropint(ma->ma_node, "slave", -2); 255 zsc->zsc_node = ma->ma_node; 256 257 /* 258 * For machines with zs on mainbus (all sun4c models), we expect 259 * the device registers to be mapped by the PROM. 260 */ 261 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 262 } 263 264 static void 265 zs_attach_obio(device_t parent, device_t self, void *aux) 266 { 267 struct zsc_softc *zsc = device_private(self); 268 union obio_attach_args *uoba = aux; 269 270 zsc->zsc_dev = self; 271 272 if (uoba->uoba_isobio4 == 0) { 273 struct sbus_attach_args *sa = &uoba->uoba_sbus; 274 void *va; 275 struct zs_chanstate *cs; 276 int channel; 277 278 if (sa->sa_nintr == 0) { 279 aprint_error(": no interrupt lines\n"); 280 return; 281 } 282 283 /* 284 * Some sun4m models (Javastations) may not map the zs device. 285 */ 286 if (sa->sa_npromvaddrs > 0) 287 va = (void *)sa->sa_promvaddr; 288 else { 289 bus_space_handle_t bh; 290 291 if (sbus_bus_map(sa->sa_bustag, 292 sa->sa_slot, 293 sa->sa_offset, 294 sa->sa_size, 295 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 296 aprint_error(": cannot map zs registers\n"); 297 return; 298 } 299 va = (void *)bh; 300 } 301 302 /* 303 * Check if power state can be set, e.g. Tadpole 3GX 304 */ 305 if (prom_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) { 306 aprint_normal(": powered via auxio2"); 307 for (channel = 0; channel < 2; channel++) { 308 cs = &zsc->zsc_cs_store[channel]; 309 cs->enable = zs_enable; 310 cs->disable = zs_disable; 311 } 312 } 313 314 zsc->zsc_bustag = sa->sa_bustag; 315 zsc->zsc_dmatag = sa->sa_dmatag; 316 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 317 zsc->zsc_node = sa->sa_node; 318 zs_attach(zsc, va, sa->sa_pri); 319 } else { 320 struct obio4_attach_args *oba = &uoba->uoba_oba4; 321 bus_space_handle_t bh; 322 bus_addr_t paddr = oba->oba_paddr; 323 324 /* 325 * As for zs on mainbus, we require a PROM mapping. 326 */ 327 if (bus_space_map(oba->oba_bustag, 328 paddr, 329 sizeof(struct zsdevice), 330 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 331 &bh) != 0) { 332 aprint_error(": cannot map zs registers\n"); 333 return; 334 } 335 zsc->zsc_bustag = oba->oba_bustag; 336 zsc->zsc_dmatag = oba->oba_dmatag; 337 /* 338 * Find prom unit by physical address 339 * We're just comparing the address (not the iospace) here 340 */ 341 paddr = BUS_ADDR_PADDR(paddr); 342 if (cpuinfo.cpu_type == CPUTYP_4_100) 343 /* 344 * On the sun4/100, the top-most 4 bits are zero 345 * on obio addresses; force them to 1's for the 346 * sake of the comparison here. 347 */ 348 paddr |= 0xf0000000; 349 zsc->zsc_promunit = 350 (paddr == 0xf1000000) ? 0 : 351 (paddr == 0xf0000000) ? 1 : 352 (paddr == 0xe0000000) ? 2 : -2; 353 354 zs_attach(zsc, (void *)bh, oba->oba_pri); 355 } 356 } 357 358 #if defined(SUN4D) 359 static void 360 zs_attach_bootbus(device_t parent, device_t self, void *aux) 361 { 362 struct zsc_softc *zsc = device_private(self); 363 struct bootbus_attach_args *baa = aux; 364 void *va; 365 366 zsc->zsc_dev = self; 367 368 if (baa->ba_nintr == 0) { 369 aprint_error(": no interrupt lines\n"); 370 return; 371 } 372 373 if (baa->ba_npromvaddrs > 0) 374 va = (void *) baa->ba_promvaddrs; 375 else { 376 bus_space_handle_t bh; 377 378 if (bus_space_map(baa->ba_bustag, 379 BUS_ADDR(baa->ba_slot, baa->ba_offset), 380 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 381 aprint_error(": cannot map zs registers\n"); 382 return; 383 } 384 va = (void *) bh; 385 } 386 387 zsc->zsc_bustag = baa->ba_bustag; 388 zsc->zsc_promunit = prom_getpropint(baa->ba_node, "slave", -2); 389 zsc->zsc_node = baa->ba_node; 390 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 391 } 392 #endif /* SUN4D */ 393 394 /* 395 * Attach a found zs. 396 * 397 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 398 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 399 */ 400 static void 401 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 402 { 403 struct zsc_attach_args zsc_args; 404 struct zs_chanstate *cs; 405 int s, channel; 406 static int didintr, prevpri; 407 int ch0_is_cons = 0; 408 409 if (zsd == NULL) { 410 aprint_error(": configuration incomplete\n"); 411 return; 412 } 413 414 if (!didintr) { 415 zs_sicookie = softint_establish(SOFTINT_SERIAL, zssoft, NULL); 416 if (zs_sicookie == NULL) { 417 aprint_error(": cannot establish soft int handler\n"); 418 return; 419 } 420 } 421 aprint_normal(" softpri %d\n", IPL_SOFTSERIAL); 422 423 /* 424 * Initialize software state for each channel. 425 */ 426 for (channel = 0; channel < 2; channel++) { 427 struct zschan *zc; 428 struct device *child; 429 int hwflags; 430 431 zsc_args.channel = channel; 432 cs = &zsc->zsc_cs_store[channel]; 433 zsc->zsc_cs[channel] = cs; 434 435 zs_lock_init(cs); 436 cs->cs_channel = channel; 437 cs->cs_private = NULL; 438 cs->cs_ops = &zsops_null; 439 cs->cs_brg_clk = PCLK / 16; 440 441 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 442 443 hwflags = zs_console_flags(zsc->zsc_promunit, 444 zsc->zsc_node, 445 channel); 446 447 #if NWSKBD == 0 448 /* Not using wscons console, so always set console flags.*/ 449 zsc_args.hwflags = hwflags; 450 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 451 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 452 zsc_args.consdev = &zs_consdev; 453 } 454 #else 455 /* If we are unit 1, then this is the "real" console. 456 * Remember this in order to set up the keyboard and 457 * mouse line disciplines for SUN4 machines below. 458 * Also, don't set the console flags, otherwise we 459 * tell zstty_attach() to attach as console. 460 */ 461 if (zsc->zsc_promunit == 1) { 462 if ((hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0 && 463 !channel) { 464 ch0_is_cons = 1; 465 } 466 } else { 467 zsc_args.hwflags = hwflags; 468 } 469 #endif 470 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 471 zs_conschan_get = zc; 472 } 473 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 474 zs_conschan_put = zc; 475 } 476 /* Childs need to set cn_dev, etc */ 477 478 cs->cs_reg_csr = &zc->zc_csr; 479 cs->cs_reg_data = &zc->zc_data; 480 481 bcopy(zs_init_reg, cs->cs_creg, 16); 482 bcopy(zs_init_reg, cs->cs_preg, 16); 483 484 /* XXX: Consult PROM properties for this?! */ 485 cs->cs_defspeed = zs_get_speed(cs); 486 cs->cs_defcflag = zs_def_cflag; 487 488 /* Make these correspond to cs_defcflag (-crtscts) */ 489 cs->cs_rr0_dcd = ZSRR0_DCD; 490 cs->cs_rr0_cts = 0; 491 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 492 cs->cs_wr5_rts = 0; 493 494 /* 495 * Clear the master interrupt enable. 496 * The INTENA is common to both channels, 497 * so just do it on the A channel. 498 */ 499 if (channel == 0) { 500 zs_write_reg(cs, 9, 0); 501 } 502 503 /* 504 * Look for a child driver for this channel. 505 * The child attach will setup the hardware. 506 */ 507 508 child = config_found(zsc->zsc_dev, &zsc_args, zs_print); 509 if (child == NULL) { 510 /* No sub-driver. Just reset it. */ 511 uint8_t reset = (channel == 0) ? 512 ZSWR9_A_RESET : ZSWR9_B_RESET; 513 s = splzs(); 514 zs_write_reg(cs, 9, reset); 515 splx(s); 516 } 517 #if (NKBD > 0) || (NMS > 0) 518 /* 519 * If this was a zstty it has a keyboard 520 * property on it we need to attach the 521 * sunkbd and sunms line disciplines. 522 * There are no properties on SUN4 machines. 523 * For them, check if we have set the 524 * ch0_is_cons variable above. 525 */ 526 if ((child != NULL) && 527 (device_is_a(child, "zstty")) && ( 528 (CPU_ISSUN4 && ch0_is_cons) || (!CPU_ISSUN4 && 529 (prom_getproplen(zsc->zsc_node, "keyboard") == 0)))) 530 { 531 struct kbd_ms_tty_attach_args kma; 532 struct tty *tp = zstty_get_tty_from_dev(child); 533 kma.kmta_tp = tp; 534 kma.kmta_dev = tp->t_dev; 535 kma.kmta_consdev = zsc_args.consdev; 536 537 /* Attach 'em if we got 'em. */ 538 #if (NKBD > 0) 539 if (channel == 0) { 540 kma.kmta_name = "keyboard"; 541 config_found(child, &kma, NULL); 542 } 543 #endif 544 #if (NMS > 0) 545 if (channel == 1) { 546 kma.kmta_name = "mouse"; 547 config_found(child, &kma, NULL); 548 } 549 #endif 550 } 551 #endif 552 } 553 554 /* 555 * Now safe to install interrupt handlers. Note the arguments 556 * to the interrupt handlers aren't used. Note, we only do this 557 * once since both SCCs interrupt at the same level and vector. 558 */ 559 if (!didintr) { 560 didintr = 1; 561 prevpri = pri; 562 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 563 zshard, NULL); 564 } else if (pri != prevpri) 565 panic("broken zs interrupt scheme"); 566 567 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 568 device_xname(zsc->zsc_dev), "intr"); 569 570 /* 571 * Set the master interrupt enable and interrupt vector. 572 * (common to both channels, do it on A) 573 */ 574 cs = zsc->zsc_cs[0]; 575 s = splhigh(); 576 /* interrupt vector */ 577 zs_write_reg(cs, 2, zs_init_reg[2]); 578 /* master interrupt control (enable) */ 579 zs_write_reg(cs, 9, zs_init_reg[9]); 580 splx(s); 581 582 #if 0 583 /* 584 * XXX: L1A hack - We would like to be able to break into 585 * the debugger during the rest of autoconfiguration, so 586 * lower interrupts just enough to let zs interrupts in. 587 * This is done after both zs devices are attached. 588 */ 589 if (zsc->zsc_promunit == 1) { 590 aprint_debug("zs1: enabling zs interrupts\n"); 591 (void)splfd(); /* XXX: splzs - 1 */ 592 } 593 #endif 594 595 } 596 597 static int 598 zs_print(void *aux, const char *name) 599 { 600 struct zsc_attach_args *args = aux; 601 602 if (name != NULL) 603 aprint_normal("%s: ", name); 604 605 if (args->channel != -1) 606 aprint_normal(" channel %d", args->channel); 607 608 return (UNCONF); 609 } 610 611 static volatile int zssoftpending; 612 613 /* 614 * Our ZS chips all share a common, autovectored interrupt, 615 * so we have to look at all of them on each interrupt. 616 */ 617 static int 618 zshard(void *arg) 619 { 620 struct zsc_softc *zsc; 621 int unit, rr3, rval, softreq; 622 623 rval = softreq = 0; 624 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 625 struct zs_chanstate *cs; 626 627 zsc = device_private(zs_cd.cd_devs[unit]); 628 if (zsc == NULL) 629 continue; 630 rr3 = zsc_intr_hard(zsc); 631 /* Count up the interrupts. */ 632 if (rr3) { 633 rval |= rr3; 634 zsc->zsc_intrcnt.ev_count++; 635 } 636 if ((cs = zsc->zsc_cs[0]) != NULL) 637 softreq |= cs->cs_softreq; 638 if ((cs = zsc->zsc_cs[1]) != NULL) 639 softreq |= cs->cs_softreq; 640 } 641 642 /* We are at splzs here, so no need to lock. */ 643 if (softreq && (zssoftpending == 0)) { 644 zssoftpending = 1; 645 softint_schedule(zs_sicookie); 646 } 647 return (rval); 648 } 649 650 /* 651 * Similar scheme as for zshard (look at all of them) 652 */ 653 static void 654 zssoft(void *arg) 655 { 656 struct zsc_softc *zsc; 657 int s, unit; 658 659 /* This is not the only ISR on this IPL. */ 660 if (zssoftpending == 0) 661 return; 662 663 /* 664 * The soft intr. bit will be set by zshard only if 665 * the variable zssoftpending is zero. The order of 666 * these next two statements prevents our clearing 667 * the soft intr bit just after zshard has set it. 668 */ 669 /* ienab_bic(IE_ZSSOFT); */ 670 zssoftpending = 0; 671 672 /* Make sure we call the tty layer at spltty. */ 673 s = spltty(); 674 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 675 zsc = device_private(zs_cd.cd_devs[unit]); 676 if (zsc == NULL) 677 continue; 678 (void)zsc_intr_soft(zsc); 679 } 680 splx(s); 681 } 682 683 684 /* 685 * Compute the current baud rate given a ZS channel. 686 */ 687 static int 688 zs_get_speed(struct zs_chanstate *cs) 689 { 690 int tconst; 691 692 tconst = zs_read_reg(cs, 12); 693 tconst |= zs_read_reg(cs, 13) << 8; 694 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 695 } 696 697 /* 698 * MD functions for setting the baud rate and control modes. 699 * bps - in bits per second 700 */ 701 int 702 zs_set_speed(struct zs_chanstate *cs, int bps) 703 { 704 int tconst, real_bps; 705 706 if (bps == 0) 707 return (0); 708 709 #ifdef DIAGNOSTIC 710 if (cs->cs_brg_clk == 0) 711 panic("zs_set_speed"); 712 #endif 713 714 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 715 if (tconst < 0) 716 return (EINVAL); 717 718 /* Convert back to make sure we can do it. */ 719 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 720 721 /* XXX - Allow some tolerance here? */ 722 if (real_bps != bps) 723 return (EINVAL); 724 725 cs->cs_preg[12] = tconst; 726 cs->cs_preg[13] = tconst >> 8; 727 728 /* Caller will stuff the pending registers. */ 729 return (0); 730 } 731 732 int 733 zs_set_modes(struct zs_chanstate *cs, int cflag) 734 { 735 int s; 736 737 /* 738 * Output hardware flow control on the chip is horrendous: 739 * if carrier detect drops, the receiver is disabled, and if 740 * CTS drops, the transmitter is stoped IN MID CHARACTER! 741 * Therefore, NEVER set the HFC bit, and instead use the 742 * status interrupt to detect CTS changes. 743 */ 744 s = splzs(); 745 cs->cs_rr0_pps = 0; 746 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 747 cs->cs_rr0_dcd = 0; 748 if ((cflag & MDMBUF) == 0) 749 cs->cs_rr0_pps = ZSRR0_DCD; 750 } else 751 cs->cs_rr0_dcd = ZSRR0_DCD; 752 if ((cflag & CRTSCTS) != 0) { 753 cs->cs_wr5_dtr = ZSWR5_DTR; 754 cs->cs_wr5_rts = ZSWR5_RTS; 755 cs->cs_rr0_cts = ZSRR0_CTS; 756 } else if ((cflag & CDTRCTS) != 0) { 757 cs->cs_wr5_dtr = 0; 758 cs->cs_wr5_rts = ZSWR5_DTR; 759 cs->cs_rr0_cts = ZSRR0_CTS; 760 } else if ((cflag & MDMBUF) != 0) { 761 cs->cs_wr5_dtr = 0; 762 cs->cs_wr5_rts = ZSWR5_DTR; 763 cs->cs_rr0_cts = ZSRR0_DCD; 764 } else { 765 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 766 cs->cs_wr5_rts = 0; 767 cs->cs_rr0_cts = 0; 768 } 769 splx(s); 770 771 /* Caller will stuff the pending registers. */ 772 return (0); 773 } 774 775 776 /* 777 * Read or write the chip with suitable delays. 778 */ 779 780 uint8_t 781 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 782 { 783 uint8_t val; 784 785 *cs->cs_reg_csr = reg; 786 ZS_DELAY(); 787 val = *cs->cs_reg_csr; 788 ZS_DELAY(); 789 return (val); 790 } 791 792 void 793 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 794 { 795 796 *cs->cs_reg_csr = reg; 797 ZS_DELAY(); 798 *cs->cs_reg_csr = val; 799 ZS_DELAY(); 800 } 801 802 uint8_t 803 zs_read_csr(struct zs_chanstate *cs) 804 { 805 uint8_t val; 806 807 val = *cs->cs_reg_csr; 808 ZS_DELAY(); 809 return (val); 810 } 811 812 void 813 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 814 { 815 816 *cs->cs_reg_csr = val; 817 ZS_DELAY(); 818 } 819 820 uint8_t 821 zs_read_data(struct zs_chanstate *cs) 822 { 823 uint8_t val; 824 825 val = *cs->cs_reg_data; 826 ZS_DELAY(); 827 return (val); 828 } 829 830 void 831 zs_write_data(struct zs_chanstate *cs, uint8_t val) 832 { 833 834 *cs->cs_reg_data = val; 835 ZS_DELAY(); 836 } 837 838 /**************************************************************** 839 * Console support functions (Sun specific!) 840 * Note: this code is allowed to know about the layout of 841 * the chip registers, and uses that to keep things simple. 842 * XXX - I think I like the mvme167 code better. -gwr 843 ****************************************************************/ 844 845 /* 846 * Handle user request to enter kernel debugger. 847 */ 848 void 849 zs_abort(struct zs_chanstate *cs) 850 { 851 struct zschan *zc = zs_conschan_get; 852 int rr0; 853 854 /* Wait for end of break to avoid PROM abort. */ 855 /* XXX - Limit the wait? */ 856 do { 857 rr0 = zc->zc_csr; 858 ZS_DELAY(); 859 } while (rr0 & ZSRR0_BREAK); 860 861 #if defined(KGDB) 862 zskgdb(cs); 863 #elif defined(DDB) 864 Debugger(); 865 #else 866 printf("stopping on keyboard abort\n"); 867 callrom(); 868 #endif 869 } 870 871 int zs_getc(void *); 872 void zs_putc(void *, int); 873 874 /* 875 * Polled input char. 876 */ 877 int 878 zs_getc(void *arg) 879 { 880 struct zschan *zc = arg; 881 int s, c, rr0; 882 u_int omid; 883 884 /* Temporarily direct interrupts at ourselves */ 885 s = splhigh(); 886 omid = setitr(cpuinfo.mid); 887 888 /* Wait for a character to arrive. */ 889 do { 890 rr0 = zc->zc_csr; 891 ZS_DELAY(); 892 } while ((rr0 & ZSRR0_RX_READY) == 0); 893 894 c = zc->zc_data; 895 ZS_DELAY(); 896 setitr(omid); 897 splx(s); 898 899 /* 900 * This is used by the kd driver to read scan codes, 901 * so don't translate '\r' ==> '\n' here... 902 */ 903 return (c); 904 } 905 906 /* 907 * Polled output char. 908 */ 909 void 910 zs_putc(void *arg, int c) 911 { 912 struct zschan *zc = arg; 913 int s, rr0; 914 u_int omid; 915 916 /* Temporarily direct interrupts at ourselves */ 917 s = splhigh(); 918 omid = setitr(cpuinfo.mid); 919 920 /* Wait for transmitter to become ready. */ 921 do { 922 rr0 = zc->zc_csr; 923 ZS_DELAY(); 924 } while ((rr0 & ZSRR0_TX_READY) == 0); 925 926 /* 927 * Send the next character. 928 * Now you'd think that this could be followed by a ZS_DELAY() 929 * just like all the other chip accesses, but it turns out that 930 * the `transmit-ready' interrupt isn't de-asserted until 931 * some period of time after the register write completes 932 * (more than a couple instructions). So to avoid stray 933 * interrupts we put in the 2us delay regardless of CPU model. 934 */ 935 zc->zc_data = c; 936 delay(2); 937 938 setitr(omid); 939 splx(s); 940 } 941 942 /*****************************************************************/ 943 /* 944 * Polled console input putchar. 945 */ 946 static int 947 zscngetc(dev_t dev) 948 { 949 950 return (zs_getc(zs_conschan_get)); 951 } 952 953 /* 954 * Polled console output putchar. 955 */ 956 static void 957 zscnputc(dev_t dev, int c) 958 { 959 960 zs_putc(zs_conschan_put, c); 961 } 962 963 static void 964 zscnpollc(dev_t dev, int on) 965 { 966 967 /* No action needed */ 968 } 969 970 static int 971 zs_console_flags(int promunit, int node, int channel) 972 { 973 int cookie, flags = 0; 974 975 switch (prom_version()) { 976 case PROM_OLDMON: 977 case PROM_OBP_V0: 978 /* 979 * Use `promunit' and `channel' to derive the PROM 980 * stdio handles that correspond to this device. 981 */ 982 if (promunit == 0) 983 cookie = PROMDEV_TTYA + channel; 984 else if (promunit == 1 && channel == 0) 985 cookie = PROMDEV_KBD; 986 else 987 cookie = -1; 988 989 if (cookie == prom_stdin()) 990 flags |= ZS_HWFLAG_CONSOLE_INPUT; 991 992 /* 993 * Prevent the keyboard from matching the output device 994 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 995 */ 996 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 997 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 998 999 break; 1000 1001 case PROM_OBP_V2: 1002 case PROM_OBP_V3: 1003 case PROM_OPENFIRM: 1004 1005 /* 1006 * Match the nodes and device arguments prepared by 1007 * consinit() against our device node and channel. 1008 * (The device argument is the part of the OBP path 1009 * following the colon, as in `/obio/zs@0,100000:a') 1010 */ 1011 1012 /* Default to channel 0 if there are no explicit prom args */ 1013 cookie = 0; 1014 1015 if (node == prom_stdin_node) { 1016 if (prom_stdin_args[0] != '\0') 1017 /* Translate (a,b) -> (0,1) */ 1018 cookie = prom_stdin_args[0] - 'a'; 1019 1020 if (channel == cookie) 1021 flags |= ZS_HWFLAG_CONSOLE_INPUT; 1022 } 1023 1024 if (node == prom_stdout_node) { 1025 if (prom_stdout_args[0] != '\0') 1026 /* Translate (a,b) -> (0,1) */ 1027 cookie = prom_stdout_args[0] - 'a'; 1028 1029 if (channel == cookie) 1030 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1031 } 1032 1033 break; 1034 1035 default: 1036 break; 1037 } 1038 1039 return (flags); 1040 } 1041 1042 /* 1043 * Power management hooks for zsopen() and zsclose(). 1044 * We use them to power on/off the ports, if necessary. 1045 */ 1046 int 1047 zs_enable(struct zs_chanstate *cs) 1048 { 1049 1050 auxiotwoserialendis (ZS_ENABLE); 1051 cs->enabled = 1; 1052 return(0); 1053 } 1054 1055 void 1056 zs_disable(struct zs_chanstate *cs) 1057 { 1058 1059 auxiotwoserialendis (ZS_DISABLE); 1060 cs->enabled = 0; 1061 } 1062