1 /* $NetBSD: zs.c,v 1.117 2010/01/17 16:23:43 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.117 2010/01/17 16:23:43 tsutsui Exp $"); 42 43 #include "opt_ddb.h" 44 #include "opt_kgdb.h" 45 #include "opt_sparc_arch.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/conf.h> 50 #include <sys/device.h> 51 #include <sys/file.h> 52 #include <sys/ioctl.h> 53 #include <sys/kernel.h> 54 #include <sys/proc.h> 55 #include <sys/tty.h> 56 #include <sys/time.h> 57 #include <sys/syslog.h> 58 #include <sys/intr.h> 59 60 #include <machine/bsd_openprom.h> 61 #include <machine/autoconf.h> 62 #include <machine/eeprom.h> 63 #include <machine/psl.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include <sparc/sparc/vaddrs.h> 70 #include <sparc/sparc/auxreg.h> 71 #include <sparc/sparc/auxiotwo.h> 72 #include <sparc/dev/cons.h> 73 #include <dev/sun/kbd_ms_ttyvar.h> 74 75 #include "kbd.h" 76 #include "ms.h" 77 #include "wskbd.h" 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 86 /* 87 * The Sun provides a 4.9152 MHz clock to the ZS chips. 88 */ 89 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 90 91 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 92 93 /* The layout of this is hardware-dependent (padding, order). */ 94 struct zschan { 95 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 96 uint8_t zc_xxx0; 97 volatile uint8_t zc_data; /* data */ 98 uint8_t zc_xxx1; 99 }; 100 struct zsdevice { 101 /* Yes, they are backwards. */ 102 struct zschan zs_chan_b; 103 struct zschan zs_chan_a; 104 }; 105 106 /* ZS channel used as the console device (if any) */ 107 void *zs_conschan_get, *zs_conschan_put; 108 109 static uint8_t zs_init_reg[16] = { 110 0, /* 0: CMD (reset, etc.) */ 111 0, /* 1: No interrupts yet. */ 112 0, /* 2: IVECT */ 113 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 114 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 115 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 116 0, /* 6: TXSYNC/SYNCLO */ 117 0, /* 7: RXSYNC/SYNCHI */ 118 0, /* 8: alias for data port */ 119 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 120 0, /*10: Misc. TX/RX control bits */ 121 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 122 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 123 0, /*13: BAUDHI (default=9600) */ 124 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 125 ZSWR15_BREAK_IE, 126 }; 127 128 /* Console ops */ 129 static int zscngetc(dev_t); 130 static void zscnputc(dev_t, int); 131 static void zscnpollc(dev_t, int); 132 133 struct consdev zs_consdev = { 134 NULL, 135 NULL, 136 zscngetc, 137 zscnputc, 138 zscnpollc, 139 NULL, 140 }; 141 142 143 /**************************************************************** 144 * Autoconfig 145 ****************************************************************/ 146 147 /* Definition of the driver for autoconfig. */ 148 static int zs_match_mainbus(device_t, cfdata_t, void *); 149 static int zs_match_obio(device_t, cfdata_t, void *); 150 static void zs_attach_mainbus(device_t, device_t, void *); 151 static void zs_attach_obio(device_t, device_t, void *); 152 153 #if defined(SUN4D) 154 #include <sparc/dev/bootbusvar.h> 155 156 static int zs_match_bootbus(device_t, cfdata_t, void *); 157 static void zs_attach_bootbus(device_t, device_t, void *); 158 159 CFATTACH_DECL_NEW(zs_bootbus, sizeof(struct zsc_softc), 160 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 161 #endif /* SUN4D */ 162 163 static void zs_attach(struct zsc_softc *, struct zsdevice *, int); 164 static int zs_print(void *, const char *name); 165 166 CFATTACH_DECL_NEW(zs_mainbus, sizeof(struct zsc_softc), 167 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 168 169 CFATTACH_DECL_NEW(zs_obio, sizeof(struct zsc_softc), 170 zs_match_obio, zs_attach_obio, NULL, NULL); 171 172 extern struct cfdriver zs_cd; 173 174 /* softintr(9) cookie, shared by all instances of this driver */ 175 static void *zs_sicookie; 176 177 /* Interrupt handlers. */ 178 static int zshard(void *); 179 static void zssoft(void *); 180 181 static int zs_get_speed(struct zs_chanstate *); 182 183 /* Console device support */ 184 static int zs_console_flags(int, int, int); 185 186 /* Power management hooks */ 187 int zs_enable(struct zs_chanstate *); 188 void zs_disable(struct zs_chanstate *); 189 190 191 /* XXX from dev/ic/z8530tty.c */ 192 extern struct tty *zstty_get_tty_from_dev(struct device *); 193 194 /* 195 * Is the zs chip present? 196 */ 197 static int 198 zs_match_mainbus(device_t parent, cfdata_t cf, void *aux) 199 { 200 struct mainbus_attach_args *ma = aux; 201 202 if (strcmp(cf->cf_name, ma->ma_name) != 0) 203 return (0); 204 205 return (1); 206 } 207 208 static int 209 zs_match_obio(device_t parent, cfdata_t cf, void *aux) 210 { 211 union obio_attach_args *uoba = aux; 212 struct obio4_attach_args *oba; 213 214 if (uoba->uoba_isobio4 == 0) { 215 struct sbus_attach_args *sa = &uoba->uoba_sbus; 216 217 if (strcmp(cf->cf_name, sa->sa_name) != 0) 218 return (0); 219 220 return (1); 221 } 222 223 oba = &uoba->uoba_oba4; 224 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 225 1, 0, 0, NULL, NULL)); 226 } 227 228 #if defined(SUN4D) 229 static int 230 zs_match_bootbus(device_t parent, cfdata_t cf, void *aux) 231 { 232 struct bootbus_attach_args *baa = aux; 233 234 return (strcmp(cf->cf_name, baa->ba_name) == 0); 235 } 236 #endif /* SUN4D */ 237 238 static void 239 zs_attach_mainbus(device_t parent, device_t self, void *aux) 240 { 241 struct zsc_softc *zsc = device_private(self); 242 struct mainbus_attach_args *ma = aux; 243 244 zsc->zsc_dev = self; 245 zsc->zsc_bustag = ma->ma_bustag; 246 zsc->zsc_dmatag = ma->ma_dmatag; 247 zsc->zsc_promunit = prom_getpropint(ma->ma_node, "slave", -2); 248 zsc->zsc_node = ma->ma_node; 249 250 /* 251 * For machines with zs on mainbus (all sun4c models), we expect 252 * the device registers to be mapped by the PROM. 253 */ 254 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 255 } 256 257 static void 258 zs_attach_obio(device_t parent, device_t self, void *aux) 259 { 260 struct zsc_softc *zsc = device_private(self); 261 union obio_attach_args *uoba = aux; 262 263 zsc->zsc_dev = self; 264 265 if (uoba->uoba_isobio4 == 0) { 266 struct sbus_attach_args *sa = &uoba->uoba_sbus; 267 void *va; 268 struct zs_chanstate *cs; 269 int channel; 270 271 if (sa->sa_nintr == 0) { 272 aprint_error(": no interrupt lines\n"); 273 return; 274 } 275 276 /* 277 * Some sun4m models (Javastations) may not map the zs device. 278 */ 279 if (sa->sa_npromvaddrs > 0) 280 va = (void *)sa->sa_promvaddr; 281 else { 282 bus_space_handle_t bh; 283 284 if (sbus_bus_map(sa->sa_bustag, 285 sa->sa_slot, 286 sa->sa_offset, 287 sa->sa_size, 288 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 289 aprint_error(": cannot map zs registers\n"); 290 return; 291 } 292 va = (void *)bh; 293 } 294 295 /* 296 * Check if power state can be set, e.g. Tadpole 3GX 297 */ 298 if (prom_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) { 299 aprint_normal(": powered via auxio2"); 300 for (channel = 0; channel < 2; channel++) { 301 cs = &zsc->zsc_cs_store[channel]; 302 cs->enable = zs_enable; 303 cs->disable = zs_disable; 304 } 305 } 306 307 zsc->zsc_bustag = sa->sa_bustag; 308 zsc->zsc_dmatag = sa->sa_dmatag; 309 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 310 zsc->zsc_node = sa->sa_node; 311 zs_attach(zsc, va, sa->sa_pri); 312 } else { 313 struct obio4_attach_args *oba = &uoba->uoba_oba4; 314 bus_space_handle_t bh; 315 bus_addr_t paddr = oba->oba_paddr; 316 317 /* 318 * As for zs on mainbus, we require a PROM mapping. 319 */ 320 if (bus_space_map(oba->oba_bustag, 321 paddr, 322 sizeof(struct zsdevice), 323 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 324 &bh) != 0) { 325 aprint_error(": cannot map zs registers\n"); 326 return; 327 } 328 zsc->zsc_bustag = oba->oba_bustag; 329 zsc->zsc_dmatag = oba->oba_dmatag; 330 /* 331 * Find prom unit by physical address 332 * We're just comparing the address (not the iospace) here 333 */ 334 paddr = BUS_ADDR_PADDR(paddr); 335 if (cpuinfo.cpu_type == CPUTYP_4_100) 336 /* 337 * On the sun4/100, the top-most 4 bits are zero 338 * on obio addresses; force them to 1's for the 339 * sake of the comparison here. 340 */ 341 paddr |= 0xf0000000; 342 zsc->zsc_promunit = 343 (paddr == 0xf1000000) ? 0 : 344 (paddr == 0xf0000000) ? 1 : 345 (paddr == 0xe0000000) ? 2 : -2; 346 347 zs_attach(zsc, (void *)bh, oba->oba_pri); 348 } 349 } 350 351 #if defined(SUN4D) 352 static void 353 zs_attach_bootbus(device_t parent, device_t self, void *aux) 354 { 355 struct zsc_softc *zsc = device_private(self); 356 struct bootbus_attach_args *baa = aux; 357 void *va; 358 359 zsc->zsc_dev = self; 360 361 if (baa->ba_nintr == 0) { 362 aprint_error(": no interrupt lines\n"); 363 return; 364 } 365 366 if (baa->ba_npromvaddrs > 0) 367 va = (void *) baa->ba_promvaddrs; 368 else { 369 bus_space_handle_t bh; 370 371 if (bus_space_map(baa->ba_bustag, 372 BUS_ADDR(baa->ba_slot, baa->ba_offset), 373 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 374 aprint_error(": cannot map zs registers\n"); 375 return; 376 } 377 va = (void *) bh; 378 } 379 380 zsc->zsc_bustag = baa->ba_bustag; 381 zsc->zsc_promunit = prom_getpropint(baa->ba_node, "slave", -2); 382 zsc->zsc_node = baa->ba_node; 383 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 384 } 385 #endif /* SUN4D */ 386 387 /* 388 * Attach a found zs. 389 * 390 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 391 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 392 */ 393 static void 394 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 395 { 396 struct zsc_attach_args zsc_args; 397 struct zs_chanstate *cs; 398 int channel; 399 static int didintr, prevpri; 400 #if (NKBD > 0) || (NMS > 0) 401 int ch0_is_cons = 0; 402 #endif 403 404 memset(&zsc_args, 0, sizeof zsc_args); 405 if (zsd == NULL) { 406 aprint_error(": configuration incomplete\n"); 407 return; 408 } 409 410 if (!didintr) { 411 zs_sicookie = softint_establish(SOFTINT_SERIAL, zssoft, NULL); 412 if (zs_sicookie == NULL) { 413 aprint_error(": cannot establish soft int handler\n"); 414 return; 415 } 416 } 417 aprint_normal(" softpri %d\n", IPL_SOFTSERIAL); 418 419 /* 420 * Initialize software state for each channel. 421 */ 422 for (channel = 0; channel < 2; channel++) { 423 struct zschan *zc; 424 struct device *child; 425 int hwflags; 426 427 zsc_args.channel = channel; 428 zsc_args.hwflags = 0; 429 cs = &zsc->zsc_cs_store[channel]; 430 zsc->zsc_cs[channel] = cs; 431 432 zs_lock_init(cs); 433 cs->cs_channel = channel; 434 cs->cs_private = NULL; 435 cs->cs_ops = &zsops_null; 436 cs->cs_brg_clk = PCLK / 16; 437 438 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 439 440 hwflags = zs_console_flags(zsc->zsc_promunit, 441 zsc->zsc_node, 442 channel); 443 444 #if NWSKBD == 0 445 /* Not using wscons console, so always set console flags.*/ 446 zsc_args.hwflags = hwflags; 447 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 448 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 449 zsc_args.consdev = &zs_consdev; 450 } 451 #else 452 /* If we are unit 1, then this is the "real" console. 453 * Remember this in order to set up the keyboard and 454 * mouse line disciplines for SUN4 machines below. 455 * Also, don't set the console flags, otherwise we 456 * tell zstty_attach() to attach as console. 457 */ 458 if (zsc->zsc_promunit == 1) { 459 if ((hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0 && 460 !channel) { 461 #if (NKBD > 0) || (NMS > 0) 462 ch0_is_cons = 1; 463 #endif 464 } 465 } else { 466 zsc_args.hwflags = hwflags; 467 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 468 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 469 zsc_args.consdev = &zs_consdev; 470 } 471 } 472 #endif 473 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 474 zs_conschan_get = zc; 475 } 476 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 477 zs_conschan_put = zc; 478 } 479 /* Childs need to set cn_dev, etc */ 480 481 cs->cs_reg_csr = &zc->zc_csr; 482 cs->cs_reg_data = &zc->zc_data; 483 484 memcpy(cs->cs_creg, zs_init_reg, 16); 485 memcpy(cs->cs_preg, zs_init_reg, 16); 486 487 /* XXX: Consult PROM properties for this?! */ 488 cs->cs_defspeed = zs_get_speed(cs); 489 cs->cs_defcflag = zs_def_cflag; 490 491 /* Make these correspond to cs_defcflag (-crtscts) */ 492 cs->cs_rr0_dcd = ZSRR0_DCD; 493 cs->cs_rr0_cts = 0; 494 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 495 cs->cs_wr5_rts = 0; 496 497 /* 498 * Clear the master interrupt enable. 499 * The INTENA is common to both channels, 500 * so just do it on the A channel. 501 */ 502 if (channel == 0) { 503 zs_write_reg(cs, 9, 0); 504 } 505 506 /* 507 * Look for a child driver for this channel. 508 * The child attach will setup the hardware. 509 */ 510 511 child = config_found(zsc->zsc_dev, &zsc_args, zs_print); 512 if (child == NULL) { 513 /* No sub-driver. Just reset it. */ 514 uint8_t reset = (channel == 0) ? 515 ZSWR9_A_RESET : ZSWR9_B_RESET; 516 zs_lock_chan(cs); 517 zs_write_reg(cs, 9, reset); 518 zs_unlock_chan(cs); 519 } 520 #if (NKBD > 0) || (NMS > 0) 521 /* 522 * If this was a zstty it has a keyboard 523 * property on it we need to attach the 524 * sunkbd and sunms line disciplines. 525 * There are no properties on SUN4 machines. 526 * For them, check if we have set the 527 * ch0_is_cons variable above. 528 */ 529 if ((child != NULL) && 530 (device_is_a(child, "zstty")) && ( 531 (CPU_ISSUN4 && ch0_is_cons) || (!CPU_ISSUN4 && 532 (prom_getproplen(zsc->zsc_node, "keyboard") == 0)))) 533 { 534 struct kbd_ms_tty_attach_args kma; 535 struct tty *tp = zstty_get_tty_from_dev(child); 536 kma.kmta_tp = tp; 537 kma.kmta_dev = tp->t_dev; 538 kma.kmta_consdev = zsc_args.consdev; 539 540 /* Attach 'em if we got 'em. */ 541 #if (NKBD > 0) 542 if (channel == 0) { 543 kma.kmta_name = "keyboard"; 544 config_found(child, &kma, NULL); 545 } 546 #endif 547 #if (NMS > 0) 548 if (channel == 1) { 549 kma.kmta_name = "mouse"; 550 config_found(child, &kma, NULL); 551 } 552 #endif 553 } 554 #endif 555 } 556 557 /* 558 * Now safe to install interrupt handlers. Note the arguments 559 * to the interrupt handlers aren't used. Note, we only do this 560 * once since both SCCs interrupt at the same level and vector. 561 */ 562 if (!didintr) { 563 didintr = 1; 564 prevpri = pri; 565 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 566 zshard, NULL); 567 } else if (pri != prevpri) 568 panic("broken zs interrupt scheme"); 569 570 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 571 device_xname(zsc->zsc_dev), "intr"); 572 573 /* 574 * Set the master interrupt enable and interrupt vector. 575 * (common to both channels, do it on A) 576 */ 577 cs = zsc->zsc_cs[0]; 578 zs_lock_chan(cs); 579 /* interrupt vector */ 580 zs_write_reg(cs, 2, zs_init_reg[2]); 581 /* master interrupt control (enable) */ 582 zs_write_reg(cs, 9, zs_init_reg[9]); 583 zs_unlock_chan(cs); 584 585 #if 0 586 /* 587 * XXX: L1A hack - We would like to be able to break into 588 * the debugger during the rest of autoconfiguration, so 589 * lower interrupts just enough to let zs interrupts in. 590 * This is done after both zs devices are attached. 591 */ 592 if (zsc->zsc_promunit == 1) { 593 aprint_debug("zs1: enabling zs interrupts\n"); 594 (void)splfd(); /* XXX: splzs - 1 */ 595 } 596 #endif 597 598 } 599 600 static int 601 zs_print(void *aux, const char *name) 602 { 603 struct zsc_attach_args *args = aux; 604 605 if (name != NULL) 606 aprint_normal("%s: ", name); 607 608 if (args->channel != -1) 609 aprint_normal(" channel %d", args->channel); 610 611 return (UNCONF); 612 } 613 614 static volatile int zssoftpending; 615 616 /* 617 * Our ZS chips all share a common, autovectored interrupt, 618 * so we have to look at all of them on each interrupt. 619 */ 620 static int 621 zshard(void *arg) 622 { 623 struct zsc_softc *zsc; 624 int unit, rr3, rval, softreq; 625 626 rval = softreq = 0; 627 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 628 struct zs_chanstate *cs; 629 630 zsc = device_lookup_private(&zs_cd, unit); 631 if (zsc == NULL) 632 continue; 633 rr3 = zsc_intr_hard(zsc); 634 /* Count up the interrupts. */ 635 if (rr3) { 636 rval |= rr3; 637 zsc->zsc_intrcnt.ev_count++; 638 } 639 if ((cs = zsc->zsc_cs[0]) != NULL) 640 softreq |= cs->cs_softreq; 641 if ((cs = zsc->zsc_cs[1]) != NULL) 642 softreq |= cs->cs_softreq; 643 } 644 645 /* We are at splzs here, so no need to lock. */ 646 if (softreq && (zssoftpending == 0)) { 647 zssoftpending = 1; 648 softint_schedule(zs_sicookie); 649 } 650 return (rval); 651 } 652 653 /* 654 * Similar scheme as for zshard (look at all of them) 655 */ 656 static void 657 zssoft(void *arg) 658 { 659 struct zsc_softc *zsc; 660 int unit; 661 662 /* This is not the only ISR on this IPL. */ 663 if (zssoftpending == 0) 664 return; 665 666 /* 667 * The soft intr. bit will be set by zshard only if 668 * the variable zssoftpending is zero. The order of 669 * these next two statements prevents our clearing 670 * the soft intr bit just after zshard has set it. 671 */ 672 /* ienab_bic(IE_ZSSOFT); */ 673 zssoftpending = 0; 674 675 #if 0 /* not yet */ 676 /* Make sure we call the tty layer with tty_lock held. */ 677 mutex_spin_enter(&tty_lock); 678 #endif 679 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 680 zsc = device_lookup_private(&zs_cd, unit); 681 if (zsc == NULL) 682 continue; 683 (void)zsc_intr_soft(zsc); 684 } 685 #if 0 /* not yet */ 686 mutex_spin_exit(&tty_lock); 687 #endif 688 } 689 690 691 /* 692 * Compute the current baud rate given a ZS channel. 693 */ 694 static int 695 zs_get_speed(struct zs_chanstate *cs) 696 { 697 int tconst; 698 699 tconst = zs_read_reg(cs, 12); 700 tconst |= zs_read_reg(cs, 13) << 8; 701 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 702 } 703 704 /* 705 * MD functions for setting the baud rate and control modes. 706 * bps - in bits per second 707 */ 708 int 709 zs_set_speed(struct zs_chanstate *cs, int bps) 710 { 711 int tconst, real_bps; 712 713 if (bps == 0) 714 return (0); 715 716 #ifdef DIAGNOSTIC 717 if (cs->cs_brg_clk == 0) 718 panic("zs_set_speed"); 719 #endif 720 721 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 722 if (tconst < 0) 723 return (EINVAL); 724 725 /* Convert back to make sure we can do it. */ 726 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 727 728 /* XXX - Allow some tolerance here? */ 729 if (real_bps != bps) 730 return (EINVAL); 731 732 cs->cs_preg[12] = tconst; 733 cs->cs_preg[13] = tconst >> 8; 734 735 /* Caller will stuff the pending registers. */ 736 return (0); 737 } 738 739 int 740 zs_set_modes(struct zs_chanstate *cs, int cflag) 741 { 742 743 /* 744 * Output hardware flow control on the chip is horrendous: 745 * if carrier detect drops, the receiver is disabled, and if 746 * CTS drops, the transmitter is stoped IN MID CHARACTER! 747 * Therefore, NEVER set the HFC bit, and instead use the 748 * status interrupt to detect CTS changes. 749 */ 750 zs_lock_chan(cs); 751 cs->cs_rr0_pps = 0; 752 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 753 cs->cs_rr0_dcd = 0; 754 if ((cflag & MDMBUF) == 0) 755 cs->cs_rr0_pps = ZSRR0_DCD; 756 } else 757 cs->cs_rr0_dcd = ZSRR0_DCD; 758 if ((cflag & CRTSCTS) != 0) { 759 cs->cs_wr5_dtr = ZSWR5_DTR; 760 cs->cs_wr5_rts = ZSWR5_RTS; 761 cs->cs_rr0_cts = ZSRR0_CTS; 762 } else if ((cflag & CDTRCTS) != 0) { 763 cs->cs_wr5_dtr = 0; 764 cs->cs_wr5_rts = ZSWR5_DTR; 765 cs->cs_rr0_cts = ZSRR0_CTS; 766 } else if ((cflag & MDMBUF) != 0) { 767 cs->cs_wr5_dtr = 0; 768 cs->cs_wr5_rts = ZSWR5_DTR; 769 cs->cs_rr0_cts = ZSRR0_DCD; 770 } else { 771 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 772 cs->cs_wr5_rts = 0; 773 cs->cs_rr0_cts = 0; 774 } 775 zs_unlock_chan(cs); 776 777 /* Caller will stuff the pending registers. */ 778 return (0); 779 } 780 781 782 /* 783 * Read or write the chip with suitable delays. 784 */ 785 786 uint8_t 787 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 788 { 789 uint8_t val; 790 791 *cs->cs_reg_csr = reg; 792 ZS_DELAY(); 793 val = *cs->cs_reg_csr; 794 ZS_DELAY(); 795 return (val); 796 } 797 798 void 799 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 800 { 801 802 *cs->cs_reg_csr = reg; 803 ZS_DELAY(); 804 *cs->cs_reg_csr = val; 805 ZS_DELAY(); 806 } 807 808 uint8_t 809 zs_read_csr(struct zs_chanstate *cs) 810 { 811 uint8_t val; 812 813 val = *cs->cs_reg_csr; 814 ZS_DELAY(); 815 return (val); 816 } 817 818 void 819 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 820 { 821 822 *cs->cs_reg_csr = val; 823 ZS_DELAY(); 824 } 825 826 uint8_t 827 zs_read_data(struct zs_chanstate *cs) 828 { 829 uint8_t val; 830 831 val = *cs->cs_reg_data; 832 ZS_DELAY(); 833 return (val); 834 } 835 836 void 837 zs_write_data(struct zs_chanstate *cs, uint8_t val) 838 { 839 840 *cs->cs_reg_data = val; 841 ZS_DELAY(); 842 } 843 844 /**************************************************************** 845 * Console support functions (Sun specific!) 846 * Note: this code is allowed to know about the layout of 847 * the chip registers, and uses that to keep things simple. 848 * XXX - I think I like the mvme167 code better. -gwr 849 ****************************************************************/ 850 851 /* 852 * Handle user request to enter kernel debugger. 853 */ 854 void 855 zs_abort(struct zs_chanstate *cs) 856 { 857 struct zschan *zc = zs_conschan_get; 858 int rr0; 859 860 /* Wait for end of break to avoid PROM abort. */ 861 /* XXX - Limit the wait? */ 862 do { 863 rr0 = zc->zc_csr; 864 ZS_DELAY(); 865 } while (rr0 & ZSRR0_BREAK); 866 867 #if defined(KGDB) 868 zskgdb(cs); 869 #elif defined(DDB) 870 Debugger(); 871 #else 872 printf("stopping on keyboard abort\n"); 873 callrom(); 874 #endif 875 } 876 877 int zs_getc(void *); 878 void zs_putc(void *, int); 879 880 /* 881 * Polled input char. 882 */ 883 int 884 zs_getc(void *arg) 885 { 886 struct zschan *zc = arg; 887 int s, c, rr0; 888 u_int omid; 889 890 /* Temporarily direct interrupts at ourselves */ 891 s = splhigh(); 892 omid = setitr(cpuinfo.mid); 893 894 /* Wait for a character to arrive. */ 895 do { 896 rr0 = zc->zc_csr; 897 ZS_DELAY(); 898 } while ((rr0 & ZSRR0_RX_READY) == 0); 899 900 c = zc->zc_data; 901 ZS_DELAY(); 902 setitr(omid); 903 splx(s); 904 905 /* 906 * This is used by the kd driver to read scan codes, 907 * so don't translate '\r' ==> '\n' here... 908 */ 909 return (c); 910 } 911 912 /* 913 * Polled output char. 914 */ 915 void 916 zs_putc(void *arg, int c) 917 { 918 struct zschan *zc = arg; 919 int s, rr0; 920 u_int omid; 921 922 /* Temporarily direct interrupts at ourselves */ 923 s = splhigh(); 924 omid = setitr(cpuinfo.mid); 925 926 /* Wait for transmitter to become ready. */ 927 do { 928 rr0 = zc->zc_csr; 929 ZS_DELAY(); 930 } while ((rr0 & ZSRR0_TX_READY) == 0); 931 932 /* 933 * Send the next character. 934 * Now you'd think that this could be followed by a ZS_DELAY() 935 * just like all the other chip accesses, but it turns out that 936 * the `transmit-ready' interrupt isn't de-asserted until 937 * some period of time after the register write completes 938 * (more than a couple instructions). So to avoid stray 939 * interrupts we put in the 2us delay regardless of CPU model. 940 */ 941 zc->zc_data = c; 942 delay(2); 943 944 setitr(omid); 945 splx(s); 946 } 947 948 /*****************************************************************/ 949 /* 950 * Polled console input putchar. 951 */ 952 static int 953 zscngetc(dev_t dev) 954 { 955 956 return (zs_getc(zs_conschan_get)); 957 } 958 959 /* 960 * Polled console output putchar. 961 */ 962 static void 963 zscnputc(dev_t dev, int c) 964 { 965 966 zs_putc(zs_conschan_put, c); 967 } 968 969 static void 970 zscnpollc(dev_t dev, int on) 971 { 972 973 /* No action needed */ 974 } 975 976 static int 977 zs_console_flags(int promunit, int node, int channel) 978 { 979 int cookie, flags = 0; 980 981 switch (prom_version()) { 982 case PROM_OLDMON: 983 case PROM_OBP_V0: 984 /* 985 * Use `promunit' and `channel' to derive the PROM 986 * stdio handles that correspond to this device. 987 */ 988 if (promunit == 0) 989 cookie = PROMDEV_TTYA + channel; 990 else if (promunit == 1 && channel == 0) 991 cookie = PROMDEV_KBD; 992 else 993 cookie = -1; 994 995 if (cookie == prom_stdin()) 996 flags |= ZS_HWFLAG_CONSOLE_INPUT; 997 998 /* 999 * Prevent the keyboard from matching the output device 1000 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 1001 */ 1002 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 1003 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1004 1005 break; 1006 1007 case PROM_OBP_V2: 1008 case PROM_OBP_V3: 1009 case PROM_OPENFIRM: 1010 1011 /* 1012 * Match the nodes and device arguments prepared by 1013 * consinit() against our device node and channel. 1014 * (The device argument is the part of the OBP path 1015 * following the colon, as in `/obio/zs@0,100000:a') 1016 */ 1017 1018 /* Default to channel 0 if there are no explicit prom args */ 1019 cookie = 0; 1020 1021 if (node == prom_stdin_node) { 1022 if (prom_stdin_args[0] != '\0') 1023 /* Translate (a,b) -> (0,1) */ 1024 cookie = prom_stdin_args[0] - 'a'; 1025 1026 if (channel == cookie) 1027 flags |= ZS_HWFLAG_CONSOLE_INPUT; 1028 } 1029 1030 if (node == prom_stdout_node) { 1031 if (prom_stdout_args[0] != '\0') 1032 /* Translate (a,b) -> (0,1) */ 1033 cookie = prom_stdout_args[0] - 'a'; 1034 1035 if (channel == cookie) 1036 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1037 } 1038 1039 break; 1040 1041 default: 1042 break; 1043 } 1044 1045 return (flags); 1046 } 1047 1048 /* 1049 * Power management hooks for zsopen() and zsclose(). 1050 * We use them to power on/off the ports, if necessary. 1051 */ 1052 int 1053 zs_enable(struct zs_chanstate *cs) 1054 { 1055 1056 auxiotwoserialendis (ZS_ENABLE); 1057 cs->enabled = 1; 1058 return(0); 1059 } 1060 1061 void 1062 zs_disable(struct zs_chanstate *cs) 1063 { 1064 1065 auxiotwoserialendis (ZS_DISABLE); 1066 cs->enabled = 0; 1067 } 1068