1 /* $NetBSD: zs.c,v 1.121 2012/10/27 17:18:11 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.121 2012/10/27 17:18:11 chs Exp $"); 42 43 #include "opt_ddb.h" 44 #include "opt_kgdb.h" 45 #include "opt_sparc_arch.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/conf.h> 50 #include <sys/device.h> 51 #include <sys/file.h> 52 #include <sys/ioctl.h> 53 #include <sys/kernel.h> 54 #include <sys/proc.h> 55 #include <sys/tty.h> 56 #include <sys/time.h> 57 #include <sys/syslog.h> 58 #include <sys/intr.h> 59 60 #include <machine/bsd_openprom.h> 61 #include <machine/autoconf.h> 62 #include <machine/eeprom.h> 63 #include <machine/psl.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include <sparc/sparc/vaddrs.h> 70 #include <sparc/sparc/auxreg.h> 71 #include <sparc/sparc/auxiotwo.h> 72 #include <sparc/dev/cons.h> 73 #include <dev/sun/kbd_ms_ttyvar.h> 74 75 #include "kbd.h" 76 #include "ms.h" 77 #include "wskbd.h" 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 86 /* 87 * The Sun provides a 4.9152 MHz clock to the ZS chips. 88 */ 89 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 90 91 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 92 93 /* The layout of this is hardware-dependent (padding, order). */ 94 struct zschan { 95 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 96 uint8_t zc_xxx0; 97 volatile uint8_t zc_data; /* data */ 98 uint8_t zc_xxx1; 99 }; 100 struct zsdevice { 101 /* Yes, they are backwards. */ 102 struct zschan zs_chan_b; 103 struct zschan zs_chan_a; 104 }; 105 106 /* ZS channel used as the console device (if any) */ 107 void *zs_conschan_get, *zs_conschan_put; 108 109 static uint8_t zs_init_reg[16] = { 110 0, /* 0: CMD (reset, etc.) */ 111 0, /* 1: No interrupts yet. */ 112 0, /* 2: IVECT */ 113 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 114 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 115 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 116 0, /* 6: TXSYNC/SYNCLO */ 117 0, /* 7: RXSYNC/SYNCHI */ 118 0, /* 8: alias for data port */ 119 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 120 0, /*10: Misc. TX/RX control bits */ 121 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 122 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 123 0, /*13: BAUDHI (default=9600) */ 124 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 125 ZSWR15_BREAK_IE, 126 }; 127 128 /* Console ops */ 129 static int zscngetc(dev_t); 130 static void zscnputc(dev_t, int); 131 static void zscnpollc(dev_t, int); 132 133 struct consdev zs_consdev = { 134 NULL, 135 NULL, 136 zscngetc, 137 zscnputc, 138 zscnpollc, 139 NULL, 140 }; 141 142 143 /**************************************************************** 144 * Autoconfig 145 ****************************************************************/ 146 147 /* Definition of the driver for autoconfig. */ 148 static int zs_match_mainbus(device_t, cfdata_t, void *); 149 static int zs_match_obio(device_t, cfdata_t, void *); 150 static void zs_attach_mainbus(device_t, device_t, void *); 151 static void zs_attach_obio(device_t, device_t, void *); 152 153 #if defined(SUN4D) 154 #include <sparc/dev/bootbusvar.h> 155 156 static int zs_match_bootbus(device_t, cfdata_t, void *); 157 static void zs_attach_bootbus(device_t, device_t, void *); 158 159 CFATTACH_DECL_NEW(zs_bootbus, sizeof(struct zsc_softc), 160 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 161 #endif /* SUN4D */ 162 163 static void zs_attach(struct zsc_softc *, struct zsdevice *, int); 164 static int zs_print(void *, const char *name); 165 166 CFATTACH_DECL_NEW(zs_mainbus, sizeof(struct zsc_softc), 167 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 168 169 CFATTACH_DECL_NEW(zs_obio, sizeof(struct zsc_softc), 170 zs_match_obio, zs_attach_obio, NULL, NULL); 171 172 extern struct cfdriver zs_cd; 173 174 /* Interrupt handlers. */ 175 static int zshard(void *); 176 177 static int zs_get_speed(struct zs_chanstate *); 178 179 /* Console device support */ 180 static int zs_console_flags(int, int, int); 181 182 /* Power management hooks */ 183 int zs_enable(struct zs_chanstate *); 184 void zs_disable(struct zs_chanstate *); 185 186 187 /* XXX from dev/ic/z8530tty.c */ 188 extern struct tty *zstty_get_tty_from_dev(device_t); 189 190 /* 191 * Is the zs chip present? 192 */ 193 static int 194 zs_match_mainbus(device_t parent, cfdata_t cf, void *aux) 195 { 196 struct mainbus_attach_args *ma = aux; 197 198 if (strcmp(cf->cf_name, ma->ma_name) != 0) 199 return (0); 200 201 return (1); 202 } 203 204 static int 205 zs_match_obio(device_t parent, cfdata_t cf, void *aux) 206 { 207 union obio_attach_args *uoba = aux; 208 struct obio4_attach_args *oba; 209 210 if (uoba->uoba_isobio4 == 0) { 211 struct sbus_attach_args *sa = &uoba->uoba_sbus; 212 213 if (strcmp(cf->cf_name, sa->sa_name) != 0) 214 return (0); 215 216 return (1); 217 } 218 219 oba = &uoba->uoba_oba4; 220 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 221 1, 0, 0, NULL, NULL)); 222 } 223 224 #if defined(SUN4D) 225 static int 226 zs_match_bootbus(device_t parent, cfdata_t cf, void *aux) 227 { 228 struct bootbus_attach_args *baa = aux; 229 230 return (strcmp(cf->cf_name, baa->ba_name) == 0); 231 } 232 #endif /* SUN4D */ 233 234 static void 235 zs_attach_mainbus(device_t parent, device_t self, void *aux) 236 { 237 struct zsc_softc *zsc = device_private(self); 238 struct mainbus_attach_args *ma = aux; 239 240 zsc->zsc_dev = self; 241 zsc->zsc_bustag = ma->ma_bustag; 242 zsc->zsc_dmatag = ma->ma_dmatag; 243 zsc->zsc_promunit = prom_getpropint(ma->ma_node, "slave", -2); 244 zsc->zsc_node = ma->ma_node; 245 246 /* 247 * For machines with zs on mainbus (all sun4c models), we expect 248 * the device registers to be mapped by the PROM. 249 */ 250 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 251 } 252 253 static void 254 zs_attach_obio(device_t parent, device_t self, void *aux) 255 { 256 struct zsc_softc *zsc = device_private(self); 257 union obio_attach_args *uoba = aux; 258 259 zsc->zsc_dev = self; 260 261 if (uoba->uoba_isobio4 == 0) { 262 struct sbus_attach_args *sa = &uoba->uoba_sbus; 263 void *va; 264 struct zs_chanstate *cs; 265 int channel; 266 267 if (sa->sa_nintr == 0) { 268 aprint_error(": no interrupt lines\n"); 269 return; 270 } 271 272 /* 273 * Some sun4m models (Javastations) may not map the zs device. 274 */ 275 if (sa->sa_npromvaddrs > 0) 276 va = (void *)sa->sa_promvaddr; 277 else { 278 bus_space_handle_t bh; 279 280 if (sbus_bus_map(sa->sa_bustag, 281 sa->sa_slot, 282 sa->sa_offset, 283 sa->sa_size, 284 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 285 aprint_error(": cannot map zs registers\n"); 286 return; 287 } 288 va = (void *)bh; 289 } 290 291 /* 292 * Check if power state can be set, e.g. Tadpole 3GX 293 */ 294 if (prom_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) { 295 aprint_normal(": powered via auxio2"); 296 for (channel = 0; channel < 2; channel++) { 297 cs = &zsc->zsc_cs_store[channel]; 298 cs->enable = zs_enable; 299 cs->disable = zs_disable; 300 } 301 } 302 303 zsc->zsc_bustag = sa->sa_bustag; 304 zsc->zsc_dmatag = sa->sa_dmatag; 305 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 306 zsc->zsc_node = sa->sa_node; 307 zs_attach(zsc, va, sa->sa_pri); 308 } else { 309 struct obio4_attach_args *oba = &uoba->uoba_oba4; 310 bus_space_handle_t bh; 311 bus_addr_t paddr = oba->oba_paddr; 312 313 /* 314 * As for zs on mainbus, we require a PROM mapping. 315 */ 316 if (bus_space_map(oba->oba_bustag, 317 paddr, 318 sizeof(struct zsdevice), 319 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 320 &bh) != 0) { 321 aprint_error(": cannot map zs registers\n"); 322 return; 323 } 324 zsc->zsc_bustag = oba->oba_bustag; 325 zsc->zsc_dmatag = oba->oba_dmatag; 326 /* 327 * Find prom unit by physical address 328 * We're just comparing the address (not the iospace) here 329 */ 330 paddr = BUS_ADDR_PADDR(paddr); 331 if (cpuinfo.cpu_type == CPUTYP_4_100) 332 /* 333 * On the sun4/100, the top-most 4 bits are zero 334 * on obio addresses; force them to 1's for the 335 * sake of the comparison here. 336 */ 337 paddr |= 0xf0000000; 338 zsc->zsc_promunit = 339 (paddr == 0xf1000000) ? 0 : 340 (paddr == 0xf0000000) ? 1 : 341 (paddr == 0xe0000000) ? 2 : -2; 342 343 zs_attach(zsc, (void *)bh, oba->oba_pri); 344 } 345 } 346 347 #if defined(SUN4D) 348 static void 349 zs_attach_bootbus(device_t parent, device_t self, void *aux) 350 { 351 struct zsc_softc *zsc = device_private(self); 352 struct bootbus_attach_args *baa = aux; 353 void *va; 354 355 zsc->zsc_dev = self; 356 357 if (baa->ba_nintr == 0) { 358 aprint_error(": no interrupt lines\n"); 359 return; 360 } 361 362 if (baa->ba_npromvaddrs > 0) 363 va = (void *) baa->ba_promvaddrs; 364 else { 365 bus_space_handle_t bh; 366 367 if (bus_space_map(baa->ba_bustag, 368 BUS_ADDR(baa->ba_slot, baa->ba_offset), 369 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 370 aprint_error(": cannot map zs registers\n"); 371 return; 372 } 373 va = (void *) bh; 374 } 375 376 zsc->zsc_bustag = baa->ba_bustag; 377 zsc->zsc_promunit = prom_getpropint(baa->ba_node, "slave", -2); 378 zsc->zsc_node = baa->ba_node; 379 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 380 } 381 #endif /* SUN4D */ 382 383 /* 384 * Attach a found zs. 385 * 386 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 387 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 388 */ 389 static void 390 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 391 { 392 struct zsc_attach_args zsc_args; 393 struct zs_chanstate *cs; 394 int channel; 395 #if (NKBD > 0) || (NMS > 0) 396 int ch0_is_cons = 0; 397 #endif 398 399 memset(&zsc_args, 0, sizeof zsc_args); 400 if (zsd == NULL) { 401 aprint_error(": configuration incomplete\n"); 402 return; 403 } 404 405 zsc->zsc_sicookie = softint_establish(SOFTINT_SERIAL, 406 (void (*)(void *))zsc_intr_soft, zsc); 407 if (zsc->zsc_sicookie == NULL) { 408 aprint_error(": cannot establish soft int handler\n"); 409 return; 410 } 411 aprint_normal(" softpri %d\n", IPL_SOFTSERIAL); 412 413 /* 414 * Initialize software state for each channel. 415 */ 416 for (channel = 0; channel < 2; channel++) { 417 struct zschan *zc; 418 device_t child; 419 int hwflags; 420 421 zsc_args.channel = channel; 422 zsc_args.hwflags = 0; 423 cs = &zsc->zsc_cs_store[channel]; 424 zsc->zsc_cs[channel] = cs; 425 426 zs_lock_init(cs); 427 cs->cs_channel = channel; 428 cs->cs_private = NULL; 429 cs->cs_ops = &zsops_null; 430 cs->cs_brg_clk = PCLK / 16; 431 432 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 433 434 hwflags = zs_console_flags(zsc->zsc_promunit, 435 zsc->zsc_node, 436 channel); 437 438 #if NWSKBD == 0 439 /* Not using wscons console, so always set console flags.*/ 440 zsc_args.hwflags = hwflags; 441 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 442 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 443 zsc_args.consdev = &zs_consdev; 444 } 445 #else 446 /* If we are unit 1, then this is the "real" console. 447 * Remember this in order to set up the keyboard and 448 * mouse line disciplines for SUN4 machines below. 449 * Also, don't set the console flags, otherwise we 450 * tell zstty_attach() to attach as console. 451 * XXX 452 * is this still necessary? sparc64 passes the console flags to 453 * zstty etc. 454 */ 455 if (zsc->zsc_promunit == 1) { 456 if ((hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0 && 457 !channel) { 458 #if (NKBD > 0) || (NMS > 0) 459 ch0_is_cons = 1; 460 #endif 461 } 462 } else { 463 zsc_args.hwflags = hwflags; 464 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 465 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 466 zsc_args.consdev = &zs_consdev; 467 } 468 } 469 #endif 470 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 471 zs_conschan_get = zc; 472 } 473 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 474 zs_conschan_put = zc; 475 } 476 /* Childs need to set cn_dev, etc */ 477 478 cs->cs_reg_csr = &zc->zc_csr; 479 cs->cs_reg_data = &zc->zc_data; 480 481 memcpy(cs->cs_creg, zs_init_reg, 16); 482 memcpy(cs->cs_preg, zs_init_reg, 16); 483 484 /* XXX: Consult PROM properties for this?! */ 485 cs->cs_defspeed = zs_get_speed(cs); 486 cs->cs_defcflag = zs_def_cflag; 487 488 /* Make these correspond to cs_defcflag (-crtscts) */ 489 cs->cs_rr0_dcd = ZSRR0_DCD; 490 cs->cs_rr0_cts = 0; 491 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 492 cs->cs_wr5_rts = 0; 493 494 /* 495 * Clear the master interrupt enable. 496 * The INTENA is common to both channels, 497 * so just do it on the A channel. 498 */ 499 if (channel == 0) { 500 zs_write_reg(cs, 9, 0); 501 } 502 503 /* 504 * Look for a child driver for this channel. 505 * The child attach will setup the hardware. 506 */ 507 508 child = config_found(zsc->zsc_dev, &zsc_args, zs_print); 509 if (child == NULL) { 510 /* No sub-driver. Just reset it. */ 511 uint8_t reset = (channel == 0) ? 512 ZSWR9_A_RESET : ZSWR9_B_RESET; 513 zs_lock_chan(cs); 514 zs_write_reg(cs, 9, reset); 515 zs_unlock_chan(cs); 516 } 517 #if (NKBD > 0) || (NMS > 0) 518 /* 519 * If this was a zstty it has a keyboard 520 * property on it we need to attach the 521 * sunkbd and sunms line disciplines. 522 * There are no properties on SUN4 machines. 523 * For them, check if we have set the 524 * ch0_is_cons variable above. 525 */ 526 if ((child != NULL) && 527 (device_is_a(child, "zstty")) && ( 528 (CPU_ISSUN4 && ch0_is_cons) || (!CPU_ISSUN4 && 529 (prom_getproplen(zsc->zsc_node, "keyboard") == 0)))) 530 { 531 struct kbd_ms_tty_attach_args kma; 532 struct tty *tp = zstty_get_tty_from_dev(child); 533 kma.kmta_tp = tp; 534 kma.kmta_dev = tp->t_dev; 535 536 /* 537 * we need to pass a consdev since that's how kbd knows 538 * it's the console keyboard 539 */ 540 if (hwflags & ZS_HWFLAG_CONSOLE_INPUT) { 541 kma.kmta_consdev = &zs_consdev; 542 } else 543 kma.kmta_consdev = zsc_args.consdev; 544 545 /* Attach 'em if we got 'em. */ 546 #if (NKBD > 0) 547 if (channel == 0) { 548 kma.kmta_name = "keyboard"; 549 config_found(child, &kma, NULL); 550 } 551 #endif 552 #if (NMS > 0) 553 if (channel == 1) { 554 kma.kmta_name = "mouse"; 555 config_found(child, &kma, NULL); 556 } 557 #endif 558 } 559 #endif 560 } 561 562 /* 563 * Now safe to install interrupt handlers. 564 */ 565 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, zshard, zsc); 566 567 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 568 device_xname(zsc->zsc_dev), "intr"); 569 570 /* 571 * Set the master interrupt enable and interrupt vector. 572 * (common to both channels, do it on A) 573 */ 574 cs = zsc->zsc_cs[0]; 575 zs_lock_chan(cs); 576 /* interrupt vector */ 577 zs_write_reg(cs, 2, zs_init_reg[2]); 578 /* master interrupt control (enable) */ 579 zs_write_reg(cs, 9, zs_init_reg[9]); 580 zs_unlock_chan(cs); 581 582 #if 0 583 /* 584 * XXX: L1A hack - We would like to be able to break into 585 * the debugger during the rest of autoconfiguration, so 586 * lower interrupts just enough to let zs interrupts in. 587 * This is done after both zs devices are attached. 588 */ 589 if (zsc->zsc_promunit == 1) { 590 aprint_debug("zs1: enabling zs interrupts\n"); 591 (void)splfd(); /* XXX: splzs - 1 */ 592 } 593 #endif 594 595 } 596 597 static int 598 zs_print(void *aux, const char *name) 599 { 600 struct zsc_attach_args *args = aux; 601 602 if (name != NULL) 603 aprint_normal("%s: ", name); 604 605 if (args->channel != -1) 606 aprint_normal(" channel %d", args->channel); 607 608 return (UNCONF); 609 } 610 611 /* 612 * Our ZS chips all share a common interrupt level, 613 * but we establish zshard handler per each ZS chips 614 * to avoid holding unnecessary locks in interrupt context. 615 */ 616 static int 617 zshard(void *arg) 618 { 619 struct zsc_softc *zsc = arg; 620 int rr3, rval; 621 622 rval = 0; 623 rr3 = zsc_intr_hard(zsc); 624 /* Count up the interrupts. */ 625 if (rr3) { 626 rval = rr3; 627 zsc->zsc_intrcnt.ev_count++; 628 } 629 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 630 softint_schedule(zsc->zsc_sicookie); 631 return (rval); 632 } 633 634 /* 635 * Compute the current baud rate given a ZS channel. 636 */ 637 static int 638 zs_get_speed(struct zs_chanstate *cs) 639 { 640 int tconst; 641 642 tconst = zs_read_reg(cs, 12); 643 tconst |= zs_read_reg(cs, 13) << 8; 644 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 645 } 646 647 /* 648 * MD functions for setting the baud rate and control modes. 649 * bps - in bits per second 650 */ 651 int 652 zs_set_speed(struct zs_chanstate *cs, int bps) 653 { 654 int tconst, real_bps; 655 656 if (bps == 0) 657 return (0); 658 659 #ifdef DIAGNOSTIC 660 if (cs->cs_brg_clk == 0) 661 panic("zs_set_speed"); 662 #endif 663 664 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 665 if (tconst < 0) 666 return (EINVAL); 667 668 /* Convert back to make sure we can do it. */ 669 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 670 671 /* XXX - Allow some tolerance here? */ 672 if (real_bps != bps) 673 return (EINVAL); 674 675 cs->cs_preg[12] = tconst; 676 cs->cs_preg[13] = tconst >> 8; 677 678 /* Caller will stuff the pending registers. */ 679 return (0); 680 } 681 682 int 683 zs_set_modes(struct zs_chanstate *cs, int cflag) 684 { 685 686 /* 687 * Output hardware flow control on the chip is horrendous: 688 * if carrier detect drops, the receiver is disabled, and if 689 * CTS drops, the transmitter is stoped IN MID CHARACTER! 690 * Therefore, NEVER set the HFC bit, and instead use the 691 * status interrupt to detect CTS changes. 692 */ 693 zs_lock_chan(cs); 694 cs->cs_rr0_pps = 0; 695 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 696 cs->cs_rr0_dcd = 0; 697 if ((cflag & MDMBUF) == 0) 698 cs->cs_rr0_pps = ZSRR0_DCD; 699 } else 700 cs->cs_rr0_dcd = ZSRR0_DCD; 701 if ((cflag & CRTSCTS) != 0) { 702 cs->cs_wr5_dtr = ZSWR5_DTR; 703 cs->cs_wr5_rts = ZSWR5_RTS; 704 cs->cs_rr0_cts = ZSRR0_CTS; 705 } else if ((cflag & CDTRCTS) != 0) { 706 cs->cs_wr5_dtr = 0; 707 cs->cs_wr5_rts = ZSWR5_DTR; 708 cs->cs_rr0_cts = ZSRR0_CTS; 709 } else if ((cflag & MDMBUF) != 0) { 710 cs->cs_wr5_dtr = 0; 711 cs->cs_wr5_rts = ZSWR5_DTR; 712 cs->cs_rr0_cts = ZSRR0_DCD; 713 } else { 714 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 715 cs->cs_wr5_rts = 0; 716 cs->cs_rr0_cts = 0; 717 } 718 zs_unlock_chan(cs); 719 720 /* Caller will stuff the pending registers. */ 721 return (0); 722 } 723 724 725 /* 726 * Read or write the chip with suitable delays. 727 */ 728 729 uint8_t 730 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 731 { 732 uint8_t val; 733 734 *cs->cs_reg_csr = reg; 735 ZS_DELAY(); 736 val = *cs->cs_reg_csr; 737 ZS_DELAY(); 738 return (val); 739 } 740 741 void 742 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 743 { 744 745 *cs->cs_reg_csr = reg; 746 ZS_DELAY(); 747 *cs->cs_reg_csr = val; 748 ZS_DELAY(); 749 } 750 751 uint8_t 752 zs_read_csr(struct zs_chanstate *cs) 753 { 754 uint8_t val; 755 756 val = *cs->cs_reg_csr; 757 ZS_DELAY(); 758 return (val); 759 } 760 761 void 762 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 763 { 764 765 *cs->cs_reg_csr = val; 766 ZS_DELAY(); 767 } 768 769 uint8_t 770 zs_read_data(struct zs_chanstate *cs) 771 { 772 uint8_t val; 773 774 val = *cs->cs_reg_data; 775 ZS_DELAY(); 776 return (val); 777 } 778 779 void 780 zs_write_data(struct zs_chanstate *cs, uint8_t val) 781 { 782 783 *cs->cs_reg_data = val; 784 ZS_DELAY(); 785 } 786 787 /**************************************************************** 788 * Console support functions (Sun specific!) 789 * Note: this code is allowed to know about the layout of 790 * the chip registers, and uses that to keep things simple. 791 * XXX - I think I like the mvme167 code better. -gwr 792 ****************************************************************/ 793 794 /* 795 * Handle user request to enter kernel debugger. 796 */ 797 void 798 zs_abort(struct zs_chanstate *cs) 799 { 800 struct zschan *zc = zs_conschan_get; 801 int rr0; 802 803 /* Wait for end of break to avoid PROM abort. */ 804 /* XXX - Limit the wait? */ 805 do { 806 rr0 = zc->zc_csr; 807 ZS_DELAY(); 808 } while (rr0 & ZSRR0_BREAK); 809 810 #if defined(KGDB) 811 zskgdb(cs); 812 #elif defined(DDB) 813 Debugger(); 814 #else 815 printf("stopping on keyboard abort\n"); 816 callrom(); 817 #endif 818 } 819 820 int zs_getc(void *); 821 void zs_putc(void *, int); 822 823 /* 824 * Polled input char. 825 */ 826 int 827 zs_getc(void *arg) 828 { 829 struct zschan *zc = arg; 830 int s, c, rr0; 831 u_int omid; 832 833 /* Temporarily direct interrupts at ourselves */ 834 s = splhigh(); 835 omid = setitr(cpuinfo.mid); 836 837 /* Wait for a character to arrive. */ 838 do { 839 rr0 = zc->zc_csr; 840 ZS_DELAY(); 841 } while ((rr0 & ZSRR0_RX_READY) == 0); 842 843 c = zc->zc_data; 844 ZS_DELAY(); 845 setitr(omid); 846 splx(s); 847 848 /* 849 * This is used by the kd driver to read scan codes, 850 * so don't translate '\r' ==> '\n' here... 851 */ 852 return (c); 853 } 854 855 /* 856 * Polled output char. 857 */ 858 void 859 zs_putc(void *arg, int c) 860 { 861 struct zschan *zc = arg; 862 int s, rr0; 863 u_int omid; 864 865 /* Temporarily direct interrupts at ourselves */ 866 s = splhigh(); 867 omid = setitr(cpuinfo.mid); 868 869 /* Wait for transmitter to become ready. */ 870 do { 871 rr0 = zc->zc_csr; 872 ZS_DELAY(); 873 } while ((rr0 & ZSRR0_TX_READY) == 0); 874 875 /* 876 * Send the next character. 877 * Now you'd think that this could be followed by a ZS_DELAY() 878 * just like all the other chip accesses, but it turns out that 879 * the `transmit-ready' interrupt isn't de-asserted until 880 * some period of time after the register write completes 881 * (more than a couple instructions). So to avoid stray 882 * interrupts we put in the 2us delay regardless of CPU model. 883 */ 884 zc->zc_data = c; 885 delay(2); 886 887 setitr(omid); 888 splx(s); 889 } 890 891 /*****************************************************************/ 892 /* 893 * Polled console input putchar. 894 */ 895 static int 896 zscngetc(dev_t dev) 897 { 898 899 return (zs_getc(zs_conschan_get)); 900 } 901 902 /* 903 * Polled console output putchar. 904 */ 905 static void 906 zscnputc(dev_t dev, int c) 907 { 908 909 zs_putc(zs_conschan_put, c); 910 } 911 912 static void 913 zscnpollc(dev_t dev, int on) 914 { 915 916 /* No action needed */ 917 } 918 919 static int 920 zs_console_flags(int promunit, int node, int channel) 921 { 922 int cookie, flags = 0; 923 924 switch (prom_version()) { 925 case PROM_OLDMON: 926 case PROM_OBP_V0: 927 /* 928 * Use `promunit' and `channel' to derive the PROM 929 * stdio handles that correspond to this device. 930 */ 931 if (promunit == 0) 932 cookie = PROMDEV_TTYA + channel; 933 else if (promunit == 1 && channel == 0) 934 cookie = PROMDEV_KBD; 935 else 936 cookie = -1; 937 938 if (cookie == prom_stdin()) 939 flags |= ZS_HWFLAG_CONSOLE_INPUT; 940 941 /* 942 * Prevent the keyboard from matching the output device 943 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 944 */ 945 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 946 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 947 948 break; 949 950 case PROM_OBP_V2: 951 case PROM_OBP_V3: 952 case PROM_OPENFIRM: 953 954 /* 955 * Match the nodes and device arguments prepared by 956 * consinit() against our device node and channel. 957 * (The device argument is the part of the OBP path 958 * following the colon, as in `/obio/zs@0,100000:a') 959 */ 960 961 /* Default to channel 0 if there are no explicit prom args */ 962 cookie = 0; 963 964 if (node == prom_stdin_node) { 965 if (prom_stdin_args[0] != '\0') 966 /* Translate (a,b) -> (0,1) */ 967 cookie = prom_stdin_args[0] - 'a'; 968 969 if (channel == cookie) 970 flags |= ZS_HWFLAG_CONSOLE_INPUT; 971 } 972 973 if (node == prom_stdout_node) { 974 if (prom_stdout_args[0] != '\0') 975 /* Translate (a,b) -> (0,1) */ 976 cookie = prom_stdout_args[0] - 'a'; 977 978 if (channel == cookie) 979 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 980 } 981 982 break; 983 984 default: 985 break; 986 } 987 988 return (flags); 989 } 990 991 /* 992 * Power management hooks for zsopen() and zsclose(). 993 * We use them to power on/off the ports, if necessary. 994 */ 995 int 996 zs_enable(struct zs_chanstate *cs) 997 { 998 999 auxiotwoserialendis (ZS_ENABLE); 1000 cs->enabled = 1; 1001 return(0); 1002 } 1003 1004 void 1005 zs_disable(struct zs_chanstate *cs) 1006 { 1007 1008 auxiotwoserialendis (ZS_DISABLE); 1009 cs->enabled = 0; 1010 } 1011