1 /* $NetBSD: zs.c,v 1.81 2000/10/18 23:55:11 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/bsd_openprom.h> 62 #include <machine/autoconf.h> 63 #include <machine/intr.h> 64 #include <machine/conf.h> 65 #include <machine/eeprom.h> 66 #include <machine/psl.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/cons.h> 70 #include <dev/ic/z8530reg.h> 71 72 #include <sparc/sparc/vaddrs.h> 73 #include <sparc/sparc/auxreg.h> 74 #include <sparc/sparc/auxiotwo.h> 75 #include <sparc/dev/cons.h> 76 77 #include "kbd.h" /* NKBD */ 78 #include "zs.h" /* NZS */ 79 80 /* Make life easier for the initialized arrays here. */ 81 #if NZS < 3 82 #undef NZS 83 #define NZS 3 84 #endif 85 86 /* 87 * Some warts needed by z8530tty.c - 88 * The default parity REALLY needs to be the same as the PROM uses, 89 * or you can not see messages done with printf during boot-up... 90 */ 91 int zs_def_cflag = (CREAD | CS8 | HUPCL); 92 int zs_major = 12; 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 /* 100 * Select software interrupt bit based on TTY ipl. 101 */ 102 #if PIL_TTY == 1 103 # define IE_ZSSOFT IE_L1 104 #elif PIL_TTY == 4 105 # define IE_ZSSOFT IE_L4 106 #elif PIL_TTY == 6 107 # define IE_ZSSOFT IE_L6 108 #else 109 # error "no suitable software interrupt bit" 110 #endif 111 112 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zschan { 116 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 117 u_char zc_xxx0; 118 volatile u_char zc_data; /* data */ 119 u_char zc_xxx1; 120 }; 121 struct zsdevice { 122 /* Yes, they are backwards. */ 123 struct zschan zs_chan_b; 124 struct zschan zs_chan_a; 125 }; 126 127 /* ZS channel used as the console device (if any) */ 128 void *zs_conschan_get, *zs_conschan_put; 129 130 static u_char zs_init_reg[16] = { 131 0, /* 0: CMD (reset, etc.) */ 132 0, /* 1: No interrupts yet. */ 133 0, /* 2: IVECT */ 134 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 135 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 136 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 137 0, /* 6: TXSYNC/SYNCLO */ 138 0, /* 7: RXSYNC/SYNCHI */ 139 0, /* 8: alias for data port */ 140 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 141 0, /*10: Misc. TX/RX control bits */ 142 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 143 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 144 0, /*13: BAUDHI (default=9600) */ 145 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 146 ZSWR15_BREAK_IE, 147 }; 148 149 /* Console ops */ 150 static int zscngetc __P((dev_t)); 151 static void zscnputc __P((dev_t, int)); 152 static void zscnpollc __P((dev_t, int)); 153 154 struct consdev zs_consdev = { 155 NULL, 156 NULL, 157 zscngetc, 158 zscnputc, 159 zscnpollc, 160 NULL, 161 }; 162 163 164 /**************************************************************** 165 * Autoconfig 166 ****************************************************************/ 167 168 /* Definition of the driver for autoconfig. */ 169 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 170 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 171 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 172 static void zs_attach_obio __P((struct device *, struct device *, void *)); 173 174 175 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 176 static int zs_print __P((void *, const char *name)); 177 178 struct cfattach zs_mainbus_ca = { 179 sizeof(struct zsc_softc), zs_match_mainbus, zs_attach_mainbus 180 }; 181 182 struct cfattach zs_obio_ca = { 183 sizeof(struct zsc_softc), zs_match_obio, zs_attach_obio 184 }; 185 186 extern struct cfdriver zs_cd; 187 188 /* Interrupt handlers. */ 189 static int zshard __P((void *)); 190 static int zssoft __P((void *)); 191 192 static int zs_get_speed __P((struct zs_chanstate *)); 193 194 /* Console device support */ 195 static int zs_console_flags __P((int, int, int)); 196 197 /* Power management hooks */ 198 int zs_enable __P((struct zs_chanstate *)); 199 void zs_disable __P((struct zs_chanstate *)); 200 201 202 /* 203 * Is the zs chip present? 204 */ 205 static int 206 zs_match_mainbus(parent, cf, aux) 207 struct device *parent; 208 struct cfdata *cf; 209 void *aux; 210 { 211 struct mainbus_attach_args *ma = aux; 212 213 if (strcmp(cf->cf_driver->cd_name, ma->ma_name) != 0) 214 return (0); 215 216 return (1); 217 } 218 219 static int 220 zs_match_obio(parent, cf, aux) 221 struct device *parent; 222 struct cfdata *cf; 223 void *aux; 224 { 225 union obio_attach_args *uoba = aux; 226 struct obio4_attach_args *oba; 227 228 if (uoba->uoba_isobio4 == 0) { 229 struct sbus_attach_args *sa = &uoba->uoba_sbus; 230 231 if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0) 232 return (0); 233 234 return (1); 235 } 236 237 oba = &uoba->uoba_oba4; 238 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 239 1, 0, 0, NULL, NULL)); 240 } 241 242 static void 243 zs_attach_mainbus(parent, self, aux) 244 struct device *parent; 245 struct device *self; 246 void *aux; 247 { 248 struct zsc_softc *zsc = (void *) self; 249 struct mainbus_attach_args *ma = aux; 250 251 zsc->zsc_bustag = ma->ma_bustag; 252 zsc->zsc_dmatag = ma->ma_dmatag; 253 zsc->zsc_promunit = getpropint(ma->ma_node, "slave", -2); 254 zsc->zsc_node = ma->ma_node; 255 256 /* 257 * For machines with zs on mainbus (all sun4c models), we expect 258 * the device registers to be mapped by the PROM. 259 */ 260 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 261 } 262 263 static void 264 zs_attach_obio(parent, self, aux) 265 struct device *parent; 266 struct device *self; 267 void *aux; 268 { 269 struct zsc_softc *zsc = (void *) self; 270 union obio_attach_args *uoba = aux; 271 272 if (uoba->uoba_isobio4 == 0) { 273 struct sbus_attach_args *sa = &uoba->uoba_sbus; 274 void *va; 275 struct zs_chanstate *cs; 276 int channel; 277 278 if (sa->sa_nintr == 0) { 279 printf(" no interrupt lines\n"); 280 return; 281 } 282 283 /* 284 * Some sun4m models (Javastations) may not map the zs device. 285 */ 286 if (sa->sa_npromvaddrs > 0) 287 va = (void *)sa->sa_promvaddr; 288 else { 289 bus_space_handle_t bh; 290 291 if (sbus_bus_map(sa->sa_bustag, 292 sa->sa_slot, 293 sa->sa_offset, 294 sa->sa_size, 295 BUS_SPACE_MAP_LINEAR, 296 0, &bh) != 0) { 297 printf(" cannot map zs registers\n"); 298 return; 299 } 300 va = (void *)bh; 301 } 302 303 /* 304 * Check if power state can be set, e.g. Tadpole 3GX 305 */ 306 if (getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 307 { 308 printf (" powered via auxio2"); 309 for (channel = 0; channel < 2; channel++) { 310 cs = &zsc->zsc_cs_store[channel]; 311 cs->enable = zs_enable; 312 cs->disable = zs_disable; 313 } 314 } 315 316 zsc->zsc_bustag = sa->sa_bustag; 317 zsc->zsc_dmatag = sa->sa_dmatag; 318 zsc->zsc_promunit = getpropint(sa->sa_node, "slave", -2); 319 zsc->zsc_node = sa->sa_node; 320 zs_attach(zsc, va, sa->sa_pri); 321 } else { 322 struct obio4_attach_args *oba = &uoba->uoba_oba4; 323 bus_space_handle_t bh; 324 bus_addr_t paddr = oba->oba_paddr; 325 326 /* 327 * As for zs on mainbus, we require a PROM mapping. 328 */ 329 if (bus_space_map(oba->oba_bustag, 330 paddr, 331 sizeof(struct zsdevice), 332 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 333 &bh) != 0) { 334 printf(" cannot map zs registers\n"); 335 return; 336 } 337 zsc->zsc_bustag = oba->oba_bustag; 338 zsc->zsc_dmatag = oba->oba_dmatag; 339 /* Find prom unit by physical address */ 340 if (cpuinfo.cpu_type == CPUTYP_4_100) 341 /* 342 * On the sun4/100, the top-most 4 bits are zero 343 * on obio addresses; force them to 1's for the 344 * sake of the comparison here. 345 */ 346 paddr |= 0xf0000000; 347 zsc->zsc_promunit = 348 (paddr == 0xf1000000) ? 0 : 349 (paddr == 0xf0000000) ? 1 : 350 (paddr == 0xe0000000) ? 2 : -2; 351 352 zs_attach(zsc, (void *)bh, oba->oba_pri); 353 } 354 } 355 /* 356 * Attach a found zs. 357 * 358 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 359 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 360 */ 361 static void 362 zs_attach(zsc, zsd, pri) 363 struct zsc_softc *zsc; 364 struct zsdevice *zsd; 365 int pri; 366 { 367 struct zsc_attach_args zsc_args; 368 struct zs_chanstate *cs; 369 int s, channel; 370 static int didintr, prevpri; 371 372 if (zsd == NULL) { 373 printf("configuration incomplete\n"); 374 return; 375 } 376 377 printf(" softpri %d\n", PIL_TTY); 378 379 /* 380 * Initialize software state for each channel. 381 */ 382 for (channel = 0; channel < 2; channel++) { 383 struct zschan *zc; 384 385 zsc_args.channel = channel; 386 cs = &zsc->zsc_cs_store[channel]; 387 zsc->zsc_cs[channel] = cs; 388 389 cs->cs_channel = channel; 390 cs->cs_private = NULL; 391 cs->cs_ops = &zsops_null; 392 cs->cs_brg_clk = PCLK / 16; 393 394 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 395 396 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 397 zsc->zsc_node, 398 channel); 399 400 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 401 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 402 zsc_args.consdev = &zs_consdev; 403 } 404 405 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 406 zs_conschan_get = zc; 407 } 408 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 409 zs_conschan_put = zc; 410 } 411 /* Childs need to set cn_dev, etc */ 412 413 cs->cs_reg_csr = &zc->zc_csr; 414 cs->cs_reg_data = &zc->zc_data; 415 416 bcopy(zs_init_reg, cs->cs_creg, 16); 417 bcopy(zs_init_reg, cs->cs_preg, 16); 418 419 /* XXX: Consult PROM properties for this?! */ 420 cs->cs_defspeed = zs_get_speed(cs); 421 cs->cs_defcflag = zs_def_cflag; 422 423 /* Make these correspond to cs_defcflag (-crtscts) */ 424 cs->cs_rr0_dcd = ZSRR0_DCD; 425 cs->cs_rr0_cts = 0; 426 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 427 cs->cs_wr5_rts = 0; 428 429 /* 430 * Clear the master interrupt enable. 431 * The INTENA is common to both channels, 432 * so just do it on the A channel. 433 */ 434 if (channel == 0) { 435 zs_write_reg(cs, 9, 0); 436 } 437 438 /* 439 * Look for a child driver for this channel. 440 * The child attach will setup the hardware. 441 */ 442 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 443 /* No sub-driver. Just reset it. */ 444 u_char reset = (channel == 0) ? 445 ZSWR9_A_RESET : ZSWR9_B_RESET; 446 s = splzs(); 447 zs_write_reg(cs, 9, reset); 448 splx(s); 449 } 450 } 451 452 /* 453 * Now safe to install interrupt handlers. Note the arguments 454 * to the interrupt handlers aren't used. Note, we only do this 455 * once since both SCCs interrupt at the same level and vector. 456 */ 457 if (!didintr) { 458 didintr = 1; 459 prevpri = pri; 460 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, 461 zshard, NULL); 462 bus_intr_establish(zsc->zsc_bustag, PIL_TTY, 463 IPL_SOFTSERIAL, 464 BUS_INTR_ESTABLISH_SOFTINTR, 465 zssoft, NULL); 466 } else if (pri != prevpri) 467 panic("broken zs interrupt scheme"); 468 469 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 470 zsc->zsc_dev.dv_xname, "intr"); 471 472 /* 473 * Set the master interrupt enable and interrupt vector. 474 * (common to both channels, do it on A) 475 */ 476 cs = zsc->zsc_cs[0]; 477 s = splhigh(); 478 /* interrupt vector */ 479 zs_write_reg(cs, 2, zs_init_reg[2]); 480 /* master interrupt control (enable) */ 481 zs_write_reg(cs, 9, zs_init_reg[9]); 482 splx(s); 483 484 #if 0 485 /* 486 * XXX: L1A hack - We would like to be able to break into 487 * the debugger during the rest of autoconfiguration, so 488 * lower interrupts just enough to let zs interrupts in. 489 * This is done after both zs devices are attached. 490 */ 491 if (zsc->zsc_promunit == 1) { 492 printf("zs1: enabling zs interrupts\n"); 493 (void)splfd(); /* XXX: splzs - 1 */ 494 } 495 #endif 496 } 497 498 static int 499 zs_print(aux, name) 500 void *aux; 501 const char *name; 502 { 503 struct zsc_attach_args *args = aux; 504 505 if (name != NULL) 506 printf("%s: ", name); 507 508 if (args->channel != -1) 509 printf(" channel %d", args->channel); 510 511 return (UNCONF); 512 } 513 514 static volatile int zssoftpending; 515 516 /* 517 * Our ZS chips all share a common, autovectored interrupt, 518 * so we have to look at all of them on each interrupt. 519 */ 520 static int 521 zshard(arg) 522 void *arg; 523 { 524 struct zsc_softc *zsc; 525 int unit, rr3, rval, softreq; 526 527 rval = softreq = 0; 528 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 529 struct zs_chanstate *cs; 530 531 zsc = zs_cd.cd_devs[unit]; 532 if (zsc == NULL) 533 continue; 534 rr3 = zsc_intr_hard(zsc); 535 /* Count up the interrupts. */ 536 if (rr3) { 537 rval |= rr3; 538 zsc->zsc_intrcnt.ev_count++; 539 } 540 if ((cs = zsc->zsc_cs[0]) != NULL) 541 softreq |= cs->cs_softreq; 542 if ((cs = zsc->zsc_cs[1]) != NULL) 543 softreq |= cs->cs_softreq; 544 } 545 546 /* We are at splzs here, so no need to lock. */ 547 if (softreq && (zssoftpending == 0)) { 548 zssoftpending = IE_ZSSOFT; 549 #if defined(SUN4M) 550 if (CPU_ISSUN4M) 551 raise(0, PIL_TTY); 552 else 553 #endif 554 ienab_bis(IE_ZSSOFT); 555 } 556 return (rval); 557 } 558 559 /* 560 * Similar scheme as for zshard (look at all of them) 561 */ 562 static int 563 zssoft(arg) 564 void *arg; 565 { 566 struct zsc_softc *zsc; 567 int s, unit; 568 569 /* This is not the only ISR on this IPL. */ 570 if (zssoftpending == 0) 571 return (0); 572 573 /* 574 * The soft intr. bit will be set by zshard only if 575 * the variable zssoftpending is zero. The order of 576 * these next two statements prevents our clearing 577 * the soft intr bit just after zshard has set it. 578 */ 579 /* ienab_bic(IE_ZSSOFT); */ 580 zssoftpending = 0; 581 582 /* Make sure we call the tty layer at spltty. */ 583 s = spltty(); 584 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 585 zsc = zs_cd.cd_devs[unit]; 586 if (zsc == NULL) 587 continue; 588 (void)zsc_intr_soft(zsc); 589 } 590 splx(s); 591 return (1); 592 } 593 594 595 /* 596 * Compute the current baud rate given a ZS channel. 597 */ 598 static int 599 zs_get_speed(cs) 600 struct zs_chanstate *cs; 601 { 602 int tconst; 603 604 tconst = zs_read_reg(cs, 12); 605 tconst |= zs_read_reg(cs, 13) << 8; 606 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 607 } 608 609 /* 610 * MD functions for setting the baud rate and control modes. 611 */ 612 int 613 zs_set_speed(cs, bps) 614 struct zs_chanstate *cs; 615 int bps; /* bits per second */ 616 { 617 int tconst, real_bps; 618 619 if (bps == 0) 620 return (0); 621 622 #ifdef DIAGNOSTIC 623 if (cs->cs_brg_clk == 0) 624 panic("zs_set_speed"); 625 #endif 626 627 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 628 if (tconst < 0) 629 return (EINVAL); 630 631 /* Convert back to make sure we can do it. */ 632 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 633 634 /* XXX - Allow some tolerance here? */ 635 if (real_bps != bps) 636 return (EINVAL); 637 638 cs->cs_preg[12] = tconst; 639 cs->cs_preg[13] = tconst >> 8; 640 641 /* Caller will stuff the pending registers. */ 642 return (0); 643 } 644 645 int 646 zs_set_modes(cs, cflag) 647 struct zs_chanstate *cs; 648 int cflag; /* bits per second */ 649 { 650 int s; 651 652 /* 653 * Output hardware flow control on the chip is horrendous: 654 * if carrier detect drops, the receiver is disabled, and if 655 * CTS drops, the transmitter is stoped IN MID CHARACTER! 656 * Therefore, NEVER set the HFC bit, and instead use the 657 * status interrupt to detect CTS changes. 658 */ 659 s = splzs(); 660 cs->cs_rr0_pps = 0; 661 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 662 cs->cs_rr0_dcd = 0; 663 if ((cflag & MDMBUF) == 0) 664 cs->cs_rr0_pps = ZSRR0_DCD; 665 } else 666 cs->cs_rr0_dcd = ZSRR0_DCD; 667 if ((cflag & CRTSCTS) != 0) { 668 cs->cs_wr5_dtr = ZSWR5_DTR; 669 cs->cs_wr5_rts = ZSWR5_RTS; 670 cs->cs_rr0_cts = ZSRR0_CTS; 671 } else if ((cflag & CDTRCTS) != 0) { 672 cs->cs_wr5_dtr = 0; 673 cs->cs_wr5_rts = ZSWR5_DTR; 674 cs->cs_rr0_cts = ZSRR0_CTS; 675 } else if ((cflag & MDMBUF) != 0) { 676 cs->cs_wr5_dtr = 0; 677 cs->cs_wr5_rts = ZSWR5_DTR; 678 cs->cs_rr0_cts = ZSRR0_DCD; 679 } else { 680 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 681 cs->cs_wr5_rts = 0; 682 cs->cs_rr0_cts = 0; 683 } 684 splx(s); 685 686 /* Caller will stuff the pending registers. */ 687 return (0); 688 } 689 690 691 /* 692 * Read or write the chip with suitable delays. 693 */ 694 695 u_char 696 zs_read_reg(cs, reg) 697 struct zs_chanstate *cs; 698 u_char reg; 699 { 700 u_char val; 701 702 *cs->cs_reg_csr = reg; 703 ZS_DELAY(); 704 val = *cs->cs_reg_csr; 705 ZS_DELAY(); 706 return (val); 707 } 708 709 void 710 zs_write_reg(cs, reg, val) 711 struct zs_chanstate *cs; 712 u_char reg, val; 713 { 714 *cs->cs_reg_csr = reg; 715 ZS_DELAY(); 716 *cs->cs_reg_csr = val; 717 ZS_DELAY(); 718 } 719 720 u_char 721 zs_read_csr(cs) 722 struct zs_chanstate *cs; 723 { 724 u_char val; 725 726 val = *cs->cs_reg_csr; 727 ZS_DELAY(); 728 return (val); 729 } 730 731 void 732 zs_write_csr(cs, val) 733 struct zs_chanstate *cs; 734 u_char val; 735 { 736 *cs->cs_reg_csr = val; 737 ZS_DELAY(); 738 } 739 740 u_char 741 zs_read_data(cs) 742 struct zs_chanstate *cs; 743 { 744 u_char val; 745 746 val = *cs->cs_reg_data; 747 ZS_DELAY(); 748 return (val); 749 } 750 751 void zs_write_data(cs, val) 752 struct zs_chanstate *cs; 753 u_char val; 754 { 755 *cs->cs_reg_data = val; 756 ZS_DELAY(); 757 } 758 759 /**************************************************************** 760 * Console support functions (Sun specific!) 761 * Note: this code is allowed to know about the layout of 762 * the chip registers, and uses that to keep things simple. 763 * XXX - I think I like the mvme167 code better. -gwr 764 ****************************************************************/ 765 766 /* 767 * Handle user request to enter kernel debugger. 768 */ 769 void 770 zs_abort(cs) 771 struct zs_chanstate *cs; 772 { 773 struct zschan *zc = zs_conschan_get; 774 int rr0; 775 776 /* Wait for end of break to avoid PROM abort. */ 777 /* XXX - Limit the wait? */ 778 do { 779 rr0 = zc->zc_csr; 780 ZS_DELAY(); 781 } while (rr0 & ZSRR0_BREAK); 782 783 #if defined(KGDB) 784 zskgdb(cs); 785 #elif defined(DDB) 786 Debugger(); 787 #else 788 printf("stopping on keyboard abort\n"); 789 callrom(); 790 #endif 791 } 792 793 static int zs_getc __P((void *arg)); 794 static void zs_putc __P((void *arg, int c)); 795 796 /* 797 * Polled input char. 798 */ 799 int 800 zs_getc(arg) 801 void *arg; 802 { 803 struct zschan *zc = arg; 804 int s, c, rr0; 805 806 s = splhigh(); 807 /* Wait for a character to arrive. */ 808 do { 809 rr0 = zc->zc_csr; 810 ZS_DELAY(); 811 } while ((rr0 & ZSRR0_RX_READY) == 0); 812 813 c = zc->zc_data; 814 ZS_DELAY(); 815 splx(s); 816 817 /* 818 * This is used by the kd driver to read scan codes, 819 * so don't translate '\r' ==> '\n' here... 820 */ 821 return (c); 822 } 823 824 /* 825 * Polled output char. 826 */ 827 void 828 zs_putc(arg, c) 829 void *arg; 830 int c; 831 { 832 struct zschan *zc = arg; 833 int s, rr0; 834 835 s = splhigh(); 836 837 /* Wait for transmitter to become ready. */ 838 do { 839 rr0 = zc->zc_csr; 840 ZS_DELAY(); 841 } while ((rr0 & ZSRR0_TX_READY) == 0); 842 843 /* 844 * Send the next character. 845 * Now you'd think that this could be followed by a ZS_DELAY() 846 * just like all the other chip accesses, but it turns out that 847 * the `transmit-ready' interrupt isn't de-asserted until 848 * some period of time after the register write completes 849 * (more than a couple instructions). So to avoid stray 850 * interrupts we put in the 2us delay regardless of cpu model. 851 */ 852 zc->zc_data = c; 853 delay(2); 854 855 splx(s); 856 } 857 858 /*****************************************************************/ 859 /* 860 * Polled console input putchar. 861 */ 862 int 863 zscngetc(dev) 864 dev_t dev; 865 { 866 return (zs_getc(zs_conschan_get)); 867 } 868 869 /* 870 * Polled console output putchar. 871 */ 872 void 873 zscnputc(dev, c) 874 dev_t dev; 875 int c; 876 { 877 zs_putc(zs_conschan_put, c); 878 } 879 880 void 881 zscnpollc(dev, on) 882 dev_t dev; 883 int on; 884 { 885 /* No action needed */ 886 } 887 888 int 889 zs_console_flags(promunit, node, channel) 890 int promunit; 891 int node; 892 int channel; 893 { 894 int cookie, flags = 0; 895 896 switch (prom_version()) { 897 case PROM_OLDMON: 898 case PROM_OBP_V0: 899 /* 900 * Use `promunit' and `channel' to derive the PROM 901 * stdio handles that correspond to this device. 902 */ 903 if (promunit == 0) 904 cookie = PROMDEV_TTYA + channel; 905 else if (promunit == 1 && channel == 0) 906 cookie = PROMDEV_KBD; 907 else 908 cookie = -1; 909 910 if (cookie == prom_stdin()) 911 flags |= ZS_HWFLAG_CONSOLE_INPUT; 912 913 /* 914 * Prevent the keyboard from matching the output device 915 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 916 */ 917 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 918 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 919 920 break; 921 922 case PROM_OBP_V2: 923 case PROM_OBP_V3: 924 case PROM_OPENFIRM: 925 926 /* 927 * Match the nodes and device arguments prepared by 928 * consinit() against our device node and channel. 929 * (The device argument is the part of the OBP path 930 * following the colon, as in `/obio/zs@0,100000:a') 931 */ 932 933 /* Default to channel 0 if there are no explicit prom args */ 934 cookie = 0; 935 936 if (node == prom_stdin_node) { 937 if (prom_stdin_args[0] != '\0') 938 /* Translate (a,b) -> (0,1) */ 939 cookie = prom_stdin_args[0] - 'a'; 940 941 if (channel == cookie) 942 flags |= ZS_HWFLAG_CONSOLE_INPUT; 943 } 944 945 if (node == prom_stdout_node) { 946 if (prom_stdout_args[0] != '\0') 947 /* Translate (a,b) -> (0,1) */ 948 cookie = prom_stdout_args[0] - 'a'; 949 950 if (channel == cookie) 951 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 952 } 953 954 break; 955 956 default: 957 break; 958 } 959 960 return (flags); 961 } 962 963 /* 964 * Power management hooks for zsopen() and zsclose(). 965 * We use them to power on/off the ports, if necessary. 966 */ 967 int 968 zs_enable(cs) 969 struct zs_chanstate *cs; 970 { 971 auxiotwoserialendis (ZS_ENABLE); 972 cs->enabled = 1; 973 return(0); 974 } 975 976 void 977 zs_disable(cs) 978 struct zs_chanstate *cs; 979 { 980 auxiotwoserialendis (ZS_DISABLE); 981 cs->enabled = 0; 982 } 983