1 /* $NetBSD: zs.c,v 1.80 2000/07/09 20:57:48 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/bsd_openprom.h> 62 #include <machine/autoconf.h> 63 #include <machine/intr.h> 64 #include <machine/conf.h> 65 #include <machine/eeprom.h> 66 #include <machine/psl.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/cons.h> 70 #include <dev/ic/z8530reg.h> 71 72 #include <sparc/sparc/vaddrs.h> 73 #include <sparc/sparc/auxreg.h> 74 #include <sparc/sparc/auxiotwo.h> 75 #include <sparc/dev/cons.h> 76 77 #include "kbd.h" /* NKBD */ 78 #include "zs.h" /* NZS */ 79 80 /* Make life easier for the initialized arrays here. */ 81 #if NZS < 3 82 #undef NZS 83 #define NZS 3 84 #endif 85 86 /* 87 * Some warts needed by z8530tty.c - 88 * The default parity REALLY needs to be the same as the PROM uses, 89 * or you can not see messages done with printf during boot-up... 90 */ 91 int zs_def_cflag = (CREAD | CS8 | HUPCL); 92 int zs_major = 12; 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 /* 100 * Select software interrupt bit based on TTY ipl. 101 */ 102 #if PIL_TTY == 1 103 # define IE_ZSSOFT IE_L1 104 #elif PIL_TTY == 4 105 # define IE_ZSSOFT IE_L4 106 #elif PIL_TTY == 6 107 # define IE_ZSSOFT IE_L6 108 #else 109 # error "no suitable software interrupt bit" 110 #endif 111 112 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zschan { 116 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 117 u_char zc_xxx0; 118 volatile u_char zc_data; /* data */ 119 u_char zc_xxx1; 120 }; 121 struct zsdevice { 122 /* Yes, they are backwards. */ 123 struct zschan zs_chan_b; 124 struct zschan zs_chan_a; 125 }; 126 127 /* ZS channel used as the console device (if any) */ 128 void *zs_conschan_get, *zs_conschan_put; 129 130 static u_char zs_init_reg[16] = { 131 0, /* 0: CMD (reset, etc.) */ 132 0, /* 1: No interrupts yet. */ 133 0, /* 2: IVECT */ 134 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 135 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 136 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 137 0, /* 6: TXSYNC/SYNCLO */ 138 0, /* 7: RXSYNC/SYNCHI */ 139 0, /* 8: alias for data port */ 140 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 141 0, /*10: Misc. TX/RX control bits */ 142 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 143 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 144 0, /*13: BAUDHI (default=9600) */ 145 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 146 ZSWR15_BREAK_IE, 147 }; 148 149 /* Console ops */ 150 static int zscngetc __P((dev_t)); 151 static void zscnputc __P((dev_t, int)); 152 static void zscnpollc __P((dev_t, int)); 153 154 struct consdev zs_consdev = { 155 NULL, 156 NULL, 157 zscngetc, 158 zscnputc, 159 zscnpollc, 160 NULL, 161 }; 162 163 164 /**************************************************************** 165 * Autoconfig 166 ****************************************************************/ 167 168 /* Definition of the driver for autoconfig. */ 169 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 170 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 171 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 172 static void zs_attach_obio __P((struct device *, struct device *, void *)); 173 174 175 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 176 static int zs_print __P((void *, const char *name)); 177 178 struct cfattach zs_mainbus_ca = { 179 sizeof(struct zsc_softc), zs_match_mainbus, zs_attach_mainbus 180 }; 181 182 struct cfattach zs_obio_ca = { 183 sizeof(struct zsc_softc), zs_match_obio, zs_attach_obio 184 }; 185 186 extern struct cfdriver zs_cd; 187 188 /* Interrupt handlers. */ 189 static int zshard __P((void *)); 190 static int zssoft __P((void *)); 191 192 static int zs_get_speed __P((struct zs_chanstate *)); 193 194 /* Console device support */ 195 static int zs_console_flags __P((int, int, int)); 196 197 /* Power management hooks */ 198 int zs_enable __P((struct zs_chanstate *)); 199 void zs_disable __P((struct zs_chanstate *)); 200 201 202 /* 203 * Is the zs chip present? 204 */ 205 static int 206 zs_match_mainbus(parent, cf, aux) 207 struct device *parent; 208 struct cfdata *cf; 209 void *aux; 210 { 211 struct mainbus_attach_args *ma = aux; 212 213 if (strcmp(cf->cf_driver->cd_name, ma->ma_name) != 0) 214 return (0); 215 216 return (1); 217 } 218 219 static int 220 zs_match_obio(parent, cf, aux) 221 struct device *parent; 222 struct cfdata *cf; 223 void *aux; 224 { 225 union obio_attach_args *uoba = aux; 226 struct obio4_attach_args *oba; 227 228 if (uoba->uoba_isobio4 == 0) { 229 struct sbus_attach_args *sa = &uoba->uoba_sbus; 230 231 if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0) 232 return (0); 233 234 return (1); 235 } 236 237 oba = &uoba->uoba_oba4; 238 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 239 1, 0, 0, NULL, NULL)); 240 } 241 242 static void 243 zs_attach_mainbus(parent, self, aux) 244 struct device *parent; 245 struct device *self; 246 void *aux; 247 { 248 struct zsc_softc *zsc = (void *) self; 249 struct mainbus_attach_args *ma = aux; 250 251 zsc->zsc_bustag = ma->ma_bustag; 252 zsc->zsc_dmatag = ma->ma_dmatag; 253 zsc->zsc_promunit = getpropint(ma->ma_node, "slave", -2); 254 zsc->zsc_node = ma->ma_node; 255 256 /* 257 * For machines with zs on mainbus (all sun4c models), we expect 258 * the device registers to be mapped by the PROM. 259 */ 260 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 261 } 262 263 static void 264 zs_attach_obio(parent, self, aux) 265 struct device *parent; 266 struct device *self; 267 void *aux; 268 { 269 struct zsc_softc *zsc = (void *) self; 270 union obio_attach_args *uoba = aux; 271 272 if (uoba->uoba_isobio4 == 0) { 273 struct sbus_attach_args *sa = &uoba->uoba_sbus; 274 void *va; 275 struct zs_chanstate *cs; 276 int channel; 277 278 if (sa->sa_nintr == 0) { 279 printf(" no interrupt lines\n"); 280 return; 281 } 282 283 /* 284 * Some sun4m models (Javastations) may not map the zs device. 285 */ 286 if (sa->sa_npromvaddrs > 0) 287 va = (void *)sa->sa_promvaddr; 288 else { 289 bus_space_handle_t bh; 290 291 if (sbus_bus_map(sa->sa_bustag, 292 sa->sa_slot, 293 sa->sa_offset, 294 sa->sa_size, 295 BUS_SPACE_MAP_LINEAR, 296 0, &bh) != 0) { 297 printf(" cannot map zs registers\n"); 298 return; 299 } 300 va = (void *)bh; 301 } 302 303 /* 304 * Check if power state can be set, e.g. Tadpole 3GX 305 */ 306 if (getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 307 { 308 printf (" powered via auxio2"); 309 for (channel = 0; channel < 2; channel++) { 310 cs = &zsc->zsc_cs_store[channel]; 311 cs->enable = zs_enable; 312 cs->disable = zs_disable; 313 } 314 } 315 316 zsc->zsc_bustag = sa->sa_bustag; 317 zsc->zsc_dmatag = sa->sa_dmatag; 318 zsc->zsc_promunit = getpropint(sa->sa_node, "slave", -2); 319 zsc->zsc_node = sa->sa_node; 320 zs_attach(zsc, va, sa->sa_pri); 321 } else { 322 struct obio4_attach_args *oba = &uoba->uoba_oba4; 323 bus_space_handle_t bh; 324 bus_addr_t paddr = oba->oba_paddr; 325 326 /* 327 * As for zs on mainbus, we require a PROM mapping. 328 */ 329 if (bus_space_map(oba->oba_bustag, 330 paddr, 331 sizeof(struct zsdevice), 332 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 333 &bh) != 0) { 334 printf(" cannot map zs registers\n"); 335 return; 336 } 337 zsc->zsc_bustag = oba->oba_bustag; 338 zsc->zsc_dmatag = oba->oba_dmatag; 339 /* Find prom unit by physical address */ 340 zsc->zsc_promunit = 341 (paddr == 0xf1000000) ? 0 : 342 (paddr == 0xf0000000) ? 1 : 343 (paddr == 0xe0000000) ? 2 : -2; 344 345 zs_attach(zsc, (void *)bh, oba->oba_pri); 346 } 347 } 348 /* 349 * Attach a found zs. 350 * 351 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 352 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 353 */ 354 static void 355 zs_attach(zsc, zsd, pri) 356 struct zsc_softc *zsc; 357 struct zsdevice *zsd; 358 int pri; 359 { 360 struct zsc_attach_args zsc_args; 361 struct zs_chanstate *cs; 362 int s, channel; 363 static int didintr, prevpri; 364 365 if (zsd == NULL) { 366 printf("configuration incomplete\n"); 367 return; 368 } 369 370 printf(" softpri %d\n", PIL_TTY); 371 372 /* 373 * Initialize software state for each channel. 374 */ 375 for (channel = 0; channel < 2; channel++) { 376 struct zschan *zc; 377 378 zsc_args.channel = channel; 379 cs = &zsc->zsc_cs_store[channel]; 380 zsc->zsc_cs[channel] = cs; 381 382 cs->cs_channel = channel; 383 cs->cs_private = NULL; 384 cs->cs_ops = &zsops_null; 385 cs->cs_brg_clk = PCLK / 16; 386 387 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 388 389 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 390 zsc->zsc_node, 391 channel); 392 393 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 394 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 395 zsc_args.consdev = &zs_consdev; 396 } 397 398 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 399 zs_conschan_get = zc; 400 } 401 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 402 zs_conschan_put = zc; 403 } 404 /* Childs need to set cn_dev, etc */ 405 406 cs->cs_reg_csr = &zc->zc_csr; 407 cs->cs_reg_data = &zc->zc_data; 408 409 bcopy(zs_init_reg, cs->cs_creg, 16); 410 bcopy(zs_init_reg, cs->cs_preg, 16); 411 412 /* XXX: Consult PROM properties for this?! */ 413 cs->cs_defspeed = zs_get_speed(cs); 414 cs->cs_defcflag = zs_def_cflag; 415 416 /* Make these correspond to cs_defcflag (-crtscts) */ 417 cs->cs_rr0_dcd = ZSRR0_DCD; 418 cs->cs_rr0_cts = 0; 419 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 420 cs->cs_wr5_rts = 0; 421 422 /* 423 * Clear the master interrupt enable. 424 * The INTENA is common to both channels, 425 * so just do it on the A channel. 426 */ 427 if (channel == 0) { 428 zs_write_reg(cs, 9, 0); 429 } 430 431 /* 432 * Look for a child driver for this channel. 433 * The child attach will setup the hardware. 434 */ 435 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 436 /* No sub-driver. Just reset it. */ 437 u_char reset = (channel == 0) ? 438 ZSWR9_A_RESET : ZSWR9_B_RESET; 439 s = splzs(); 440 zs_write_reg(cs, 9, reset); 441 splx(s); 442 } 443 } 444 445 /* 446 * Now safe to install interrupt handlers. Note the arguments 447 * to the interrupt handlers aren't used. Note, we only do this 448 * once since both SCCs interrupt at the same level and vector. 449 */ 450 if (!didintr) { 451 didintr = 1; 452 prevpri = pri; 453 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, 454 zshard, NULL); 455 bus_intr_establish(zsc->zsc_bustag, PIL_TTY, 456 IPL_SOFTSERIAL, 457 BUS_INTR_ESTABLISH_SOFTINTR, 458 zssoft, NULL); 459 } else if (pri != prevpri) 460 panic("broken zs interrupt scheme"); 461 462 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 463 zsc->zsc_dev.dv_xname, "intr"); 464 465 /* 466 * Set the master interrupt enable and interrupt vector. 467 * (common to both channels, do it on A) 468 */ 469 cs = zsc->zsc_cs[0]; 470 s = splhigh(); 471 /* interrupt vector */ 472 zs_write_reg(cs, 2, zs_init_reg[2]); 473 /* master interrupt control (enable) */ 474 zs_write_reg(cs, 9, zs_init_reg[9]); 475 splx(s); 476 477 #if 0 478 /* 479 * XXX: L1A hack - We would like to be able to break into 480 * the debugger during the rest of autoconfiguration, so 481 * lower interrupts just enough to let zs interrupts in. 482 * This is done after both zs devices are attached. 483 */ 484 if (zsc->zsc_promunit == 1) { 485 printf("zs1: enabling zs interrupts\n"); 486 (void)splfd(); /* XXX: splzs - 1 */ 487 } 488 #endif 489 } 490 491 static int 492 zs_print(aux, name) 493 void *aux; 494 const char *name; 495 { 496 struct zsc_attach_args *args = aux; 497 498 if (name != NULL) 499 printf("%s: ", name); 500 501 if (args->channel != -1) 502 printf(" channel %d", args->channel); 503 504 return (UNCONF); 505 } 506 507 static volatile int zssoftpending; 508 509 /* 510 * Our ZS chips all share a common, autovectored interrupt, 511 * so we have to look at all of them on each interrupt. 512 */ 513 static int 514 zshard(arg) 515 void *arg; 516 { 517 struct zsc_softc *zsc; 518 int unit, rr3, rval, softreq; 519 520 rval = softreq = 0; 521 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 522 struct zs_chanstate *cs; 523 524 zsc = zs_cd.cd_devs[unit]; 525 if (zsc == NULL) 526 continue; 527 rr3 = zsc_intr_hard(zsc); 528 /* Count up the interrupts. */ 529 if (rr3) { 530 rval |= rr3; 531 zsc->zsc_intrcnt.ev_count++; 532 } 533 if ((cs = zsc->zsc_cs[0]) != NULL) 534 softreq |= cs->cs_softreq; 535 if ((cs = zsc->zsc_cs[1]) != NULL) 536 softreq |= cs->cs_softreq; 537 } 538 539 /* We are at splzs here, so no need to lock. */ 540 if (softreq && (zssoftpending == 0)) { 541 zssoftpending = IE_ZSSOFT; 542 #if defined(SUN4M) 543 if (CPU_ISSUN4M) 544 raise(0, PIL_TTY); 545 else 546 #endif 547 ienab_bis(IE_ZSSOFT); 548 } 549 return (rval); 550 } 551 552 /* 553 * Similar scheme as for zshard (look at all of them) 554 */ 555 static int 556 zssoft(arg) 557 void *arg; 558 { 559 struct zsc_softc *zsc; 560 int s, unit; 561 562 /* This is not the only ISR on this IPL. */ 563 if (zssoftpending == 0) 564 return (0); 565 566 /* 567 * The soft intr. bit will be set by zshard only if 568 * the variable zssoftpending is zero. The order of 569 * these next two statements prevents our clearing 570 * the soft intr bit just after zshard has set it. 571 */ 572 /* ienab_bic(IE_ZSSOFT); */ 573 zssoftpending = 0; 574 575 /* Make sure we call the tty layer at spltty. */ 576 s = spltty(); 577 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 578 zsc = zs_cd.cd_devs[unit]; 579 if (zsc == NULL) 580 continue; 581 (void)zsc_intr_soft(zsc); 582 } 583 splx(s); 584 return (1); 585 } 586 587 588 /* 589 * Compute the current baud rate given a ZS channel. 590 */ 591 static int 592 zs_get_speed(cs) 593 struct zs_chanstate *cs; 594 { 595 int tconst; 596 597 tconst = zs_read_reg(cs, 12); 598 tconst |= zs_read_reg(cs, 13) << 8; 599 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 600 } 601 602 /* 603 * MD functions for setting the baud rate and control modes. 604 */ 605 int 606 zs_set_speed(cs, bps) 607 struct zs_chanstate *cs; 608 int bps; /* bits per second */ 609 { 610 int tconst, real_bps; 611 612 if (bps == 0) 613 return (0); 614 615 #ifdef DIAGNOSTIC 616 if (cs->cs_brg_clk == 0) 617 panic("zs_set_speed"); 618 #endif 619 620 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 621 if (tconst < 0) 622 return (EINVAL); 623 624 /* Convert back to make sure we can do it. */ 625 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 626 627 /* XXX - Allow some tolerance here? */ 628 if (real_bps != bps) 629 return (EINVAL); 630 631 cs->cs_preg[12] = tconst; 632 cs->cs_preg[13] = tconst >> 8; 633 634 /* Caller will stuff the pending registers. */ 635 return (0); 636 } 637 638 int 639 zs_set_modes(cs, cflag) 640 struct zs_chanstate *cs; 641 int cflag; /* bits per second */ 642 { 643 int s; 644 645 /* 646 * Output hardware flow control on the chip is horrendous: 647 * if carrier detect drops, the receiver is disabled, and if 648 * CTS drops, the transmitter is stoped IN MID CHARACTER! 649 * Therefore, NEVER set the HFC bit, and instead use the 650 * status interrupt to detect CTS changes. 651 */ 652 s = splzs(); 653 cs->cs_rr0_pps = 0; 654 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 655 cs->cs_rr0_dcd = 0; 656 if ((cflag & MDMBUF) == 0) 657 cs->cs_rr0_pps = ZSRR0_DCD; 658 } else 659 cs->cs_rr0_dcd = ZSRR0_DCD; 660 if ((cflag & CRTSCTS) != 0) { 661 cs->cs_wr5_dtr = ZSWR5_DTR; 662 cs->cs_wr5_rts = ZSWR5_RTS; 663 cs->cs_rr0_cts = ZSRR0_CTS; 664 } else if ((cflag & CDTRCTS) != 0) { 665 cs->cs_wr5_dtr = 0; 666 cs->cs_wr5_rts = ZSWR5_DTR; 667 cs->cs_rr0_cts = ZSRR0_CTS; 668 } else if ((cflag & MDMBUF) != 0) { 669 cs->cs_wr5_dtr = 0; 670 cs->cs_wr5_rts = ZSWR5_DTR; 671 cs->cs_rr0_cts = ZSRR0_DCD; 672 } else { 673 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 674 cs->cs_wr5_rts = 0; 675 cs->cs_rr0_cts = 0; 676 } 677 splx(s); 678 679 /* Caller will stuff the pending registers. */ 680 return (0); 681 } 682 683 684 /* 685 * Read or write the chip with suitable delays. 686 */ 687 688 u_char 689 zs_read_reg(cs, reg) 690 struct zs_chanstate *cs; 691 u_char reg; 692 { 693 u_char val; 694 695 *cs->cs_reg_csr = reg; 696 ZS_DELAY(); 697 val = *cs->cs_reg_csr; 698 ZS_DELAY(); 699 return (val); 700 } 701 702 void 703 zs_write_reg(cs, reg, val) 704 struct zs_chanstate *cs; 705 u_char reg, val; 706 { 707 *cs->cs_reg_csr = reg; 708 ZS_DELAY(); 709 *cs->cs_reg_csr = val; 710 ZS_DELAY(); 711 } 712 713 u_char 714 zs_read_csr(cs) 715 struct zs_chanstate *cs; 716 { 717 u_char val; 718 719 val = *cs->cs_reg_csr; 720 ZS_DELAY(); 721 return (val); 722 } 723 724 void 725 zs_write_csr(cs, val) 726 struct zs_chanstate *cs; 727 u_char val; 728 { 729 *cs->cs_reg_csr = val; 730 ZS_DELAY(); 731 } 732 733 u_char 734 zs_read_data(cs) 735 struct zs_chanstate *cs; 736 { 737 u_char val; 738 739 val = *cs->cs_reg_data; 740 ZS_DELAY(); 741 return (val); 742 } 743 744 void zs_write_data(cs, val) 745 struct zs_chanstate *cs; 746 u_char val; 747 { 748 *cs->cs_reg_data = val; 749 ZS_DELAY(); 750 } 751 752 /**************************************************************** 753 * Console support functions (Sun specific!) 754 * Note: this code is allowed to know about the layout of 755 * the chip registers, and uses that to keep things simple. 756 * XXX - I think I like the mvme167 code better. -gwr 757 ****************************************************************/ 758 759 /* 760 * Handle user request to enter kernel debugger. 761 */ 762 void 763 zs_abort(cs) 764 struct zs_chanstate *cs; 765 { 766 struct zschan *zc = zs_conschan_get; 767 int rr0; 768 769 /* Wait for end of break to avoid PROM abort. */ 770 /* XXX - Limit the wait? */ 771 do { 772 rr0 = zc->zc_csr; 773 ZS_DELAY(); 774 } while (rr0 & ZSRR0_BREAK); 775 776 #if defined(KGDB) 777 zskgdb(cs); 778 #elif defined(DDB) 779 Debugger(); 780 #else 781 printf("stopping on keyboard abort\n"); 782 callrom(); 783 #endif 784 } 785 786 static int zs_getc __P((void *arg)); 787 static void zs_putc __P((void *arg, int c)); 788 789 /* 790 * Polled input char. 791 */ 792 int 793 zs_getc(arg) 794 void *arg; 795 { 796 struct zschan *zc = arg; 797 int s, c, rr0; 798 799 s = splhigh(); 800 /* Wait for a character to arrive. */ 801 do { 802 rr0 = zc->zc_csr; 803 ZS_DELAY(); 804 } while ((rr0 & ZSRR0_RX_READY) == 0); 805 806 c = zc->zc_data; 807 ZS_DELAY(); 808 splx(s); 809 810 /* 811 * This is used by the kd driver to read scan codes, 812 * so don't translate '\r' ==> '\n' here... 813 */ 814 return (c); 815 } 816 817 /* 818 * Polled output char. 819 */ 820 void 821 zs_putc(arg, c) 822 void *arg; 823 int c; 824 { 825 struct zschan *zc = arg; 826 int s, rr0; 827 828 s = splhigh(); 829 830 /* Wait for transmitter to become ready. */ 831 do { 832 rr0 = zc->zc_csr; 833 ZS_DELAY(); 834 } while ((rr0 & ZSRR0_TX_READY) == 0); 835 836 /* 837 * Send the next character. 838 * Now you'd think that this could be followed by a ZS_DELAY() 839 * just like all the other chip accesses, but it turns out that 840 * the `transmit-ready' interrupt isn't de-asserted until 841 * some period of time after the register write completes 842 * (more than a couple instructions). So to avoid stray 843 * interrupts we put in the 2us delay regardless of cpu model. 844 */ 845 zc->zc_data = c; 846 delay(2); 847 848 splx(s); 849 } 850 851 /*****************************************************************/ 852 /* 853 * Polled console input putchar. 854 */ 855 int 856 zscngetc(dev) 857 dev_t dev; 858 { 859 return (zs_getc(zs_conschan_get)); 860 } 861 862 /* 863 * Polled console output putchar. 864 */ 865 void 866 zscnputc(dev, c) 867 dev_t dev; 868 int c; 869 { 870 zs_putc(zs_conschan_put, c); 871 } 872 873 void 874 zscnpollc(dev, on) 875 dev_t dev; 876 int on; 877 { 878 /* No action needed */ 879 } 880 881 int 882 zs_console_flags(promunit, node, channel) 883 int promunit; 884 int node; 885 int channel; 886 { 887 int cookie, flags = 0; 888 889 switch (prom_version()) { 890 case PROM_OLDMON: 891 case PROM_OBP_V0: 892 /* 893 * Use `promunit' and `channel' to derive the PROM 894 * stdio handles that correspond to this device. 895 */ 896 if (promunit == 0) 897 cookie = PROMDEV_TTYA + channel; 898 else if (promunit == 1 && channel == 0) 899 cookie = PROMDEV_KBD; 900 else 901 cookie = -1; 902 903 if (cookie == prom_stdin()) 904 flags |= ZS_HWFLAG_CONSOLE_INPUT; 905 906 /* 907 * Prevent the keyboard from matching the output device 908 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 909 */ 910 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 911 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 912 913 break; 914 915 case PROM_OBP_V2: 916 case PROM_OBP_V3: 917 case PROM_OPENFIRM: 918 919 /* 920 * Match the nodes and device arguments prepared by 921 * consinit() against our device node and channel. 922 * (The device argument is the part of the OBP path 923 * following the colon, as in `/obio/zs@0,100000:a') 924 */ 925 926 /* Default to channel 0 if there are no explicit prom args */ 927 cookie = 0; 928 929 if (node == prom_stdin_node) { 930 if (prom_stdin_args[0] != '\0') 931 /* Translate (a,b) -> (0,1) */ 932 cookie = prom_stdin_args[0] - 'a'; 933 934 if (channel == cookie) 935 flags |= ZS_HWFLAG_CONSOLE_INPUT; 936 } 937 938 if (node == prom_stdout_node) { 939 if (prom_stdout_args[0] != '\0') 940 /* Translate (a,b) -> (0,1) */ 941 cookie = prom_stdout_args[0] - 'a'; 942 943 if (channel == cookie) 944 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 945 } 946 947 break; 948 949 default: 950 break; 951 } 952 953 return (flags); 954 } 955 956 /* 957 * Power management hooks for zsopen() and zsclose(). 958 * We use them to power on/off the ports, if necessary. 959 */ 960 int 961 zs_enable(cs) 962 struct zs_chanstate *cs; 963 { 964 auxiotwoserialendis (ZS_ENABLE); 965 cs->enabled = 1; 966 return(0); 967 } 968 969 void 970 zs_disable(cs) 971 struct zs_chanstate *cs; 972 { 973 auxiotwoserialendis (ZS_DISABLE); 974 cs->enabled = 0; 975 } 976