1 /* $NetBSD: zs.c,v 1.79 2000/06/04 19:15:03 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/bsd_openprom.h> 62 #include <machine/autoconf.h> 63 #include <machine/conf.h> 64 #include <machine/cpu.h> 65 #include <machine/eeprom.h> 66 #include <machine/psl.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/cons.h> 70 #include <dev/ic/z8530reg.h> 71 72 #include <sparc/sparc/vaddrs.h> 73 #include <sparc/sparc/auxreg.h> 74 #include <sparc/sparc/auxiotwo.h> 75 #include <sparc/dev/cons.h> 76 77 #include "kbd.h" /* NKBD */ 78 #include "zs.h" /* NZS */ 79 80 /* Make life easier for the initialized arrays here. */ 81 #if NZS < 3 82 #undef NZS 83 #define NZS 3 84 #endif 85 86 /* 87 * Some warts needed by z8530tty.c - 88 * The default parity REALLY needs to be the same as the PROM uses, 89 * or you can not see messages done with printf during boot-up... 90 */ 91 int zs_def_cflag = (CREAD | CS8 | HUPCL); 92 int zs_major = 12; 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 /* 100 * Select software interrupt bit based on TTY ipl. 101 */ 102 #if PIL_TTY == 1 103 # define IE_ZSSOFT IE_L1 104 #elif PIL_TTY == 4 105 # define IE_ZSSOFT IE_L4 106 #elif PIL_TTY == 6 107 # define IE_ZSSOFT IE_L6 108 #else 109 # error "no suitable software interrupt bit" 110 #endif 111 112 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zschan { 116 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 117 u_char zc_xxx0; 118 volatile u_char zc_data; /* data */ 119 u_char zc_xxx1; 120 }; 121 struct zsdevice { 122 /* Yes, they are backwards. */ 123 struct zschan zs_chan_b; 124 struct zschan zs_chan_a; 125 }; 126 127 /* ZS channel used as the console device (if any) */ 128 void *zs_conschan_get, *zs_conschan_put; 129 130 static u_char zs_init_reg[16] = { 131 0, /* 0: CMD (reset, etc.) */ 132 0, /* 1: No interrupts yet. */ 133 0, /* 2: IVECT */ 134 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 135 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 136 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 137 0, /* 6: TXSYNC/SYNCLO */ 138 0, /* 7: RXSYNC/SYNCHI */ 139 0, /* 8: alias for data port */ 140 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 141 0, /*10: Misc. TX/RX control bits */ 142 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 143 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 144 0, /*13: BAUDHI (default=9600) */ 145 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 146 ZSWR15_BREAK_IE, 147 }; 148 149 /* Console ops */ 150 static int zscngetc __P((dev_t)); 151 static void zscnputc __P((dev_t, int)); 152 static void zscnpollc __P((dev_t, int)); 153 154 struct consdev zs_consdev = { 155 NULL, 156 NULL, 157 zscngetc, 158 zscnputc, 159 zscnpollc, 160 NULL, 161 }; 162 163 164 /**************************************************************** 165 * Autoconfig 166 ****************************************************************/ 167 168 /* Definition of the driver for autoconfig. */ 169 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 170 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 171 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 172 static void zs_attach_obio __P((struct device *, struct device *, void *)); 173 174 175 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 176 static int zs_print __P((void *, const char *name)); 177 178 struct cfattach zs_mainbus_ca = { 179 sizeof(struct zsc_softc), zs_match_mainbus, zs_attach_mainbus 180 }; 181 182 struct cfattach zs_obio_ca = { 183 sizeof(struct zsc_softc), zs_match_obio, zs_attach_obio 184 }; 185 186 extern struct cfdriver zs_cd; 187 188 /* Interrupt handlers. */ 189 static int zshard __P((void *)); 190 static int zssoft __P((void *)); 191 static struct intrhand levelsoft = { zssoft }; 192 193 static int zs_get_speed __P((struct zs_chanstate *)); 194 195 /* Console device support */ 196 static int zs_console_flags __P((int, int, int)); 197 198 /* Power management hooks */ 199 int zs_enable __P((struct zs_chanstate *)); 200 void zs_disable __P((struct zs_chanstate *)); 201 202 203 /* 204 * Is the zs chip present? 205 */ 206 static int 207 zs_match_mainbus(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct mainbus_attach_args *ma = aux; 213 214 if (strcmp(cf->cf_driver->cd_name, ma->ma_name) != 0) 215 return (0); 216 217 return (1); 218 } 219 220 static int 221 zs_match_obio(parent, cf, aux) 222 struct device *parent; 223 struct cfdata *cf; 224 void *aux; 225 { 226 union obio_attach_args *uoba = aux; 227 struct obio4_attach_args *oba; 228 229 if (uoba->uoba_isobio4 == 0) { 230 struct sbus_attach_args *sa = &uoba->uoba_sbus; 231 232 if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0) 233 return (0); 234 235 return (1); 236 } 237 238 oba = &uoba->uoba_oba4; 239 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 240 1, 0, 0, NULL, NULL)); 241 } 242 243 static void 244 zs_attach_mainbus(parent, self, aux) 245 struct device *parent; 246 struct device *self; 247 void *aux; 248 { 249 struct zsc_softc *zsc = (void *) self; 250 struct mainbus_attach_args *ma = aux; 251 252 zsc->zsc_bustag = ma->ma_bustag; 253 zsc->zsc_dmatag = ma->ma_dmatag; 254 zsc->zsc_promunit = getpropint(ma->ma_node, "slave", -2); 255 zsc->zsc_node = ma->ma_node; 256 257 /* 258 * For machines with zs on mainbus (all sun4c models), we expect 259 * the device registers to be mapped by the PROM. 260 */ 261 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 262 } 263 264 static void 265 zs_attach_obio(parent, self, aux) 266 struct device *parent; 267 struct device *self; 268 void *aux; 269 { 270 struct zsc_softc *zsc = (void *) self; 271 union obio_attach_args *uoba = aux; 272 273 if (uoba->uoba_isobio4 == 0) { 274 struct sbus_attach_args *sa = &uoba->uoba_sbus; 275 void *va; 276 struct zs_chanstate *cs; 277 int channel; 278 279 if (sa->sa_nintr == 0) { 280 printf(" no interrupt lines\n"); 281 return; 282 } 283 284 /* 285 * Some sun4m models (Javastations) may not map the zs device. 286 */ 287 if (sa->sa_npromvaddrs > 0) 288 va = (void *)sa->sa_promvaddr; 289 else { 290 bus_space_handle_t bh; 291 292 if (sbus_bus_map(sa->sa_bustag, 293 sa->sa_slot, 294 sa->sa_offset, 295 sa->sa_size, 296 BUS_SPACE_MAP_LINEAR, 297 0, &bh) != 0) { 298 printf(" cannot map zs registers\n"); 299 return; 300 } 301 va = (void *)bh; 302 } 303 304 /* 305 * Check if power state can be set, e.g. Tadpole 3GX 306 */ 307 if (getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 308 { 309 printf (" powered via auxio2"); 310 for (channel = 0; channel < 2; channel++) { 311 cs = &zsc->zsc_cs_store[channel]; 312 cs->enable = zs_enable; 313 cs->disable = zs_disable; 314 } 315 } 316 317 zsc->zsc_bustag = sa->sa_bustag; 318 zsc->zsc_dmatag = sa->sa_dmatag; 319 zsc->zsc_promunit = getpropint(sa->sa_node, "slave", -2); 320 zsc->zsc_node = sa->sa_node; 321 zs_attach(zsc, va, sa->sa_pri); 322 } else { 323 struct obio4_attach_args *oba = &uoba->uoba_oba4; 324 bus_space_handle_t bh; 325 bus_addr_t paddr = oba->oba_paddr; 326 327 /* 328 * As for zs on mainbus, we require a PROM mapping. 329 */ 330 if (bus_space_map(oba->oba_bustag, 331 paddr, 332 sizeof(struct zsdevice), 333 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 334 &bh) != 0) { 335 printf(" cannot map zs registers\n"); 336 return; 337 } 338 zsc->zsc_bustag = oba->oba_bustag; 339 zsc->zsc_dmatag = oba->oba_dmatag; 340 /* Find prom unit by physical address */ 341 zsc->zsc_promunit = 342 (paddr == 0xf1000000) ? 0 : 343 (paddr == 0xf0000000) ? 1 : 344 (paddr == 0xe0000000) ? 2 : -2; 345 346 zs_attach(zsc, (void *)bh, oba->oba_pri); 347 } 348 } 349 /* 350 * Attach a found zs. 351 * 352 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 353 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 354 */ 355 static void 356 zs_attach(zsc, zsd, pri) 357 struct zsc_softc *zsc; 358 struct zsdevice *zsd; 359 int pri; 360 { 361 struct zsc_attach_args zsc_args; 362 struct zs_chanstate *cs; 363 int s, channel; 364 static int didintr, prevpri; 365 366 if (zsd == NULL) { 367 printf("configuration incomplete\n"); 368 return; 369 } 370 371 printf(" softpri %d\n", PIL_TTY); 372 373 /* 374 * Initialize software state for each channel. 375 */ 376 for (channel = 0; channel < 2; channel++) { 377 struct zschan *zc; 378 379 zsc_args.channel = channel; 380 cs = &zsc->zsc_cs_store[channel]; 381 zsc->zsc_cs[channel] = cs; 382 383 cs->cs_channel = channel; 384 cs->cs_private = NULL; 385 cs->cs_ops = &zsops_null; 386 cs->cs_brg_clk = PCLK / 16; 387 388 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 389 390 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 391 zsc->zsc_node, 392 channel); 393 394 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 395 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 396 zsc_args.consdev = &zs_consdev; 397 } 398 399 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 400 zs_conschan_get = zc; 401 } 402 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 403 zs_conschan_put = zc; 404 } 405 /* Childs need to set cn_dev, etc */ 406 407 cs->cs_reg_csr = &zc->zc_csr; 408 cs->cs_reg_data = &zc->zc_data; 409 410 bcopy(zs_init_reg, cs->cs_creg, 16); 411 bcopy(zs_init_reg, cs->cs_preg, 16); 412 413 /* XXX: Consult PROM properties for this?! */ 414 cs->cs_defspeed = zs_get_speed(cs); 415 cs->cs_defcflag = zs_def_cflag; 416 417 /* Make these correspond to cs_defcflag (-crtscts) */ 418 cs->cs_rr0_dcd = ZSRR0_DCD; 419 cs->cs_rr0_cts = 0; 420 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 421 cs->cs_wr5_rts = 0; 422 423 /* 424 * Clear the master interrupt enable. 425 * The INTENA is common to both channels, 426 * so just do it on the A channel. 427 */ 428 if (channel == 0) { 429 zs_write_reg(cs, 9, 0); 430 } 431 432 /* 433 * Look for a child driver for this channel. 434 * The child attach will setup the hardware. 435 */ 436 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 437 /* No sub-driver. Just reset it. */ 438 u_char reset = (channel == 0) ? 439 ZSWR9_A_RESET : ZSWR9_B_RESET; 440 s = splzs(); 441 zs_write_reg(cs, 9, reset); 442 splx(s); 443 } 444 } 445 446 /* 447 * Now safe to install interrupt handlers. Note the arguments 448 * to the interrupt handlers aren't used. Note, we only do this 449 * once since both SCCs interrupt at the same level and vector. 450 */ 451 if (!didintr) { 452 didintr = 1; 453 prevpri = pri; 454 bus_intr_establish(zsc->zsc_bustag, pri, 0, zshard, NULL); 455 intr_establish(PIL_TTY, &levelsoft); 456 } else if (pri != prevpri) 457 panic("broken zs interrupt scheme"); 458 459 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 460 zsc->zsc_dev.dv_xname, "intr"); 461 462 /* 463 * Set the master interrupt enable and interrupt vector. 464 * (common to both channels, do it on A) 465 */ 466 cs = zsc->zsc_cs[0]; 467 s = splhigh(); 468 /* interrupt vector */ 469 zs_write_reg(cs, 2, zs_init_reg[2]); 470 /* master interrupt control (enable) */ 471 zs_write_reg(cs, 9, zs_init_reg[9]); 472 splx(s); 473 474 #if 0 475 /* 476 * XXX: L1A hack - We would like to be able to break into 477 * the debugger during the rest of autoconfiguration, so 478 * lower interrupts just enough to let zs interrupts in. 479 * This is done after both zs devices are attached. 480 */ 481 if (zsc->zsc_promunit == 1) { 482 printf("zs1: enabling zs interrupts\n"); 483 (void)splfd(); /* XXX: splzs - 1 */ 484 } 485 #endif 486 } 487 488 static int 489 zs_print(aux, name) 490 void *aux; 491 const char *name; 492 { 493 struct zsc_attach_args *args = aux; 494 495 if (name != NULL) 496 printf("%s: ", name); 497 498 if (args->channel != -1) 499 printf(" channel %d", args->channel); 500 501 return (UNCONF); 502 } 503 504 static volatile int zssoftpending; 505 506 /* 507 * Our ZS chips all share a common, autovectored interrupt, 508 * so we have to look at all of them on each interrupt. 509 */ 510 static int 511 zshard(arg) 512 void *arg; 513 { 514 struct zsc_softc *zsc; 515 int unit, rr3, rval, softreq; 516 517 rval = softreq = 0; 518 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 519 struct zs_chanstate *cs; 520 521 zsc = zs_cd.cd_devs[unit]; 522 if (zsc == NULL) 523 continue; 524 rr3 = zsc_intr_hard(zsc); 525 /* Count up the interrupts. */ 526 if (rr3) { 527 rval |= rr3; 528 zsc->zsc_intrcnt.ev_count++; 529 } 530 if ((cs = zsc->zsc_cs[0]) != NULL) 531 softreq |= cs->cs_softreq; 532 if ((cs = zsc->zsc_cs[1]) != NULL) 533 softreq |= cs->cs_softreq; 534 } 535 536 /* We are at splzs here, so no need to lock. */ 537 if (softreq && (zssoftpending == 0)) { 538 zssoftpending = IE_ZSSOFT; 539 #if defined(SUN4M) 540 if (CPU_ISSUN4M) 541 raise(0, PIL_TTY); 542 else 543 #endif 544 ienab_bis(IE_ZSSOFT); 545 } 546 return (rval); 547 } 548 549 /* 550 * Similar scheme as for zshard (look at all of them) 551 */ 552 static int 553 zssoft(arg) 554 void *arg; 555 { 556 struct zsc_softc *zsc; 557 int s, unit; 558 559 /* This is not the only ISR on this IPL. */ 560 if (zssoftpending == 0) 561 return (0); 562 563 /* 564 * The soft intr. bit will be set by zshard only if 565 * the variable zssoftpending is zero. The order of 566 * these next two statements prevents our clearing 567 * the soft intr bit just after zshard has set it. 568 */ 569 /* ienab_bic(IE_ZSSOFT); */ 570 zssoftpending = 0; 571 572 /* Make sure we call the tty layer at spltty. */ 573 s = spltty(); 574 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 575 zsc = zs_cd.cd_devs[unit]; 576 if (zsc == NULL) 577 continue; 578 (void)zsc_intr_soft(zsc); 579 } 580 splx(s); 581 return (1); 582 } 583 584 585 /* 586 * Compute the current baud rate given a ZS channel. 587 */ 588 static int 589 zs_get_speed(cs) 590 struct zs_chanstate *cs; 591 { 592 int tconst; 593 594 tconst = zs_read_reg(cs, 12); 595 tconst |= zs_read_reg(cs, 13) << 8; 596 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 597 } 598 599 /* 600 * MD functions for setting the baud rate and control modes. 601 */ 602 int 603 zs_set_speed(cs, bps) 604 struct zs_chanstate *cs; 605 int bps; /* bits per second */ 606 { 607 int tconst, real_bps; 608 609 if (bps == 0) 610 return (0); 611 612 #ifdef DIAGNOSTIC 613 if (cs->cs_brg_clk == 0) 614 panic("zs_set_speed"); 615 #endif 616 617 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 618 if (tconst < 0) 619 return (EINVAL); 620 621 /* Convert back to make sure we can do it. */ 622 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 623 624 /* XXX - Allow some tolerance here? */ 625 if (real_bps != bps) 626 return (EINVAL); 627 628 cs->cs_preg[12] = tconst; 629 cs->cs_preg[13] = tconst >> 8; 630 631 /* Caller will stuff the pending registers. */ 632 return (0); 633 } 634 635 int 636 zs_set_modes(cs, cflag) 637 struct zs_chanstate *cs; 638 int cflag; /* bits per second */ 639 { 640 int s; 641 642 /* 643 * Output hardware flow control on the chip is horrendous: 644 * if carrier detect drops, the receiver is disabled, and if 645 * CTS drops, the transmitter is stoped IN MID CHARACTER! 646 * Therefore, NEVER set the HFC bit, and instead use the 647 * status interrupt to detect CTS changes. 648 */ 649 s = splzs(); 650 cs->cs_rr0_pps = 0; 651 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 652 cs->cs_rr0_dcd = 0; 653 if ((cflag & MDMBUF) == 0) 654 cs->cs_rr0_pps = ZSRR0_DCD; 655 } else 656 cs->cs_rr0_dcd = ZSRR0_DCD; 657 if ((cflag & CRTSCTS) != 0) { 658 cs->cs_wr5_dtr = ZSWR5_DTR; 659 cs->cs_wr5_rts = ZSWR5_RTS; 660 cs->cs_rr0_cts = ZSRR0_CTS; 661 } else if ((cflag & CDTRCTS) != 0) { 662 cs->cs_wr5_dtr = 0; 663 cs->cs_wr5_rts = ZSWR5_DTR; 664 cs->cs_rr0_cts = ZSRR0_CTS; 665 } else if ((cflag & MDMBUF) != 0) { 666 cs->cs_wr5_dtr = 0; 667 cs->cs_wr5_rts = ZSWR5_DTR; 668 cs->cs_rr0_cts = ZSRR0_DCD; 669 } else { 670 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 671 cs->cs_wr5_rts = 0; 672 cs->cs_rr0_cts = 0; 673 } 674 splx(s); 675 676 /* Caller will stuff the pending registers. */ 677 return (0); 678 } 679 680 681 /* 682 * Read or write the chip with suitable delays. 683 */ 684 685 u_char 686 zs_read_reg(cs, reg) 687 struct zs_chanstate *cs; 688 u_char reg; 689 { 690 u_char val; 691 692 *cs->cs_reg_csr = reg; 693 ZS_DELAY(); 694 val = *cs->cs_reg_csr; 695 ZS_DELAY(); 696 return (val); 697 } 698 699 void 700 zs_write_reg(cs, reg, val) 701 struct zs_chanstate *cs; 702 u_char reg, val; 703 { 704 *cs->cs_reg_csr = reg; 705 ZS_DELAY(); 706 *cs->cs_reg_csr = val; 707 ZS_DELAY(); 708 } 709 710 u_char 711 zs_read_csr(cs) 712 struct zs_chanstate *cs; 713 { 714 u_char val; 715 716 val = *cs->cs_reg_csr; 717 ZS_DELAY(); 718 return (val); 719 } 720 721 void 722 zs_write_csr(cs, val) 723 struct zs_chanstate *cs; 724 u_char val; 725 { 726 *cs->cs_reg_csr = val; 727 ZS_DELAY(); 728 } 729 730 u_char 731 zs_read_data(cs) 732 struct zs_chanstate *cs; 733 { 734 u_char val; 735 736 val = *cs->cs_reg_data; 737 ZS_DELAY(); 738 return (val); 739 } 740 741 void zs_write_data(cs, val) 742 struct zs_chanstate *cs; 743 u_char val; 744 { 745 *cs->cs_reg_data = val; 746 ZS_DELAY(); 747 } 748 749 /**************************************************************** 750 * Console support functions (Sun specific!) 751 * Note: this code is allowed to know about the layout of 752 * the chip registers, and uses that to keep things simple. 753 * XXX - I think I like the mvme167 code better. -gwr 754 ****************************************************************/ 755 756 /* 757 * Handle user request to enter kernel debugger. 758 */ 759 void 760 zs_abort(cs) 761 struct zs_chanstate *cs; 762 { 763 struct zschan *zc = zs_conschan_get; 764 int rr0; 765 766 /* Wait for end of break to avoid PROM abort. */ 767 /* XXX - Limit the wait? */ 768 do { 769 rr0 = zc->zc_csr; 770 ZS_DELAY(); 771 } while (rr0 & ZSRR0_BREAK); 772 773 #if defined(KGDB) 774 zskgdb(cs); 775 #elif defined(DDB) 776 Debugger(); 777 #else 778 printf("stopping on keyboard abort\n"); 779 callrom(); 780 #endif 781 } 782 783 static int zs_getc __P((void *arg)); 784 static void zs_putc __P((void *arg, int c)); 785 786 /* 787 * Polled input char. 788 */ 789 int 790 zs_getc(arg) 791 void *arg; 792 { 793 struct zschan *zc = arg; 794 int s, c, rr0; 795 796 s = splhigh(); 797 /* Wait for a character to arrive. */ 798 do { 799 rr0 = zc->zc_csr; 800 ZS_DELAY(); 801 } while ((rr0 & ZSRR0_RX_READY) == 0); 802 803 c = zc->zc_data; 804 ZS_DELAY(); 805 splx(s); 806 807 /* 808 * This is used by the kd driver to read scan codes, 809 * so don't translate '\r' ==> '\n' here... 810 */ 811 return (c); 812 } 813 814 /* 815 * Polled output char. 816 */ 817 void 818 zs_putc(arg, c) 819 void *arg; 820 int c; 821 { 822 struct zschan *zc = arg; 823 int s, rr0; 824 825 s = splhigh(); 826 827 /* Wait for transmitter to become ready. */ 828 do { 829 rr0 = zc->zc_csr; 830 ZS_DELAY(); 831 } while ((rr0 & ZSRR0_TX_READY) == 0); 832 833 /* 834 * Send the next character. 835 * Now you'd think that this could be followed by a ZS_DELAY() 836 * just like all the other chip accesses, but it turns out that 837 * the `transmit-ready' interrupt isn't de-asserted until 838 * some period of time after the register write completes 839 * (more than a couple instructions). So to avoid stray 840 * interrupts we put in the 2us delay regardless of cpu model. 841 */ 842 zc->zc_data = c; 843 delay(2); 844 845 splx(s); 846 } 847 848 /*****************************************************************/ 849 /* 850 * Polled console input putchar. 851 */ 852 int 853 zscngetc(dev) 854 dev_t dev; 855 { 856 return (zs_getc(zs_conschan_get)); 857 } 858 859 /* 860 * Polled console output putchar. 861 */ 862 void 863 zscnputc(dev, c) 864 dev_t dev; 865 int c; 866 { 867 zs_putc(zs_conschan_put, c); 868 } 869 870 void 871 zscnpollc(dev, on) 872 dev_t dev; 873 int on; 874 { 875 /* No action needed */ 876 } 877 878 int 879 zs_console_flags(promunit, node, channel) 880 int promunit; 881 int node; 882 int channel; 883 { 884 int cookie, flags = 0; 885 886 switch (prom_version()) { 887 case PROM_OLDMON: 888 case PROM_OBP_V0: 889 /* 890 * Use `promunit' and `channel' to derive the PROM 891 * stdio handles that correspond to this device. 892 */ 893 if (promunit == 0) 894 cookie = PROMDEV_TTYA + channel; 895 else if (promunit == 1 && channel == 0) 896 cookie = PROMDEV_KBD; 897 else 898 cookie = -1; 899 900 if (cookie == prom_stdin()) 901 flags |= ZS_HWFLAG_CONSOLE_INPUT; 902 903 /* 904 * Prevent the keyboard from matching the output device 905 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 906 */ 907 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 908 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 909 910 break; 911 912 case PROM_OBP_V2: 913 case PROM_OBP_V3: 914 case PROM_OPENFIRM: 915 916 /* 917 * Match the nodes and device arguments prepared by 918 * consinit() against our device node and channel. 919 * (The device argument is the part of the OBP path 920 * following the colon, as in `/obio/zs@0,100000:a') 921 */ 922 923 /* Default to channel 0 if there are no explicit prom args */ 924 cookie = 0; 925 926 if (node == prom_stdin_node) { 927 if (prom_stdin_args[0] != '\0') 928 /* Translate (a,b) -> (0,1) */ 929 cookie = prom_stdin_args[0] - 'a'; 930 931 if (channel == cookie) 932 flags |= ZS_HWFLAG_CONSOLE_INPUT; 933 } 934 935 if (node == prom_stdout_node) { 936 if (prom_stdout_args[0] != '\0') 937 /* Translate (a,b) -> (0,1) */ 938 cookie = prom_stdout_args[0] - 'a'; 939 940 if (channel == cookie) 941 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 942 } 943 944 break; 945 946 default: 947 break; 948 } 949 950 return (flags); 951 } 952 953 /* 954 * Power management hooks for zsopen() and zsclose(). 955 * We use them to power on/off the ports, if necessary. 956 */ 957 int 958 zs_enable(cs) 959 struct zs_chanstate *cs; 960 { 961 auxiotwoserialendis (ZS_ENABLE); 962 cs->enabled = 1; 963 return(0); 964 } 965 966 void 967 zs_disable(cs) 968 struct zs_chanstate *cs; 969 { 970 auxiotwoserialendis (ZS_DISABLE); 971 cs->enabled = 0; 972 } 973