1 /* $NetBSD: zs.c,v 1.101 2004/04/03 17:43:50 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.101 2004/04/03 17:43:50 chs Exp $"); 49 50 #include "opt_ddb.h" 51 #include "opt_kgdb.h" 52 #include "opt_sparc_arch.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/conf.h> 57 #include <sys/device.h> 58 #include <sys/file.h> 59 #include <sys/ioctl.h> 60 #include <sys/kernel.h> 61 #include <sys/proc.h> 62 #include <sys/tty.h> 63 #include <sys/time.h> 64 #include <sys/syslog.h> 65 66 #include <machine/bsd_openprom.h> 67 #include <machine/autoconf.h> 68 #include <machine/intr.h> 69 #include <machine/eeprom.h> 70 #include <machine/psl.h> 71 #include <machine/z8530var.h> 72 73 #include <dev/cons.h> 74 #include <dev/ic/z8530reg.h> 75 76 #include <sparc/sparc/vaddrs.h> 77 #include <sparc/sparc/auxreg.h> 78 #include <sparc/sparc/auxiotwo.h> 79 #include <sparc/dev/cons.h> 80 81 /* 82 * Some warts needed by z8530tty.c - 83 * The default parity REALLY needs to be the same as the PROM uses, 84 * or you can not see messages done with printf during boot-up... 85 */ 86 int zs_def_cflag = (CREAD | CS8 | HUPCL); 87 88 /* 89 * The Sun provides a 4.9152 MHz clock to the ZS chips. 90 */ 91 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 92 93 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 94 95 /* The layout of this is hardware-dependent (padding, order). */ 96 struct zschan { 97 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 98 u_char zc_xxx0; 99 volatile u_char zc_data; /* data */ 100 u_char zc_xxx1; 101 }; 102 struct zsdevice { 103 /* Yes, they are backwards. */ 104 struct zschan zs_chan_b; 105 struct zschan zs_chan_a; 106 }; 107 108 /* ZS channel used as the console device (if any) */ 109 void *zs_conschan_get, *zs_conschan_put; 110 111 static u_char zs_init_reg[16] = { 112 0, /* 0: CMD (reset, etc.) */ 113 0, /* 1: No interrupts yet. */ 114 0, /* 2: IVECT */ 115 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 116 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 117 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 118 0, /* 6: TXSYNC/SYNCLO */ 119 0, /* 7: RXSYNC/SYNCHI */ 120 0, /* 8: alias for data port */ 121 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 122 0, /*10: Misc. TX/RX control bits */ 123 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 124 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 125 0, /*13: BAUDHI (default=9600) */ 126 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 127 ZSWR15_BREAK_IE, 128 }; 129 130 /* Console ops */ 131 static int zscngetc __P((dev_t)); 132 static void zscnputc __P((dev_t, int)); 133 static void zscnpollc __P((dev_t, int)); 134 135 struct consdev zs_consdev = { 136 NULL, 137 NULL, 138 zscngetc, 139 zscnputc, 140 zscnpollc, 141 NULL, 142 }; 143 144 145 /**************************************************************** 146 * Autoconfig 147 ****************************************************************/ 148 149 /* Definition of the driver for autoconfig. */ 150 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 151 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 152 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 153 static void zs_attach_obio __P((struct device *, struct device *, void *)); 154 155 #if defined(SUN4D) 156 #include <sparc/dev/bootbusvar.h> 157 158 static int zs_match_bootbus __P((struct device *, struct cfdata *, void *)); 159 static void zs_attach_bootbus __P((struct device *, struct device *, void *)); 160 161 CFATTACH_DECL(zs_bootbus, sizeof(struct zsc_softc), 162 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 163 #endif /* SUN4D */ 164 165 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 166 static int zs_print __P((void *, const char *name)); 167 168 CFATTACH_DECL(zs_mainbus, sizeof(struct zsc_softc), 169 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 170 171 CFATTACH_DECL(zs_obio, sizeof(struct zsc_softc), 172 zs_match_obio, zs_attach_obio, NULL, NULL); 173 174 extern struct cfdriver zs_cd; 175 176 /* softintr(9) cookie, shared by all instances of this driver */ 177 static void *zs_sicookie; 178 179 /* Interrupt handlers. */ 180 static int zshard __P((void *)); 181 static void zssoft __P((void *)); 182 183 static int zs_get_speed __P((struct zs_chanstate *)); 184 185 /* Console device support */ 186 static int zs_console_flags __P((int, int, int)); 187 188 /* Power management hooks */ 189 int zs_enable __P((struct zs_chanstate *)); 190 void zs_disable __P((struct zs_chanstate *)); 191 192 193 /* 194 * Is the zs chip present? 195 */ 196 static int 197 zs_match_mainbus(parent, cf, aux) 198 struct device *parent; 199 struct cfdata *cf; 200 void *aux; 201 { 202 struct mainbus_attach_args *ma = aux; 203 204 if (strcmp(cf->cf_name, ma->ma_name) != 0) 205 return (0); 206 207 return (1); 208 } 209 210 static int 211 zs_match_obio(parent, cf, aux) 212 struct device *parent; 213 struct cfdata *cf; 214 void *aux; 215 { 216 union obio_attach_args *uoba = aux; 217 struct obio4_attach_args *oba; 218 219 if (uoba->uoba_isobio4 == 0) { 220 struct sbus_attach_args *sa = &uoba->uoba_sbus; 221 222 if (strcmp(cf->cf_name, sa->sa_name) != 0) 223 return (0); 224 225 return (1); 226 } 227 228 oba = &uoba->uoba_oba4; 229 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 230 1, 0, 0, NULL, NULL)); 231 } 232 233 #if defined(SUN4D) 234 static int 235 zs_match_bootbus(parent, cf, aux) 236 struct device *parent; 237 struct cfdata *cf; 238 void *aux; 239 { 240 struct bootbus_attach_args *baa = aux; 241 242 return (strcmp(cf->cf_name, baa->ba_name) == 0); 243 } 244 #endif /* SUN4D */ 245 246 static void 247 zs_attach_mainbus(parent, self, aux) 248 struct device *parent; 249 struct device *self; 250 void *aux; 251 { 252 struct zsc_softc *zsc = (void *) self; 253 struct mainbus_attach_args *ma = aux; 254 255 zsc->zsc_bustag = ma->ma_bustag; 256 zsc->zsc_dmatag = ma->ma_dmatag; 257 zsc->zsc_promunit = prom_getpropint(ma->ma_node, "slave", -2); 258 zsc->zsc_node = ma->ma_node; 259 260 /* 261 * For machines with zs on mainbus (all sun4c models), we expect 262 * the device registers to be mapped by the PROM. 263 */ 264 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 265 } 266 267 static void 268 zs_attach_obio(parent, self, aux) 269 struct device *parent; 270 struct device *self; 271 void *aux; 272 { 273 struct zsc_softc *zsc = (void *) self; 274 union obio_attach_args *uoba = aux; 275 276 if (uoba->uoba_isobio4 == 0) { 277 struct sbus_attach_args *sa = &uoba->uoba_sbus; 278 void *va; 279 struct zs_chanstate *cs; 280 int channel; 281 282 if (sa->sa_nintr == 0) { 283 printf(" no interrupt lines\n"); 284 return; 285 } 286 287 /* 288 * Some sun4m models (Javastations) may not map the zs device. 289 */ 290 if (sa->sa_npromvaddrs > 0) 291 va = (void *)sa->sa_promvaddr; 292 else { 293 bus_space_handle_t bh; 294 295 if (sbus_bus_map(sa->sa_bustag, 296 sa->sa_slot, 297 sa->sa_offset, 298 sa->sa_size, 299 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 300 printf(" cannot map zs registers\n"); 301 return; 302 } 303 va = (void *)bh; 304 } 305 306 /* 307 * Check if power state can be set, e.g. Tadpole 3GX 308 */ 309 if (prom_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 310 { 311 printf (" powered via auxio2"); 312 for (channel = 0; channel < 2; channel++) { 313 cs = &zsc->zsc_cs_store[channel]; 314 cs->enable = zs_enable; 315 cs->disable = zs_disable; 316 } 317 } 318 319 zsc->zsc_bustag = sa->sa_bustag; 320 zsc->zsc_dmatag = sa->sa_dmatag; 321 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 322 zsc->zsc_node = sa->sa_node; 323 zs_attach(zsc, va, sa->sa_pri); 324 } else { 325 struct obio4_attach_args *oba = &uoba->uoba_oba4; 326 bus_space_handle_t bh; 327 bus_addr_t paddr = oba->oba_paddr; 328 329 /* 330 * As for zs on mainbus, we require a PROM mapping. 331 */ 332 if (bus_space_map(oba->oba_bustag, 333 paddr, 334 sizeof(struct zsdevice), 335 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 336 &bh) != 0) { 337 printf(" cannot map zs registers\n"); 338 return; 339 } 340 zsc->zsc_bustag = oba->oba_bustag; 341 zsc->zsc_dmatag = oba->oba_dmatag; 342 /* 343 * Find prom unit by physical address 344 * We're just comparing the address (not the iospace) here 345 */ 346 paddr = BUS_ADDR_PADDR(paddr); 347 if (cpuinfo.cpu_type == CPUTYP_4_100) 348 /* 349 * On the sun4/100, the top-most 4 bits are zero 350 * on obio addresses; force them to 1's for the 351 * sake of the comparison here. 352 */ 353 paddr |= 0xf0000000; 354 zsc->zsc_promunit = 355 (paddr == 0xf1000000) ? 0 : 356 (paddr == 0xf0000000) ? 1 : 357 (paddr == 0xe0000000) ? 2 : -2; 358 359 zs_attach(zsc, (void *)bh, oba->oba_pri); 360 } 361 } 362 363 #if defined(SUN4D) 364 static void 365 zs_attach_bootbus(parent, self, aux) 366 struct device *parent; 367 struct device *self; 368 void *aux; 369 { 370 struct zsc_softc *zsc = (void *) self; 371 struct bootbus_attach_args *baa = aux; 372 void *va; 373 374 if (baa->ba_nintr == 0) { 375 printf(": no interrupt lines\n"); 376 return; 377 } 378 379 if (baa->ba_npromvaddrs > 0) 380 va = (void *) baa->ba_promvaddrs; 381 else { 382 bus_space_handle_t bh; 383 384 if (bus_space_map(baa->ba_bustag, 385 BUS_ADDR(baa->ba_slot, baa->ba_offset), 386 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 387 printf(": cannot map zs registers\n"); 388 return; 389 } 390 va = (void *) bh; 391 } 392 393 zsc->zsc_bustag = baa->ba_bustag; 394 zsc->zsc_promunit = prom_getpropint(baa->ba_node, "slave", -2); 395 zsc->zsc_node = baa->ba_node; 396 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 397 } 398 #endif /* SUN4D */ 399 400 /* 401 * Attach a found zs. 402 * 403 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 404 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 405 */ 406 static void 407 zs_attach(zsc, zsd, pri) 408 struct zsc_softc *zsc; 409 struct zsdevice *zsd; 410 int pri; 411 { 412 struct zsc_attach_args zsc_args; 413 struct zs_chanstate *cs; 414 int s, channel; 415 static int didintr, prevpri; 416 417 if (zsd == NULL) { 418 printf("configuration incomplete\n"); 419 return; 420 } 421 422 if (!didintr) { 423 zs_sicookie = softintr_establish(IPL_SOFTSERIAL, zssoft, NULL); 424 if (zs_sicookie == NULL) { 425 printf("\n%s: cannot establish soft int handler\n", 426 zsc->zsc_dev.dv_xname); 427 return; 428 } 429 } 430 printf(" softpri %d\n", IPL_SOFTSERIAL); 431 432 /* 433 * Initialize software state for each channel. 434 */ 435 for (channel = 0; channel < 2; channel++) { 436 struct zschan *zc; 437 438 zsc_args.channel = channel; 439 cs = &zsc->zsc_cs_store[channel]; 440 zsc->zsc_cs[channel] = cs; 441 442 simple_lock_init(&cs->cs_lock); 443 cs->cs_channel = channel; 444 cs->cs_private = NULL; 445 cs->cs_ops = &zsops_null; 446 cs->cs_brg_clk = PCLK / 16; 447 448 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 449 450 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 451 zsc->zsc_node, 452 channel); 453 454 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 455 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 456 zsc_args.consdev = &zs_consdev; 457 } 458 459 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 460 zs_conschan_get = zc; 461 } 462 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 463 zs_conschan_put = zc; 464 } 465 /* Childs need to set cn_dev, etc */ 466 467 cs->cs_reg_csr = &zc->zc_csr; 468 cs->cs_reg_data = &zc->zc_data; 469 470 bcopy(zs_init_reg, cs->cs_creg, 16); 471 bcopy(zs_init_reg, cs->cs_preg, 16); 472 473 /* XXX: Consult PROM properties for this?! */ 474 cs->cs_defspeed = zs_get_speed(cs); 475 cs->cs_defcflag = zs_def_cflag; 476 477 /* Make these correspond to cs_defcflag (-crtscts) */ 478 cs->cs_rr0_dcd = ZSRR0_DCD; 479 cs->cs_rr0_cts = 0; 480 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 481 cs->cs_wr5_rts = 0; 482 483 /* 484 * Clear the master interrupt enable. 485 * The INTENA is common to both channels, 486 * so just do it on the A channel. 487 */ 488 if (channel == 0) { 489 zs_write_reg(cs, 9, 0); 490 } 491 492 /* 493 * Look for a child driver for this channel. 494 * The child attach will setup the hardware. 495 */ 496 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 497 /* No sub-driver. Just reset it. */ 498 u_char reset = (channel == 0) ? 499 ZSWR9_A_RESET : ZSWR9_B_RESET; 500 s = splzs(); 501 zs_write_reg(cs, 9, reset); 502 splx(s); 503 } 504 } 505 506 /* 507 * Now safe to install interrupt handlers. Note the arguments 508 * to the interrupt handlers aren't used. Note, we only do this 509 * once since both SCCs interrupt at the same level and vector. 510 */ 511 if (!didintr) { 512 didintr = 1; 513 prevpri = pri; 514 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 515 zshard, NULL); 516 } else if (pri != prevpri) 517 panic("broken zs interrupt scheme"); 518 519 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 520 zsc->zsc_dev.dv_xname, "intr"); 521 522 /* 523 * Set the master interrupt enable and interrupt vector. 524 * (common to both channels, do it on A) 525 */ 526 cs = zsc->zsc_cs[0]; 527 s = splhigh(); 528 /* interrupt vector */ 529 zs_write_reg(cs, 2, zs_init_reg[2]); 530 /* master interrupt control (enable) */ 531 zs_write_reg(cs, 9, zs_init_reg[9]); 532 splx(s); 533 534 #if 0 535 /* 536 * XXX: L1A hack - We would like to be able to break into 537 * the debugger during the rest of autoconfiguration, so 538 * lower interrupts just enough to let zs interrupts in. 539 * This is done after both zs devices are attached. 540 */ 541 if (zsc->zsc_promunit == 1) { 542 printf("zs1: enabling zs interrupts\n"); 543 (void)splfd(); /* XXX: splzs - 1 */ 544 } 545 #endif 546 } 547 548 static int 549 zs_print(aux, name) 550 void *aux; 551 const char *name; 552 { 553 struct zsc_attach_args *args = aux; 554 555 if (name != NULL) 556 aprint_normal("%s: ", name); 557 558 if (args->channel != -1) 559 aprint_normal(" channel %d", args->channel); 560 561 return (UNCONF); 562 } 563 564 static volatile int zssoftpending; 565 566 /* 567 * Our ZS chips all share a common, autovectored interrupt, 568 * so we have to look at all of them on each interrupt. 569 */ 570 static int 571 zshard(arg) 572 void *arg; 573 { 574 struct zsc_softc *zsc; 575 int unit, rr3, rval, softreq; 576 577 rval = softreq = 0; 578 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 579 struct zs_chanstate *cs; 580 581 zsc = zs_cd.cd_devs[unit]; 582 if (zsc == NULL) 583 continue; 584 rr3 = zsc_intr_hard(zsc); 585 /* Count up the interrupts. */ 586 if (rr3) { 587 rval |= rr3; 588 zsc->zsc_intrcnt.ev_count++; 589 } 590 if ((cs = zsc->zsc_cs[0]) != NULL) 591 softreq |= cs->cs_softreq; 592 if ((cs = zsc->zsc_cs[1]) != NULL) 593 softreq |= cs->cs_softreq; 594 } 595 596 /* We are at splzs here, so no need to lock. */ 597 if (softreq && (zssoftpending == 0)) { 598 zssoftpending = 1; 599 softintr_schedule(zs_sicookie); 600 } 601 return (rval); 602 } 603 604 /* 605 * Similar scheme as for zshard (look at all of them) 606 */ 607 static void 608 zssoft(arg) 609 void *arg; 610 { 611 struct zsc_softc *zsc; 612 int s, unit; 613 614 /* This is not the only ISR on this IPL. */ 615 if (zssoftpending == 0) 616 return; 617 618 /* 619 * The soft intr. bit will be set by zshard only if 620 * the variable zssoftpending is zero. The order of 621 * these next two statements prevents our clearing 622 * the soft intr bit just after zshard has set it. 623 */ 624 /* ienab_bic(IE_ZSSOFT); */ 625 zssoftpending = 0; 626 627 /* Make sure we call the tty layer at spltty. */ 628 s = spltty(); 629 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 630 zsc = zs_cd.cd_devs[unit]; 631 if (zsc == NULL) 632 continue; 633 (void)zsc_intr_soft(zsc); 634 } 635 splx(s); 636 } 637 638 639 /* 640 * Compute the current baud rate given a ZS channel. 641 */ 642 static int 643 zs_get_speed(cs) 644 struct zs_chanstate *cs; 645 { 646 int tconst; 647 648 tconst = zs_read_reg(cs, 12); 649 tconst |= zs_read_reg(cs, 13) << 8; 650 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 651 } 652 653 /* 654 * MD functions for setting the baud rate and control modes. 655 */ 656 int 657 zs_set_speed(cs, bps) 658 struct zs_chanstate *cs; 659 int bps; /* bits per second */ 660 { 661 int tconst, real_bps; 662 663 if (bps == 0) 664 return (0); 665 666 #ifdef DIAGNOSTIC 667 if (cs->cs_brg_clk == 0) 668 panic("zs_set_speed"); 669 #endif 670 671 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 672 if (tconst < 0) 673 return (EINVAL); 674 675 /* Convert back to make sure we can do it. */ 676 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 677 678 /* XXX - Allow some tolerance here? */ 679 if (real_bps != bps) 680 return (EINVAL); 681 682 cs->cs_preg[12] = tconst; 683 cs->cs_preg[13] = tconst >> 8; 684 685 /* Caller will stuff the pending registers. */ 686 return (0); 687 } 688 689 int 690 zs_set_modes(cs, cflag) 691 struct zs_chanstate *cs; 692 int cflag; /* bits per second */ 693 { 694 int s; 695 696 /* 697 * Output hardware flow control on the chip is horrendous: 698 * if carrier detect drops, the receiver is disabled, and if 699 * CTS drops, the transmitter is stoped IN MID CHARACTER! 700 * Therefore, NEVER set the HFC bit, and instead use the 701 * status interrupt to detect CTS changes. 702 */ 703 s = splzs(); 704 cs->cs_rr0_pps = 0; 705 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 706 cs->cs_rr0_dcd = 0; 707 if ((cflag & MDMBUF) == 0) 708 cs->cs_rr0_pps = ZSRR0_DCD; 709 } else 710 cs->cs_rr0_dcd = ZSRR0_DCD; 711 if ((cflag & CRTSCTS) != 0) { 712 cs->cs_wr5_dtr = ZSWR5_DTR; 713 cs->cs_wr5_rts = ZSWR5_RTS; 714 cs->cs_rr0_cts = ZSRR0_CTS; 715 } else if ((cflag & CDTRCTS) != 0) { 716 cs->cs_wr5_dtr = 0; 717 cs->cs_wr5_rts = ZSWR5_DTR; 718 cs->cs_rr0_cts = ZSRR0_CTS; 719 } else if ((cflag & MDMBUF) != 0) { 720 cs->cs_wr5_dtr = 0; 721 cs->cs_wr5_rts = ZSWR5_DTR; 722 cs->cs_rr0_cts = ZSRR0_DCD; 723 } else { 724 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 725 cs->cs_wr5_rts = 0; 726 cs->cs_rr0_cts = 0; 727 } 728 splx(s); 729 730 /* Caller will stuff the pending registers. */ 731 return (0); 732 } 733 734 735 /* 736 * Read or write the chip with suitable delays. 737 */ 738 739 u_char 740 zs_read_reg(cs, reg) 741 struct zs_chanstate *cs; 742 u_char reg; 743 { 744 u_char val; 745 746 *cs->cs_reg_csr = reg; 747 ZS_DELAY(); 748 val = *cs->cs_reg_csr; 749 ZS_DELAY(); 750 return (val); 751 } 752 753 void 754 zs_write_reg(cs, reg, val) 755 struct zs_chanstate *cs; 756 u_char reg, val; 757 { 758 *cs->cs_reg_csr = reg; 759 ZS_DELAY(); 760 *cs->cs_reg_csr = val; 761 ZS_DELAY(); 762 } 763 764 u_char 765 zs_read_csr(cs) 766 struct zs_chanstate *cs; 767 { 768 u_char val; 769 770 val = *cs->cs_reg_csr; 771 ZS_DELAY(); 772 return (val); 773 } 774 775 void 776 zs_write_csr(cs, val) 777 struct zs_chanstate *cs; 778 u_char val; 779 { 780 *cs->cs_reg_csr = val; 781 ZS_DELAY(); 782 } 783 784 u_char 785 zs_read_data(cs) 786 struct zs_chanstate *cs; 787 { 788 u_char val; 789 790 val = *cs->cs_reg_data; 791 ZS_DELAY(); 792 return (val); 793 } 794 795 void zs_write_data(cs, val) 796 struct zs_chanstate *cs; 797 u_char val; 798 { 799 *cs->cs_reg_data = val; 800 ZS_DELAY(); 801 } 802 803 /**************************************************************** 804 * Console support functions (Sun specific!) 805 * Note: this code is allowed to know about the layout of 806 * the chip registers, and uses that to keep things simple. 807 * XXX - I think I like the mvme167 code better. -gwr 808 ****************************************************************/ 809 810 /* 811 * Handle user request to enter kernel debugger. 812 */ 813 void 814 zs_abort(cs) 815 struct zs_chanstate *cs; 816 { 817 struct zschan *zc = zs_conschan_get; 818 int rr0; 819 820 /* Wait for end of break to avoid PROM abort. */ 821 /* XXX - Limit the wait? */ 822 do { 823 rr0 = zc->zc_csr; 824 ZS_DELAY(); 825 } while (rr0 & ZSRR0_BREAK); 826 827 #if defined(KGDB) 828 zskgdb(cs); 829 #elif defined(DDB) 830 Debugger(); 831 #else 832 printf("stopping on keyboard abort\n"); 833 callrom(); 834 #endif 835 } 836 837 int zs_getc __P((void *arg)); 838 void zs_putc __P((void *arg, int c)); 839 840 /* 841 * Polled input char. 842 */ 843 int 844 zs_getc(arg) 845 void *arg; 846 { 847 struct zschan *zc = arg; 848 int s, c, rr0; 849 u_int omid; 850 851 /* Temporarily direct interrupts at ourselves */ 852 s = splhigh(); 853 omid = setitr(cpuinfo.mid); 854 855 /* Wait for a character to arrive. */ 856 do { 857 rr0 = zc->zc_csr; 858 ZS_DELAY(); 859 } while ((rr0 & ZSRR0_RX_READY) == 0); 860 861 c = zc->zc_data; 862 ZS_DELAY(); 863 setitr(omid); 864 splx(s); 865 866 /* 867 * This is used by the kd driver to read scan codes, 868 * so don't translate '\r' ==> '\n' here... 869 */ 870 return (c); 871 } 872 873 /* 874 * Polled output char. 875 */ 876 void 877 zs_putc(arg, c) 878 void *arg; 879 int c; 880 { 881 struct zschan *zc = arg; 882 int s, rr0; 883 u_int omid; 884 885 /* Temporarily direct interrupts at ourselves */ 886 s = splhigh(); 887 omid = setitr(cpuinfo.mid); 888 889 /* Wait for transmitter to become ready. */ 890 do { 891 rr0 = zc->zc_csr; 892 ZS_DELAY(); 893 } while ((rr0 & ZSRR0_TX_READY) == 0); 894 895 /* 896 * Send the next character. 897 * Now you'd think that this could be followed by a ZS_DELAY() 898 * just like all the other chip accesses, but it turns out that 899 * the `transmit-ready' interrupt isn't de-asserted until 900 * some period of time after the register write completes 901 * (more than a couple instructions). So to avoid stray 902 * interrupts we put in the 2us delay regardless of CPU model. 903 */ 904 zc->zc_data = c; 905 delay(2); 906 907 setitr(omid); 908 splx(s); 909 } 910 911 /*****************************************************************/ 912 /* 913 * Polled console input putchar. 914 */ 915 int 916 zscngetc(dev) 917 dev_t dev; 918 { 919 return (zs_getc(zs_conschan_get)); 920 } 921 922 /* 923 * Polled console output putchar. 924 */ 925 void 926 zscnputc(dev, c) 927 dev_t dev; 928 int c; 929 { 930 zs_putc(zs_conschan_put, c); 931 } 932 933 void 934 zscnpollc(dev, on) 935 dev_t dev; 936 int on; 937 { 938 /* No action needed */ 939 } 940 941 int 942 zs_console_flags(promunit, node, channel) 943 int promunit; 944 int node; 945 int channel; 946 { 947 int cookie, flags = 0; 948 949 switch (prom_version()) { 950 case PROM_OLDMON: 951 case PROM_OBP_V0: 952 /* 953 * Use `promunit' and `channel' to derive the PROM 954 * stdio handles that correspond to this device. 955 */ 956 if (promunit == 0) 957 cookie = PROMDEV_TTYA + channel; 958 else if (promunit == 1 && channel == 0) 959 cookie = PROMDEV_KBD; 960 else 961 cookie = -1; 962 963 if (cookie == prom_stdin()) 964 flags |= ZS_HWFLAG_CONSOLE_INPUT; 965 966 /* 967 * Prevent the keyboard from matching the output device 968 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 969 */ 970 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 971 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 972 973 break; 974 975 case PROM_OBP_V2: 976 case PROM_OBP_V3: 977 case PROM_OPENFIRM: 978 979 /* 980 * Match the nodes and device arguments prepared by 981 * consinit() against our device node and channel. 982 * (The device argument is the part of the OBP path 983 * following the colon, as in `/obio/zs@0,100000:a') 984 */ 985 986 /* Default to channel 0 if there are no explicit prom args */ 987 cookie = 0; 988 989 if (node == prom_stdin_node) { 990 if (prom_stdin_args[0] != '\0') 991 /* Translate (a,b) -> (0,1) */ 992 cookie = prom_stdin_args[0] - 'a'; 993 994 if (channel == cookie) 995 flags |= ZS_HWFLAG_CONSOLE_INPUT; 996 } 997 998 if (node == prom_stdout_node) { 999 if (prom_stdout_args[0] != '\0') 1000 /* Translate (a,b) -> (0,1) */ 1001 cookie = prom_stdout_args[0] - 'a'; 1002 1003 if (channel == cookie) 1004 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1005 } 1006 1007 break; 1008 1009 default: 1010 break; 1011 } 1012 1013 return (flags); 1014 } 1015 1016 /* 1017 * Power management hooks for zsopen() and zsclose(). 1018 * We use them to power on/off the ports, if necessary. 1019 */ 1020 int 1021 zs_enable(cs) 1022 struct zs_chanstate *cs; 1023 { 1024 auxiotwoserialendis (ZS_ENABLE); 1025 cs->enabled = 1; 1026 return(0); 1027 } 1028 1029 void 1030 zs_disable(cs) 1031 struct zs_chanstate *cs; 1032 { 1033 auxiotwoserialendis (ZS_DISABLE); 1034 cs->enabled = 0; 1035 } 1036