1 /* $NetBSD: zs.c,v 1.84 2001/09/26 20:53:06 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kgdb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/file.h> 55 #include <sys/ioctl.h> 56 #include <sys/kernel.h> 57 #include <sys/proc.h> 58 #include <sys/tty.h> 59 #include <sys/time.h> 60 #include <sys/syslog.h> 61 62 #include <machine/bsd_openprom.h> 63 #include <machine/autoconf.h> 64 #include <machine/intr.h> 65 #include <machine/conf.h> 66 #include <machine/eeprom.h> 67 #include <machine/psl.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 73 #include <sparc/sparc/vaddrs.h> 74 #include <sparc/sparc/auxreg.h> 75 #include <sparc/sparc/auxiotwo.h> 76 #include <sparc/dev/cons.h> 77 78 #include "kbd.h" /* NKBD */ 79 #include "zs.h" /* NZS */ 80 81 /* Make life easier for the initialized arrays here. */ 82 #if NZS < 3 83 #undef NZS 84 #define NZS 3 85 #endif 86 87 /* 88 * Some warts needed by z8530tty.c - 89 * The default parity REALLY needs to be the same as the PROM uses, 90 * or you can not see messages done with printf during boot-up... 91 */ 92 int zs_def_cflag = (CREAD | CS8 | HUPCL); 93 int zs_major = 12; 94 95 /* 96 * The Sun provides a 4.9152 MHz clock to the ZS chips. 97 */ 98 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 99 100 /* 101 * Select software interrupt bit based on TTY ipl. 102 */ 103 #if PIL_TTY == 1 104 # define IE_ZSSOFT IE_L1 105 #elif PIL_TTY == 4 106 # define IE_ZSSOFT IE_L4 107 #elif PIL_TTY == 6 108 # define IE_ZSSOFT IE_L6 109 #else 110 # error "no suitable software interrupt bit" 111 #endif 112 113 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 114 115 /* The layout of this is hardware-dependent (padding, order). */ 116 struct zschan { 117 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 118 u_char zc_xxx0; 119 volatile u_char zc_data; /* data */ 120 u_char zc_xxx1; 121 }; 122 struct zsdevice { 123 /* Yes, they are backwards. */ 124 struct zschan zs_chan_b; 125 struct zschan zs_chan_a; 126 }; 127 128 /* ZS channel used as the console device (if any) */ 129 void *zs_conschan_get, *zs_conschan_put; 130 131 static u_char zs_init_reg[16] = { 132 0, /* 0: CMD (reset, etc.) */ 133 0, /* 1: No interrupts yet. */ 134 0, /* 2: IVECT */ 135 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 136 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 137 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 138 0, /* 6: TXSYNC/SYNCLO */ 139 0, /* 7: RXSYNC/SYNCHI */ 140 0, /* 8: alias for data port */ 141 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 142 0, /*10: Misc. TX/RX control bits */ 143 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 144 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 145 0, /*13: BAUDHI (default=9600) */ 146 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 147 ZSWR15_BREAK_IE, 148 }; 149 150 /* Console ops */ 151 static int zscngetc __P((dev_t)); 152 static void zscnputc __P((dev_t, int)); 153 static void zscnpollc __P((dev_t, int)); 154 155 struct consdev zs_consdev = { 156 NULL, 157 NULL, 158 zscngetc, 159 zscnputc, 160 zscnpollc, 161 NULL, 162 }; 163 164 165 /**************************************************************** 166 * Autoconfig 167 ****************************************************************/ 168 169 /* Definition of the driver for autoconfig. */ 170 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 171 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 172 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 173 static void zs_attach_obio __P((struct device *, struct device *, void *)); 174 175 176 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 177 static int zs_print __P((void *, const char *name)); 178 179 struct cfattach zs_mainbus_ca = { 180 sizeof(struct zsc_softc), zs_match_mainbus, zs_attach_mainbus 181 }; 182 183 struct cfattach zs_obio_ca = { 184 sizeof(struct zsc_softc), zs_match_obio, zs_attach_obio 185 }; 186 187 extern struct cfdriver zs_cd; 188 189 /* Interrupt handlers. */ 190 static int zshard __P((void *)); 191 static int zssoft __P((void *)); 192 193 static int zs_get_speed __P((struct zs_chanstate *)); 194 195 /* Console device support */ 196 static int zs_console_flags __P((int, int, int)); 197 198 /* Power management hooks */ 199 int zs_enable __P((struct zs_chanstate *)); 200 void zs_disable __P((struct zs_chanstate *)); 201 202 203 /* 204 * Is the zs chip present? 205 */ 206 static int 207 zs_match_mainbus(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 struct mainbus_attach_args *ma = aux; 213 214 if (strcmp(cf->cf_driver->cd_name, ma->ma_name) != 0) 215 return (0); 216 217 return (1); 218 } 219 220 static int 221 zs_match_obio(parent, cf, aux) 222 struct device *parent; 223 struct cfdata *cf; 224 void *aux; 225 { 226 union obio_attach_args *uoba = aux; 227 struct obio4_attach_args *oba; 228 229 if (uoba->uoba_isobio4 == 0) { 230 struct sbus_attach_args *sa = &uoba->uoba_sbus; 231 232 if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0) 233 return (0); 234 235 return (1); 236 } 237 238 oba = &uoba->uoba_oba4; 239 return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 240 1, 0, 0, NULL, NULL)); 241 } 242 243 static void 244 zs_attach_mainbus(parent, self, aux) 245 struct device *parent; 246 struct device *self; 247 void *aux; 248 { 249 struct zsc_softc *zsc = (void *) self; 250 struct mainbus_attach_args *ma = aux; 251 252 zsc->zsc_bustag = ma->ma_bustag; 253 zsc->zsc_dmatag = ma->ma_dmatag; 254 zsc->zsc_promunit = PROM_getpropint(ma->ma_node, "slave", -2); 255 zsc->zsc_node = ma->ma_node; 256 257 /* 258 * For machines with zs on mainbus (all sun4c models), we expect 259 * the device registers to be mapped by the PROM. 260 */ 261 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 262 } 263 264 static void 265 zs_attach_obio(parent, self, aux) 266 struct device *parent; 267 struct device *self; 268 void *aux; 269 { 270 struct zsc_softc *zsc = (void *) self; 271 union obio_attach_args *uoba = aux; 272 273 if (uoba->uoba_isobio4 == 0) { 274 struct sbus_attach_args *sa = &uoba->uoba_sbus; 275 void *va; 276 struct zs_chanstate *cs; 277 int channel; 278 279 if (sa->sa_nintr == 0) { 280 printf(" no interrupt lines\n"); 281 return; 282 } 283 284 /* 285 * Some sun4m models (Javastations) may not map the zs device. 286 */ 287 if (sa->sa_npromvaddrs > 0) 288 va = (void *)sa->sa_promvaddr; 289 else { 290 bus_space_handle_t bh; 291 292 if (sbus_bus_map(sa->sa_bustag, 293 sa->sa_slot, 294 sa->sa_offset, 295 sa->sa_size, 296 BUS_SPACE_MAP_LINEAR, 297 0, &bh) != 0) { 298 printf(" cannot map zs registers\n"); 299 return; 300 } 301 va = (void *)bh; 302 } 303 304 /* 305 * Check if power state can be set, e.g. Tadpole 3GX 306 */ 307 if (PROM_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 308 { 309 printf (" powered via auxio2"); 310 for (channel = 0; channel < 2; channel++) { 311 cs = &zsc->zsc_cs_store[channel]; 312 cs->enable = zs_enable; 313 cs->disable = zs_disable; 314 } 315 } 316 317 zsc->zsc_bustag = sa->sa_bustag; 318 zsc->zsc_dmatag = sa->sa_dmatag; 319 zsc->zsc_promunit = PROM_getpropint(sa->sa_node, "slave", -2); 320 zsc->zsc_node = sa->sa_node; 321 zs_attach(zsc, va, sa->sa_pri); 322 } else { 323 struct obio4_attach_args *oba = &uoba->uoba_oba4; 324 bus_space_handle_t bh; 325 bus_addr_t paddr = oba->oba_paddr; 326 327 /* 328 * As for zs on mainbus, we require a PROM mapping. 329 */ 330 if (bus_space_map(oba->oba_bustag, 331 paddr, 332 sizeof(struct zsdevice), 333 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 334 &bh) != 0) { 335 printf(" cannot map zs registers\n"); 336 return; 337 } 338 zsc->zsc_bustag = oba->oba_bustag; 339 zsc->zsc_dmatag = oba->oba_dmatag; 340 /* Find prom unit by physical address */ 341 if (cpuinfo.cpu_type == CPUTYP_4_100) 342 /* 343 * On the sun4/100, the top-most 4 bits are zero 344 * on obio addresses; force them to 1's for the 345 * sake of the comparison here. 346 */ 347 paddr |= 0xf0000000; 348 zsc->zsc_promunit = 349 (paddr == 0xf1000000) ? 0 : 350 (paddr == 0xf0000000) ? 1 : 351 (paddr == 0xe0000000) ? 2 : -2; 352 353 zs_attach(zsc, (void *)bh, oba->oba_pri); 354 } 355 } 356 /* 357 * Attach a found zs. 358 * 359 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 360 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 361 */ 362 static void 363 zs_attach(zsc, zsd, pri) 364 struct zsc_softc *zsc; 365 struct zsdevice *zsd; 366 int pri; 367 { 368 struct zsc_attach_args zsc_args; 369 struct zs_chanstate *cs; 370 int s, channel; 371 static int didintr, prevpri; 372 373 if (zsd == NULL) { 374 printf("configuration incomplete\n"); 375 return; 376 } 377 378 printf(" softpri %d\n", PIL_TTY); 379 380 /* 381 * Initialize software state for each channel. 382 */ 383 for (channel = 0; channel < 2; channel++) { 384 struct zschan *zc; 385 386 zsc_args.channel = channel; 387 cs = &zsc->zsc_cs_store[channel]; 388 zsc->zsc_cs[channel] = cs; 389 390 cs->cs_channel = channel; 391 cs->cs_private = NULL; 392 cs->cs_ops = &zsops_null; 393 cs->cs_brg_clk = PCLK / 16; 394 395 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 396 397 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 398 zsc->zsc_node, 399 channel); 400 401 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 402 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 403 zsc_args.consdev = &zs_consdev; 404 } 405 406 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 407 zs_conschan_get = zc; 408 } 409 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 410 zs_conschan_put = zc; 411 } 412 /* Childs need to set cn_dev, etc */ 413 414 cs->cs_reg_csr = &zc->zc_csr; 415 cs->cs_reg_data = &zc->zc_data; 416 417 bcopy(zs_init_reg, cs->cs_creg, 16); 418 bcopy(zs_init_reg, cs->cs_preg, 16); 419 420 /* XXX: Consult PROM properties for this?! */ 421 cs->cs_defspeed = zs_get_speed(cs); 422 cs->cs_defcflag = zs_def_cflag; 423 424 /* Make these correspond to cs_defcflag (-crtscts) */ 425 cs->cs_rr0_dcd = ZSRR0_DCD; 426 cs->cs_rr0_cts = 0; 427 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 428 cs->cs_wr5_rts = 0; 429 430 /* 431 * Clear the master interrupt enable. 432 * The INTENA is common to both channels, 433 * so just do it on the A channel. 434 */ 435 if (channel == 0) { 436 zs_write_reg(cs, 9, 0); 437 } 438 439 /* 440 * Look for a child driver for this channel. 441 * The child attach will setup the hardware. 442 */ 443 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 444 /* No sub-driver. Just reset it. */ 445 u_char reset = (channel == 0) ? 446 ZSWR9_A_RESET : ZSWR9_B_RESET; 447 s = splzs(); 448 zs_write_reg(cs, 9, reset); 449 splx(s); 450 } 451 } 452 453 /* 454 * Now safe to install interrupt handlers. Note the arguments 455 * to the interrupt handlers aren't used. Note, we only do this 456 * once since both SCCs interrupt at the same level and vector. 457 */ 458 if (!didintr) { 459 didintr = 1; 460 prevpri = pri; 461 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, 462 zshard, NULL); 463 bus_intr_establish(zsc->zsc_bustag, PIL_TTY, 464 IPL_SOFTSERIAL, 465 BUS_INTR_ESTABLISH_SOFTINTR, 466 zssoft, NULL); 467 } else if (pri != prevpri) 468 panic("broken zs interrupt scheme"); 469 470 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 471 zsc->zsc_dev.dv_xname, "intr"); 472 473 /* 474 * Set the master interrupt enable and interrupt vector. 475 * (common to both channels, do it on A) 476 */ 477 cs = zsc->zsc_cs[0]; 478 s = splhigh(); 479 /* interrupt vector */ 480 zs_write_reg(cs, 2, zs_init_reg[2]); 481 /* master interrupt control (enable) */ 482 zs_write_reg(cs, 9, zs_init_reg[9]); 483 splx(s); 484 485 #if 0 486 /* 487 * XXX: L1A hack - We would like to be able to break into 488 * the debugger during the rest of autoconfiguration, so 489 * lower interrupts just enough to let zs interrupts in. 490 * This is done after both zs devices are attached. 491 */ 492 if (zsc->zsc_promunit == 1) { 493 printf("zs1: enabling zs interrupts\n"); 494 (void)splfd(); /* XXX: splzs - 1 */ 495 } 496 #endif 497 } 498 499 static int 500 zs_print(aux, name) 501 void *aux; 502 const char *name; 503 { 504 struct zsc_attach_args *args = aux; 505 506 if (name != NULL) 507 printf("%s: ", name); 508 509 if (args->channel != -1) 510 printf(" channel %d", args->channel); 511 512 return (UNCONF); 513 } 514 515 static volatile int zssoftpending; 516 517 /* 518 * Our ZS chips all share a common, autovectored interrupt, 519 * so we have to look at all of them on each interrupt. 520 */ 521 static int 522 zshard(arg) 523 void *arg; 524 { 525 struct zsc_softc *zsc; 526 int unit, rr3, rval, softreq; 527 528 rval = softreq = 0; 529 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 530 struct zs_chanstate *cs; 531 532 zsc = zs_cd.cd_devs[unit]; 533 if (zsc == NULL) 534 continue; 535 rr3 = zsc_intr_hard(zsc); 536 /* Count up the interrupts. */ 537 if (rr3) { 538 rval |= rr3; 539 zsc->zsc_intrcnt.ev_count++; 540 } 541 if ((cs = zsc->zsc_cs[0]) != NULL) 542 softreq |= cs->cs_softreq; 543 if ((cs = zsc->zsc_cs[1]) != NULL) 544 softreq |= cs->cs_softreq; 545 } 546 547 /* We are at splzs here, so no need to lock. */ 548 if (softreq && (zssoftpending == 0)) { 549 zssoftpending = IE_ZSSOFT; 550 #if defined(SUN4M) 551 if (CPU_ISSUN4M) 552 raise(0, PIL_TTY); 553 else 554 #endif 555 ienab_bis(IE_ZSSOFT); 556 } 557 return (rval); 558 } 559 560 /* 561 * Similar scheme as for zshard (look at all of them) 562 */ 563 static int 564 zssoft(arg) 565 void *arg; 566 { 567 struct zsc_softc *zsc; 568 int s, unit; 569 570 /* This is not the only ISR on this IPL. */ 571 if (zssoftpending == 0) 572 return (0); 573 574 /* 575 * The soft intr. bit will be set by zshard only if 576 * the variable zssoftpending is zero. The order of 577 * these next two statements prevents our clearing 578 * the soft intr bit just after zshard has set it. 579 */ 580 /* ienab_bic(IE_ZSSOFT); */ 581 zssoftpending = 0; 582 583 /* Make sure we call the tty layer at spltty. */ 584 s = spltty(); 585 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 586 zsc = zs_cd.cd_devs[unit]; 587 if (zsc == NULL) 588 continue; 589 (void)zsc_intr_soft(zsc); 590 } 591 splx(s); 592 return (1); 593 } 594 595 596 /* 597 * Compute the current baud rate given a ZS channel. 598 */ 599 static int 600 zs_get_speed(cs) 601 struct zs_chanstate *cs; 602 { 603 int tconst; 604 605 tconst = zs_read_reg(cs, 12); 606 tconst |= zs_read_reg(cs, 13) << 8; 607 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 608 } 609 610 /* 611 * MD functions for setting the baud rate and control modes. 612 */ 613 int 614 zs_set_speed(cs, bps) 615 struct zs_chanstate *cs; 616 int bps; /* bits per second */ 617 { 618 int tconst, real_bps; 619 620 if (bps == 0) 621 return (0); 622 623 #ifdef DIAGNOSTIC 624 if (cs->cs_brg_clk == 0) 625 panic("zs_set_speed"); 626 #endif 627 628 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 629 if (tconst < 0) 630 return (EINVAL); 631 632 /* Convert back to make sure we can do it. */ 633 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 634 635 /* XXX - Allow some tolerance here? */ 636 if (real_bps != bps) 637 return (EINVAL); 638 639 cs->cs_preg[12] = tconst; 640 cs->cs_preg[13] = tconst >> 8; 641 642 /* Caller will stuff the pending registers. */ 643 return (0); 644 } 645 646 int 647 zs_set_modes(cs, cflag) 648 struct zs_chanstate *cs; 649 int cflag; /* bits per second */ 650 { 651 int s; 652 653 /* 654 * Output hardware flow control on the chip is horrendous: 655 * if carrier detect drops, the receiver is disabled, and if 656 * CTS drops, the transmitter is stoped IN MID CHARACTER! 657 * Therefore, NEVER set the HFC bit, and instead use the 658 * status interrupt to detect CTS changes. 659 */ 660 s = splzs(); 661 cs->cs_rr0_pps = 0; 662 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 663 cs->cs_rr0_dcd = 0; 664 if ((cflag & MDMBUF) == 0) 665 cs->cs_rr0_pps = ZSRR0_DCD; 666 } else 667 cs->cs_rr0_dcd = ZSRR0_DCD; 668 if ((cflag & CRTSCTS) != 0) { 669 cs->cs_wr5_dtr = ZSWR5_DTR; 670 cs->cs_wr5_rts = ZSWR5_RTS; 671 cs->cs_rr0_cts = ZSRR0_CTS; 672 } else if ((cflag & CDTRCTS) != 0) { 673 cs->cs_wr5_dtr = 0; 674 cs->cs_wr5_rts = ZSWR5_DTR; 675 cs->cs_rr0_cts = ZSRR0_CTS; 676 } else if ((cflag & MDMBUF) != 0) { 677 cs->cs_wr5_dtr = 0; 678 cs->cs_wr5_rts = ZSWR5_DTR; 679 cs->cs_rr0_cts = ZSRR0_DCD; 680 } else { 681 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 682 cs->cs_wr5_rts = 0; 683 cs->cs_rr0_cts = 0; 684 } 685 splx(s); 686 687 /* Caller will stuff the pending registers. */ 688 return (0); 689 } 690 691 692 /* 693 * Read or write the chip with suitable delays. 694 */ 695 696 u_char 697 zs_read_reg(cs, reg) 698 struct zs_chanstate *cs; 699 u_char reg; 700 { 701 u_char val; 702 703 *cs->cs_reg_csr = reg; 704 ZS_DELAY(); 705 val = *cs->cs_reg_csr; 706 ZS_DELAY(); 707 return (val); 708 } 709 710 void 711 zs_write_reg(cs, reg, val) 712 struct zs_chanstate *cs; 713 u_char reg, val; 714 { 715 *cs->cs_reg_csr = reg; 716 ZS_DELAY(); 717 *cs->cs_reg_csr = val; 718 ZS_DELAY(); 719 } 720 721 u_char 722 zs_read_csr(cs) 723 struct zs_chanstate *cs; 724 { 725 u_char val; 726 727 val = *cs->cs_reg_csr; 728 ZS_DELAY(); 729 return (val); 730 } 731 732 void 733 zs_write_csr(cs, val) 734 struct zs_chanstate *cs; 735 u_char val; 736 { 737 *cs->cs_reg_csr = val; 738 ZS_DELAY(); 739 } 740 741 u_char 742 zs_read_data(cs) 743 struct zs_chanstate *cs; 744 { 745 u_char val; 746 747 val = *cs->cs_reg_data; 748 ZS_DELAY(); 749 return (val); 750 } 751 752 void zs_write_data(cs, val) 753 struct zs_chanstate *cs; 754 u_char val; 755 { 756 *cs->cs_reg_data = val; 757 ZS_DELAY(); 758 } 759 760 /**************************************************************** 761 * Console support functions (Sun specific!) 762 * Note: this code is allowed to know about the layout of 763 * the chip registers, and uses that to keep things simple. 764 * XXX - I think I like the mvme167 code better. -gwr 765 ****************************************************************/ 766 767 /* 768 * Handle user request to enter kernel debugger. 769 */ 770 void 771 zs_abort(cs) 772 struct zs_chanstate *cs; 773 { 774 struct zschan *zc = zs_conschan_get; 775 int rr0; 776 777 /* Wait for end of break to avoid PROM abort. */ 778 /* XXX - Limit the wait? */ 779 do { 780 rr0 = zc->zc_csr; 781 ZS_DELAY(); 782 } while (rr0 & ZSRR0_BREAK); 783 784 #if defined(KGDB) 785 zskgdb(cs); 786 #elif defined(DDB) 787 Debugger(); 788 #else 789 printf("stopping on keyboard abort\n"); 790 callrom(); 791 #endif 792 } 793 794 int zs_getc __P((void *arg)); 795 void zs_putc __P((void *arg, int c)); 796 797 /* 798 * Polled input char. 799 */ 800 int 801 zs_getc(arg) 802 void *arg; 803 { 804 struct zschan *zc = arg; 805 int s, c, rr0; 806 807 s = splhigh(); 808 /* Wait for a character to arrive. */ 809 do { 810 rr0 = zc->zc_csr; 811 ZS_DELAY(); 812 } while ((rr0 & ZSRR0_RX_READY) == 0); 813 814 c = zc->zc_data; 815 ZS_DELAY(); 816 splx(s); 817 818 /* 819 * This is used by the kd driver to read scan codes, 820 * so don't translate '\r' ==> '\n' here... 821 */ 822 return (c); 823 } 824 825 /* 826 * Polled output char. 827 */ 828 void 829 zs_putc(arg, c) 830 void *arg; 831 int c; 832 { 833 struct zschan *zc = arg; 834 int s, rr0; 835 836 s = splhigh(); 837 838 /* Wait for transmitter to become ready. */ 839 do { 840 rr0 = zc->zc_csr; 841 ZS_DELAY(); 842 } while ((rr0 & ZSRR0_TX_READY) == 0); 843 844 /* 845 * Send the next character. 846 * Now you'd think that this could be followed by a ZS_DELAY() 847 * just like all the other chip accesses, but it turns out that 848 * the `transmit-ready' interrupt isn't de-asserted until 849 * some period of time after the register write completes 850 * (more than a couple instructions). So to avoid stray 851 * interrupts we put in the 2us delay regardless of cpu model. 852 */ 853 zc->zc_data = c; 854 delay(2); 855 856 splx(s); 857 } 858 859 /*****************************************************************/ 860 /* 861 * Polled console input putchar. 862 */ 863 int 864 zscngetc(dev) 865 dev_t dev; 866 { 867 return (zs_getc(zs_conschan_get)); 868 } 869 870 /* 871 * Polled console output putchar. 872 */ 873 void 874 zscnputc(dev, c) 875 dev_t dev; 876 int c; 877 { 878 zs_putc(zs_conschan_put, c); 879 } 880 881 void 882 zscnpollc(dev, on) 883 dev_t dev; 884 int on; 885 { 886 /* No action needed */ 887 } 888 889 int 890 zs_console_flags(promunit, node, channel) 891 int promunit; 892 int node; 893 int channel; 894 { 895 int cookie, flags = 0; 896 897 switch (prom_version()) { 898 case PROM_OLDMON: 899 case PROM_OBP_V0: 900 /* 901 * Use `promunit' and `channel' to derive the PROM 902 * stdio handles that correspond to this device. 903 */ 904 if (promunit == 0) 905 cookie = PROMDEV_TTYA + channel; 906 else if (promunit == 1 && channel == 0) 907 cookie = PROMDEV_KBD; 908 else 909 cookie = -1; 910 911 if (cookie == prom_stdin()) 912 flags |= ZS_HWFLAG_CONSOLE_INPUT; 913 914 /* 915 * Prevent the keyboard from matching the output device 916 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 917 */ 918 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 919 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 920 921 break; 922 923 case PROM_OBP_V2: 924 case PROM_OBP_V3: 925 case PROM_OPENFIRM: 926 927 /* 928 * Match the nodes and device arguments prepared by 929 * consinit() against our device node and channel. 930 * (The device argument is the part of the OBP path 931 * following the colon, as in `/obio/zs@0,100000:a') 932 */ 933 934 /* Default to channel 0 if there are no explicit prom args */ 935 cookie = 0; 936 937 if (node == prom_stdin_node) { 938 if (prom_stdin_args[0] != '\0') 939 /* Translate (a,b) -> (0,1) */ 940 cookie = prom_stdin_args[0] - 'a'; 941 942 if (channel == cookie) 943 flags |= ZS_HWFLAG_CONSOLE_INPUT; 944 } 945 946 if (node == prom_stdout_node) { 947 if (prom_stdout_args[0] != '\0') 948 /* Translate (a,b) -> (0,1) */ 949 cookie = prom_stdout_args[0] - 'a'; 950 951 if (channel == cookie) 952 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 953 } 954 955 break; 956 957 default: 958 break; 959 } 960 961 return (flags); 962 } 963 964 /* 965 * Power management hooks for zsopen() and zsclose(). 966 * We use them to power on/off the ports, if necessary. 967 */ 968 int 969 zs_enable(cs) 970 struct zs_chanstate *cs; 971 { 972 auxiotwoserialendis (ZS_ENABLE); 973 cs->enabled = 1; 974 return(0); 975 } 976 977 void 978 zs_disable(cs) 979 struct zs_chanstate *cs; 980 { 981 auxiotwoserialendis (ZS_DISABLE); 982 cs->enabled = 0; 983 } 984