1 /* $NetBSD: swreg.h,v 1.1 2000/06/26 19:54:09 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Register map for the Sun3 SCSI Interface (si) 41 * The first part of this register map is an NCR5380 42 * SCSI Bus Interface Controller (SBIC). The rest is a 43 * DMA controller and custom logic for the OBIO interface (3/50,3/60,4/110) 44 * 45 * Modified for Sun 4 systems by Jason R. Thorpe <thorpej@NetBSD.ORG>. 46 */ 47 48 /* 49 * Note that the obio version on the 4/1xx (the so-called "SCSI Weird", or 50 * "sw" controller) is laid out a bit differently, and hence the evilness 51 * with unions. Also, the "sw" doesn't appear to have a FIFO. 52 */ 53 54 #if __for_reference_only__ 55 struct sw_regs { 56 /* 57 * Am5380 Register map (no padding). See dev/ic/ncr5380reg.h 58 */ 59 struct ncr5380regs { 60 u_char r[8]; 61 } sci; 62 63 /* DMA controller registers on OBIO */ 64 u_int dma_addr; /* dma address */ 65 u_int dma_count; /* dma count */ 66 u_int pad0; /* no-existent register */ 67 u_int sw_csr; /* sw control/status */ 68 u_int bpr; /* sw byte pack */ 69 }; 70 #endif 71 72 /* 73 * Size of NCR5380 registers located at the bottom of the register bank. 74 */ 75 #define NCR5380REGS_SZ 8 76 77 /* 78 * Register definition for the `sw' OBIO controller 79 */ 80 #define SWREG_DMA_ADDR (NCR5380REGS_SZ + 0) 81 #define SWREG_DMA_CNT (NCR5380REGS_SZ + 4) 82 #define SWREG_CSR (NCR5380REGS_SZ + 12) 83 #define SWREG_BPR (NCR5380REGS_SZ + 16) 84 #define SWREG_BANK_SZ (NCR5380REGS_SZ + 20) 85 86 /* 87 * Status Register. 88 * Note: 89 * (r) indicates bit is read only. 90 * (rw) indicates bit is read or write. 91 * (v) vme host adaptor interface only. 92 * (o) sun3/50 onboard host adaptor interface only. 93 * (b) both vme and sun3/50 host adaptor interfaces. 94 */ 95 #define SW_CSR_DMA_ACTIVE 0x8000 /* (r,o) dma transfer active */ 96 #define SW_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while dmaing */ 97 #define SW_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during dma */ 98 #define SW_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */ 99 /* 0 if SCSI-3 unmodified */ 100 #define SW_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */ 101 #define SW_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */ 102 #define SW_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */ 103 #define SW_CSR_DMA_IP 0x0100 /* (r,b) dma interrupt pending */ 104 #define SW_CSR_DMA_EN 0x0010 /* (rw,v) dma/interrupt enable */ 105 #define SW_CSR_SEND 0x0008 /* (rw,b) dma dir, 1=to device */ 106 #define SW_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */ 107 #define SW_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */ 108 #define SW_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */ 109