1 /* $NetBSD: sbus.c,v 1.33 1998/09/20 20:08:52 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Sbus stuff. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/systm.h> 91 #include <sys/device.h> 92 #include <vm/vm.h> 93 94 #include <machine/bus.h> 95 #include <sparc/dev/sbusreg.h> 96 #include <dev/sbus/sbusvar.h> 97 #include <dev/sbus/xboxvar.h> 98 99 #include <sparc/sparc/iommuvar.h> 100 #include <machine/autoconf.h> 101 102 103 void sbusreset __P((int)); 104 105 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 106 static int sbus_get_intr __P((struct sbus_softc *, int, 107 struct sbus_intr **, int *)); 108 static int sbus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 109 int, bus_space_handle_t *)); 110 static int _sbus_bus_map __P(( 111 bus_space_tag_t, 112 bus_type_t, /*slot*/ 113 bus_addr_t, /*offset*/ 114 bus_size_t, /*size*/ 115 int, /*flags*/ 116 vaddr_t, /*preferred virtual address */ 117 bus_space_handle_t *)); 118 static void *sbus_intr_establish __P(( 119 bus_space_tag_t, 120 int, /*level*/ 121 int, /*flags*/ 122 int (*) __P((void *)), /*handler*/ 123 void *)); /*handler arg*/ 124 125 126 /* autoconfiguration driver */ 127 int sbus_match_mainbus __P((struct device *, struct cfdata *, void *)); 128 int sbus_match_iommu __P((struct device *, struct cfdata *, void *)); 129 int sbus_match_xbox __P((struct device *, struct cfdata *, void *)); 130 void sbus_attach_mainbus __P((struct device *, struct device *, void *)); 131 void sbus_attach_iommu __P((struct device *, struct device *, void *)); 132 void sbus_attach_xbox __P((struct device *, struct device *, void *)); 133 134 static int sbus_error __P((void)); 135 int (*sbuserr_handler) __P((void)); 136 137 struct cfattach sbus_mainbus_ca = { 138 sizeof(struct sbus_softc), sbus_match_mainbus, sbus_attach_mainbus 139 }; 140 struct cfattach sbus_iommu_ca = { 141 sizeof(struct sbus_softc), sbus_match_iommu, sbus_attach_iommu 142 }; 143 struct cfattach sbus_xbox_ca = { 144 sizeof(struct sbus_softc), sbus_match_xbox, sbus_attach_xbox 145 }; 146 147 extern struct cfdriver sbus_cd; 148 149 /* The "primary" Sbus */ 150 struct sbus_softc *sbus_sc; 151 152 /* If the PROM does not provide the `ranges' property, we make up our own */ 153 struct sbus_range sbus_translations[] = { 154 /* Assume a maximum of 4 Sbus slots, all mapped to on-board io space */ 155 { 0, 0, PMAP_OBIO, SBUS_ADDR(0,0), 1 << 25 }, 156 { 1, 0, PMAP_OBIO, SBUS_ADDR(1,0), 1 << 25 }, 157 { 2, 0, PMAP_OBIO, SBUS_ADDR(2,0), 1 << 25 }, 158 { 3, 0, PMAP_OBIO, SBUS_ADDR(3,0), 1 << 25 } 159 }; 160 161 /* 162 * Child devices receive the Sbus interrupt level in their attach 163 * arguments. We translate these to CPU IPLs using the following 164 * tables. Note: obio bus interrupt levels are identical to the 165 * processor IPL. 166 * 167 * The second set of tables is used when the Sbus interrupt level 168 * cannot be had from the PROM as an `interrupt' property. We then 169 * fall back on the `intr' property which contains the CPU IPL. 170 */ 171 172 /* Translate Sbus interrupt level to processor IPL */ 173 static int intr_sbus2ipl_4c[] = { 174 0, 1, 2, 3, 5, 7, 8, 9 175 }; 176 static int intr_sbus2ipl_4m[] = { 177 0, 2, 3, 5, 7, 9, 11, 13 178 }; 179 180 /* 181 * This value is or'ed into the attach args' interrupt level cookie 182 * if the interrupt level comes from an `intr' property, i.e. it is 183 * not an Sbus interrupt level. 184 */ 185 #define SBUS_INTR_COMPAT 0x80000000 186 187 188 /* 189 * Print the location of some sbus-attached device (called just 190 * before attaching that device). If `sbus' is not NULL, the 191 * device was found but not configured; print the sbus as well. 192 * Return UNCONF (config_find ignores this if the device was configured). 193 */ 194 int 195 sbus_print(args, busname) 196 void *args; 197 const char *busname; 198 { 199 struct sbus_attach_args *sa = args; 200 int i; 201 202 if (busname) 203 printf("%s at %s", sa->sa_name, busname); 204 printf(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset); 205 for (i = 0; i < sa->sa_nintr; i++) { 206 u_int32_t level = sa->sa_intr[i].sbi_pri; 207 struct sbus_softc *sc = 208 (struct sbus_softc *) sa->sa_bustag->cookie; 209 210 printf(" level %d", level & ~SBUS_INTR_COMPAT); 211 if ((level & SBUS_INTR_COMPAT) == 0) { 212 int ipl = sc->sc_intr2ipl[level]; 213 if (ipl != level) 214 printf(" (ipl %d)", ipl); 215 } 216 } 217 return (UNCONF); 218 } 219 220 int 221 sbus_match_mainbus(parent, cf, aux) 222 struct device *parent; 223 struct cfdata *cf; 224 void *aux; 225 { 226 struct mainbus_attach_args *ma = aux; 227 228 if (CPU_ISSUN4) 229 return (0); 230 231 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 232 } 233 234 int 235 sbus_match_iommu(parent, cf, aux) 236 struct device *parent; 237 struct cfdata *cf; 238 void *aux; 239 { 240 struct iommu_attach_args *ia = aux; 241 242 if (CPU_ISSUN4) 243 return (0); 244 245 return (strcmp(cf->cf_driver->cd_name, ia->iom_name) == 0); 246 } 247 248 int 249 sbus_match_xbox(parent, cf, aux) 250 struct device *parent; 251 struct cfdata *cf; 252 void *aux; 253 { 254 struct xbox_attach_args *xa = aux; 255 256 if (CPU_ISSUN4) 257 return (0); 258 259 return (strcmp(cf->cf_driver->cd_name, xa->xa_name) == 0); 260 } 261 262 /* 263 * Attach an Sbus. 264 */ 265 void 266 sbus_attach_mainbus(parent, self, aux) 267 struct device *parent; 268 struct device *self; 269 void *aux; 270 { 271 struct sbus_softc *sc = (struct sbus_softc *)self; 272 struct mainbus_attach_args *ma = aux; 273 int node = ma->ma_node; 274 275 /* 276 * XXX there is only one Sbus, for now -- do not know how to 277 * address children on others 278 */ 279 if (sc->sc_dev.dv_unit > 0) { 280 printf(" unsupported\n"); 281 return; 282 } 283 284 sc->sc_bustag = ma->ma_bustag; 285 sc->sc_dmatag = ma->ma_dmatag; 286 287 #if 0 /* sbus at mainbus (sun4c): `reg' prop is not control space */ 288 if (ma->ma_size == 0) 289 printf("%s: no Sbus registers", self->dv_xname); 290 291 if (bus_space_map2(ma->ma_bustag, 292 (bus_type_t)ma->ma_iospace, 293 (bus_addr_t)ma->ma_paddr, 294 (bus_size_t)ma->ma_size, 295 BUS_SPACE_MAP_LINEAR, 296 0, &sc->sc_bh) != 0) { 297 panic("%s: can't map sbusbusreg", self->dv_xname); 298 } 299 #endif 300 301 /* Setup interrupt translation tables */ 302 sc->sc_intr2ipl = CPU_ISSUN4C 303 ? intr_sbus2ipl_4c 304 : intr_sbus2ipl_4m; 305 306 /* 307 * Record clock frequency for synchronous SCSI. 308 * IS THIS THE CORRECT DEFAULT?? 309 */ 310 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 311 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 312 313 sbus_sc = sc; 314 sbus_attach_common(sc, "sbus", node, ma->ma_bp, NULL); 315 } 316 317 318 void 319 sbus_attach_iommu(parent, self, aux) 320 struct device *parent; 321 struct device *self; 322 void *aux; 323 { 324 struct sbus_softc *sc = (struct sbus_softc *)self; 325 struct iommu_attach_args *ia = aux; 326 int node = ia->iom_node; 327 328 sc->sc_bustag = ia->iom_bustag; 329 sc->sc_dmatag = ia->iom_dmatag; 330 331 if (ia->iom_nreg == 0) 332 panic("%s: no Sbus registers", self->dv_xname); 333 334 if (bus_space_map2(ia->iom_bustag, 335 (bus_type_t)ia->iom_reg[0].ior_iospace, 336 (bus_addr_t)ia->iom_reg[0].ior_pa, 337 (bus_size_t)ia->iom_reg[0].ior_size, 338 BUS_SPACE_MAP_LINEAR, 339 0, &sc->sc_bh) != 0) { 340 panic("%s: can't map sbusbusreg", self->dv_xname); 341 } 342 343 /* Setup interrupt translation tables */ 344 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 345 346 /* 347 * Record clock frequency for synchronous SCSI. 348 * IS THIS THE CORRECT DEFAULT?? 349 */ 350 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 351 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 352 353 sbus_sc = sc; 354 sbuserr_handler = sbus_error; 355 sbus_attach_common(sc, "sbus", node, ia->iom_bp, NULL); 356 } 357 358 void 359 sbus_attach_xbox(parent, self, aux) 360 struct device *parent; 361 struct device *self; 362 void *aux; 363 { 364 struct sbus_softc *sc = (struct sbus_softc *)self; 365 struct xbox_attach_args *xa = aux; 366 int node = xa->xa_node; 367 368 sc->sc_bustag = xa->xa_bustag; 369 sc->sc_dmatag = xa->xa_dmatag; 370 371 /* Setup interrupt translation tables */ 372 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 373 374 /* 375 * Record clock frequency for synchronous SCSI. 376 * IS THIS THE CORRECT DEFAULT?? 377 */ 378 sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000); 379 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 380 381 sbus_attach_common(sc, "sbus", node, xa->xa_bp, NULL); 382 } 383 384 void 385 sbus_attach_common(sc, busname, busnode, bp, specials) 386 struct sbus_softc *sc; 387 char *busname; 388 int busnode; 389 struct bootpath *bp; 390 const char * const *specials; 391 { 392 int node0, node, error; 393 const char *sp; 394 const char *const *ssp; 395 bus_space_tag_t sbt; 396 struct sbus_attach_args sa; 397 398 sbt = sbus_alloc_bustag(sc); 399 400 /* 401 * Get the SBus burst transfer size if burst transfers are supported 402 */ 403 sc->sc_burst = getpropint(busnode, "burst-sizes", 0); 404 405 /* Propagate bootpath */ 406 if (bp != NULL && strcmp(bp->name, busname) == 0) 407 bp++; 408 else 409 bp = NULL; 410 411 /* 412 * Collect address translations from the OBP. 413 */ 414 error = getprop(busnode, "ranges", sizeof(struct rom_range), 415 &sc->sc_nrange, (void **)&sc->sc_range); 416 switch (error) { 417 case 0: 418 break; 419 case ENOENT: 420 /* Fall back to our own `range' construction */ 421 sc->sc_range = sbus_translations; 422 sc->sc_nrange = 423 sizeof(sbus_translations)/sizeof(sbus_translations[0]); 424 break; 425 default: 426 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 427 } 428 429 /* 430 * Loop through ROM children, fixing any relative addresses 431 * and then configuring each device. 432 * `specials' is an array of device names that are treated 433 * specially: 434 */ 435 node0 = firstchild(busnode); 436 for (ssp = specials ; ssp != NULL && *(sp = *ssp) != 0; ssp++) { 437 if ((node = findnode(node0, sp)) == 0) { 438 panic("could not find %s amongst %s devices", 439 sp, busname); 440 } 441 442 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 443 node, bp, &sa) != 0) { 444 panic("sbus_attach: %s: incomplete", sp); 445 } 446 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 447 sbus_destroy_attach_args(&sa); 448 } 449 450 for (node = node0; node; node = nextsibling(node)) { 451 char *name = getpropstring(node, "name"); 452 for (ssp = specials, sp = NULL; 453 ssp != NULL && (sp = *ssp) != NULL; 454 ssp++) 455 if (strcmp(name, sp) == 0) 456 break; 457 458 if (sp != NULL) 459 /* Already configured as an "early" device */ 460 continue; 461 462 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 463 node, bp, &sa) != 0) { 464 printf("sbus_attach: %s: incomplete\n", name); 465 continue; 466 } 467 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 468 sbus_destroy_attach_args(&sa); 469 } 470 } 471 472 int 473 sbus_setup_attach_args(sc, bustag, dmatag, node, bp, sa) 474 struct sbus_softc *sc; 475 bus_space_tag_t bustag; 476 bus_dma_tag_t dmatag; 477 int node; 478 struct bootpath *bp; 479 struct sbus_attach_args *sa; 480 { 481 int n, error; 482 483 bzero(sa, sizeof(struct sbus_attach_args)); 484 error = getprop(node, "name", 1, &n, (void **)&sa->sa_name); 485 if (error != 0) 486 return (error); 487 sa->sa_name[n] = '\0'; 488 489 sa->sa_bustag = bustag; 490 sa->sa_dmatag = dmatag; 491 sa->sa_node = node; 492 sa->sa_bp = bp; 493 494 error = getprop(node, "reg", sizeof(struct sbus_reg), 495 &sa->sa_nreg, (void **)&sa->sa_reg); 496 if (error != 0) { 497 char buf[32]; 498 if (error != ENOENT || 499 !node_has_property(node, "device_type") || 500 strcmp(getpropstringA(node, "device_type", buf), 501 "hierarchical") != 0) 502 return (error); 503 } 504 for (n = 0; n < sa->sa_nreg; n++) { 505 /* Convert to relative addressing, if necessary */ 506 u_int32_t base = sa->sa_reg[n].sbr_offset; 507 if (SBUS_ABS(base)) { 508 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 509 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 510 } 511 } 512 513 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr)) != 0) 514 return (error); 515 516 error = getprop(node, "address", sizeof(u_int32_t), 517 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 518 if (error != 0 && error != ENOENT) 519 return (error); 520 521 return (0); 522 } 523 524 void 525 sbus_destroy_attach_args(sa) 526 struct sbus_attach_args *sa; 527 { 528 if (sa->sa_name != NULL) 529 free(sa->sa_name, M_DEVBUF); 530 531 if (sa->sa_nreg != 0) 532 free(sa->sa_reg, M_DEVBUF); 533 534 if (sa->sa_intr) 535 free(sa->sa_intr, M_DEVBUF); 536 537 if (sa->sa_promvaddrs) 538 free(sa->sa_promvaddrs, M_DEVBUF); 539 540 bzero(sa, sizeof(struct sbus_attach_args));/*DEBUG*/ 541 } 542 543 544 int 545 _sbus_bus_map(t, btype, offset, size, flags, vaddr, hp) 546 bus_space_tag_t t; 547 bus_type_t btype; 548 bus_addr_t offset; 549 bus_size_t size; 550 int flags; 551 vaddr_t vaddr; 552 bus_space_handle_t *hp; 553 { 554 struct sbus_softc *sc = t->cookie; 555 int slot = btype; 556 int i; 557 558 for (i = 0; i < sc->sc_nrange; i++) { 559 bus_addr_t paddr; 560 bus_type_t iospace; 561 562 if (sc->sc_range[i].cspace != slot) 563 continue; 564 565 /* We've found the connection to the parent bus */ 566 paddr = sc->sc_range[i].poffset + offset; 567 iospace = sc->sc_range[i].pspace; 568 return (bus_space_map2(sc->sc_bustag, iospace, paddr, 569 size, flags, vaddr, hp)); 570 } 571 572 return (EINVAL); 573 } 574 575 int 576 sbus_bus_mmap(t, btype, paddr, flags, hp) 577 bus_space_tag_t t; 578 bus_type_t btype; 579 bus_addr_t paddr; 580 int flags; 581 bus_space_handle_t *hp; 582 { 583 int slot = (int)btype; 584 int offset = (int)paddr; 585 struct sbus_softc *sc = t->cookie; 586 int i; 587 588 for (i = 0; i < sc->sc_nrange; i++) { 589 bus_addr_t paddr; 590 bus_addr_t iospace; 591 592 if (sc->sc_range[i].cspace != slot) 593 continue; 594 595 paddr = sc->sc_range[i].poffset + offset; 596 iospace = (bus_addr_t)sc->sc_range[i].pspace; 597 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 598 flags, hp)); 599 } 600 601 return (-1); 602 } 603 604 605 /* 606 * Each attached device calls sbus_establish after it initializes 607 * its sbusdev portion. 608 */ 609 void 610 sbus_establish(sd, dev) 611 register struct sbusdev *sd; 612 register struct device *dev; 613 { 614 register struct sbus_softc *sc; 615 register struct device *curdev; 616 617 /* 618 * We have to look for the sbus by name, since it is not necessarily 619 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 620 * We don't just use the device structure of the above-attached 621 * sbus, since we might (in the future) support multiple sbus's. 622 */ 623 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 624 if (!curdev || !curdev->dv_xname) 625 panic("sbus_establish: can't find sbus parent for %s", 626 sd->sd_dev->dv_xname 627 ? sd->sd_dev->dv_xname 628 : "<unknown>" ); 629 630 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 631 break; 632 } 633 sc = (struct sbus_softc *) curdev; 634 635 sd->sd_dev = dev; 636 sd->sd_bchain = sc->sc_sbdev; 637 sc->sc_sbdev = sd; 638 } 639 640 /* 641 * Reset the given sbus. (???) 642 */ 643 void 644 sbusreset(sbus) 645 int sbus; 646 { 647 register struct sbusdev *sd; 648 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 649 struct device *dev; 650 651 printf("reset %s:", sc->sc_dev.dv_xname); 652 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 653 if (sd->sd_reset) { 654 dev = sd->sd_dev; 655 (*sd->sd_reset)(dev); 656 printf(" %s", dev->dv_xname); 657 } 658 } 659 } 660 661 662 /* 663 * Get interrupt attributes for an Sbus device. 664 */ 665 int 666 sbus_get_intr(sc, node, ipp, np) 667 struct sbus_softc *sc; 668 int node; 669 struct sbus_intr **ipp; 670 int *np; 671 { 672 int error, n; 673 u_int32_t *ipl = NULL; 674 675 /* 676 * The `interrupts' property contains the Sbus interrupt level. 677 */ 678 if (getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 679 /* Change format to an `struct sbus_intr' array */ 680 struct sbus_intr *ip; 681 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 682 if (ip == NULL) 683 return (ENOMEM); 684 for (n = 0; n < *np; n++) { 685 ip[n].sbi_pri = ipl[n]; 686 ip[n].sbi_vec = 0; 687 } 688 free(ipl, M_DEVBUF); 689 *ipp = ip; 690 return (0); 691 } 692 693 /* 694 * Fall back on `intr' property. 695 */ 696 *ipp = NULL; 697 error = getprop(node, "intr", sizeof(struct sbus_intr), 698 np, (void **)ipp); 699 switch (error) { 700 case 0: 701 for (n = *np; n-- > 0;) { 702 (*ipp)[n].sbi_pri &= 0xf; 703 (*ipp)[n].sbi_pri |= SBUS_INTR_COMPAT; 704 } 705 break; 706 case ENOENT: 707 error = 0; 708 break; 709 } 710 711 return (error); 712 } 713 714 715 /* 716 * Install an interrupt handler for an Sbus device. 717 */ 718 void * 719 sbus_intr_establish(t, level, flags, handler, arg) 720 bus_space_tag_t t; 721 int level; 722 int flags; 723 int (*handler) __P((void *)); 724 void *arg; 725 { 726 struct sbus_softc *sc = t->cookie; 727 struct intrhand *ih; 728 int ipl; 729 730 ih = (struct intrhand *) 731 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 732 if (ih == NULL) 733 return (NULL); 734 735 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 736 ipl = level; 737 else if ((level & SBUS_INTR_COMPAT) != 0) 738 ipl = level & ~SBUS_INTR_COMPAT; 739 else 740 ipl = sc->sc_intr2ipl[level]; 741 742 ih->ih_fun = handler; 743 ih->ih_arg = arg; 744 if ((flags & BUS_INTR_ESTABLISH_FASTTRAP) != 0) 745 intr_fasttrap(ipl, (void (*)__P((void)))handler); 746 else 747 intr_establish(ipl, ih); 748 return (ih); 749 } 750 751 static bus_space_tag_t 752 sbus_alloc_bustag(sc) 753 struct sbus_softc *sc; 754 { 755 bus_space_tag_t sbt; 756 757 sbt = (bus_space_tag_t) 758 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 759 if (sbt == NULL) 760 return (NULL); 761 762 bzero(sbt, sizeof *sbt); 763 sbt->cookie = sc; 764 sbt->parent = sc->sc_bustag; 765 sbt->sparc_bus_map = _sbus_bus_map; 766 sbt->sparc_bus_mmap = sbus_bus_mmap; 767 sbt->sparc_intr_establish = sbus_intr_establish; 768 return (sbt); 769 } 770 771 int 772 sbus_error() 773 { 774 struct sbus_softc *sc = sbus_sc; 775 bus_space_handle_t bh = sc->sc_bh; 776 u_int32_t afsr, afva; 777 char bits[64]; 778 static int straytime, nstray; 779 int timesince; 780 781 afsr = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFSR_REG); 782 afva = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFAR_REG); 783 printf("sbus error:\n\tAFSR %s\n", 784 bitmask_snprintf(afsr, SBUS_AFSR_BITS, bits, sizeof(bits))); 785 printf("\taddress: 0x%x%x\n", afsr & SBUS_AFSR_PAH, afva); 786 787 /* For now, do the same dance as on stray interrupts */ 788 timesince = time.tv_sec - straytime; 789 if (timesince <= 10) { 790 if (++nstray > 9) 791 panic("too many SBus errors"); 792 } else { 793 straytime = time.tv_sec; 794 nstray = 1; 795 } 796 797 /* Unlock registers and clear interrupt */ 798 bus_space_write_4(sc->sc_bustag, bh, SBUS_AFSR_REG, afsr); 799 800 return (0); 801 } 802