1 /* $NetBSD: sbus.c,v 1.80 2020/11/22 03:55:33 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1992, 1993 34 * The Regents of the University of California. All rights reserved. 35 * 36 * This software was developed by the Computer Systems Engineering group 37 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 38 * contributed to Berkeley. 39 * 40 * All advertising materials mentioning features or use of this software 41 * must display the following acknowledgement: 42 * This product includes software developed by the University of 43 * California, Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 70 */ 71 72 /* 73 * Sbus stuff. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: sbus.c,v 1.80 2020/11/22 03:55:33 thorpej Exp $"); 78 79 #include <sys/param.h> 80 #include <sys/malloc.h> 81 #include <sys/kmem.h> 82 #include <sys/kernel.h> 83 #include <sys/systm.h> 84 #include <sys/device.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/autoconf.h> 89 #include <sys/bus.h> 90 #include <sparc/dev/sbusreg.h> 91 #include <dev/sbus/sbusvar.h> 92 #include <dev/sbus/xboxvar.h> 93 94 #include <sparc/sparc/iommuvar.h> 95 96 void sbusreset(int); 97 98 static int sbus_get_intr(struct sbus_softc *, int, 99 struct openprom_intr **, int *); 100 static void *sbus_intr_establish( 101 bus_space_tag_t, 102 int, /* Sbus interrupt level */ 103 int, /* `device class' priority */ 104 int (*)(void *), /* handler */ 105 void *, /* handler arg */ 106 void (*)(void)); /* fast handler */ 107 108 109 /* autoconfiguration driver */ 110 int sbus_match_mainbus(device_t, struct cfdata *, void *); 111 int sbus_match_iommu(device_t, struct cfdata *, void *); 112 int sbus_match_xbox(device_t, struct cfdata *, void *); 113 void sbus_attach_mainbus(device_t, device_t, void *); 114 void sbus_attach_iommu(device_t, device_t, void *); 115 void sbus_attach_xbox(device_t, device_t, void *); 116 117 #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D) 118 static int sbus_error(void); 119 extern int (*sbuserr_handler)(void); 120 #endif 121 122 CFATTACH_DECL_NEW(sbus_mainbus, sizeof(struct sbus_softc), 123 sbus_match_mainbus, sbus_attach_mainbus, NULL, NULL); 124 125 CFATTACH_DECL_NEW(sbus_iommu, sizeof(struct sbus_softc), 126 sbus_match_iommu, sbus_attach_iommu, NULL, NULL); 127 128 CFATTACH_DECL_NEW(sbus_xbox, sizeof(struct sbus_softc), 129 sbus_match_xbox, sbus_attach_xbox, NULL, NULL); 130 131 extern struct cfdriver sbus_cd; 132 133 static int sbus_mainbus_attached; 134 135 /* The "primary" Sbus */ 136 struct sbus_softc *sbus_sc; 137 138 /* If the PROM does not provide the `ranges' property, we make up our own */ 139 struct openprom_range sbus_translations[] = { 140 /* Assume a maximum of 4 Sbus slots, all mapped to on-board io space */ 141 { 0, 0, PMAP_OBIO, SBUS_ADDR(0,0), 1 << 25 }, 142 { 1, 0, PMAP_OBIO, SBUS_ADDR(1,0), 1 << 25 }, 143 { 2, 0, PMAP_OBIO, SBUS_ADDR(2,0), 1 << 25 }, 144 { 3, 0, PMAP_OBIO, SBUS_ADDR(3,0), 1 << 25 } 145 }; 146 147 /* 148 * Child devices receive the Sbus interrupt level in their attach 149 * arguments. We translate these to CPU IPLs using the following 150 * tables. Note: obio bus interrupt levels are identical to the 151 * processor IPL. 152 * 153 * The second set of tables is used when the Sbus interrupt level 154 * cannot be had from the PROM as an `interrupt' property. We then 155 * fall back on the `intr' property which contains the CPU IPL. 156 */ 157 158 /* Translate Sbus interrupt level to processor IPL */ 159 static int intr_sbus2ipl_4c[] = { 160 0, 1, 2, 3, 5, 7, 8, 9 161 }; 162 static int intr_sbus2ipl_4m[] = { 163 0, 2, 3, 5, 7, 9, 11, 13 164 }; 165 166 /* 167 * This value is or'ed into the attach args' interrupt level cookie 168 * if the interrupt level comes from an `intr' property, i.e. it is 169 * not an Sbus interrupt level. 170 */ 171 #define SBUS_INTR_COMPAT 0x80000000 172 173 174 /* 175 * Print the location of some sbus-attached device (called just 176 * before attaching that device). If `sbus' is not NULL, the 177 * device was found but not configured; print the sbus as well. 178 * Return UNCONF (config_find ignores this if the device was configured). 179 */ 180 int 181 sbus_print(void *args, const char *busname) 182 { 183 struct sbus_attach_args *sa = args; 184 int i; 185 186 if (busname) 187 aprint_normal("%s at %s", sa->sa_name, busname); 188 aprint_normal(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset); 189 for (i = 0; i < sa->sa_nintr; i++) { 190 uint32_t level = sa->sa_intr[i].oi_pri; 191 struct sbus_softc *sc = 192 (struct sbus_softc *) sa->sa_bustag->cookie; 193 194 aprint_normal(" level %d", level & ~SBUS_INTR_COMPAT); 195 if ((level & SBUS_INTR_COMPAT) == 0) { 196 int ipl = sc->sc_intr2ipl[level]; 197 if (ipl != level) 198 aprint_normal(" (ipl %d)", ipl); 199 } 200 } 201 return (UNCONF); 202 } 203 204 int 205 sbus_match_mainbus(device_t parent, struct cfdata *cf, void *aux) 206 { 207 struct mainbus_attach_args *ma = aux; 208 209 if (CPU_ISSUN4 || sbus_mainbus_attached) 210 return (0); 211 212 return (strcmp(cf->cf_name, ma->ma_name) == 0); 213 } 214 215 int 216 sbus_match_iommu(device_t parent, struct cfdata *cf, void *aux) 217 { 218 struct iommu_attach_args *ia = aux; 219 220 if (CPU_ISSUN4) 221 return (0); 222 223 return (strcmp(cf->cf_name, ia->iom_name) == 0); 224 } 225 226 int 227 sbus_match_xbox(device_t parent, struct cfdata *cf, void *aux) 228 { 229 struct xbox_attach_args *xa = aux; 230 231 if (CPU_ISSUN4) 232 return (0); 233 234 return (strcmp(cf->cf_name, xa->xa_name) == 0); 235 } 236 237 /* 238 * Attach an Sbus. 239 */ 240 void 241 sbus_attach_mainbus(device_t parent, device_t self, void *aux) 242 { 243 struct sbus_softc *sc = device_private(self); 244 struct mainbus_attach_args *ma = aux; 245 int node = ma->ma_node; 246 247 sbus_mainbus_attached = 1; 248 249 sc->sc_dev = self; 250 sc->sc_bustag = ma->ma_bustag; 251 sc->sc_dmatag = ma->ma_dmatag; 252 253 #if 0 /* sbus at mainbus (sun4c): `reg' prop is not control space */ 254 if (ma->ma_size == 0) 255 printf("%s: no Sbus registers", device_xname(self)); 256 257 if (bus_space_map(ma->ma_bustag, 258 ma->ma_paddr, 259 ma->ma_size, 260 BUS_SPACE_MAP_LINEAR, 261 &sc->sc_bh) != 0) { 262 panic("%s: can't map sbusbusreg", device_xname(self)); 263 } 264 #endif 265 266 /* Setup interrupt translation tables */ 267 sc->sc_intr2ipl = CPU_ISSUN4C 268 ? intr_sbus2ipl_4c 269 : intr_sbus2ipl_4m; 270 271 /* 272 * Record clock frequency for synchronous SCSI. 273 * IS THIS THE CORRECT DEFAULT?? 274 */ 275 sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000); 276 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 277 278 sbus_sc = sc; 279 sbus_attach_common(sc, "sbus", node, NULL); 280 } 281 282 283 void 284 sbus_attach_iommu(device_t parent, device_t self, void *aux) 285 { 286 struct sbus_softc *sc = device_private(self); 287 struct iommu_attach_args *ia = aux; 288 int node = ia->iom_node; 289 290 sc->sc_dev = self; 291 sc->sc_bustag = ia->iom_bustag; 292 sc->sc_dmatag = ia->iom_dmatag; 293 294 if (ia->iom_nreg == 0) 295 panic("%s: no Sbus registers", device_xname(self)); 296 297 if (bus_space_map(ia->iom_bustag, 298 BUS_ADDR(ia->iom_reg[0].oa_space, 299 ia->iom_reg[0].oa_base), 300 (bus_size_t)ia->iom_reg[0].oa_size, 301 BUS_SPACE_MAP_LINEAR, 302 &sc->sc_bh) != 0) { 303 panic("%s: can't map sbusbusreg", device_xname(self)); 304 } 305 306 /* Setup interrupt translation tables */ 307 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 308 309 /* 310 * Record clock frequency for synchronous SCSI. 311 * IS THIS THE CORRECT DEFAULT?? 312 */ 313 sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000); 314 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 315 316 sbus_sc = sc; 317 #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D) 318 sbuserr_handler = sbus_error; 319 #endif 320 sbus_attach_common(sc, "sbus", node, NULL); 321 } 322 323 void 324 sbus_attach_xbox(device_t parent, device_t self, void *aux) 325 { 326 struct sbus_softc *sc = device_private(self); 327 struct xbox_attach_args *xa = aux; 328 int node = xa->xa_node; 329 330 sc->sc_bustag = xa->xa_bustag; 331 sc->sc_dmatag = xa->xa_dmatag; 332 333 /* Setup interrupt translation tables */ 334 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 335 336 /* 337 * Record clock frequency for synchronous SCSI. 338 * IS THIS THE CORRECT DEFAULT?? 339 */ 340 sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000); 341 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 342 343 sbus_attach_common(sc, "sbus", node, NULL); 344 } 345 346 void 347 sbus_attach_common(struct sbus_softc *sc, const char *busname, int busnode, 348 const char * const *specials) 349 { 350 int node0, node, error; 351 const char *sp; 352 const char *const *ssp; 353 bus_space_tag_t sbt; 354 struct sbus_attach_args sa; 355 356 if ((sbt = bus_space_tag_alloc(sc->sc_bustag, sc)) == NULL) { 357 printf("%s: attach: out of memory\n", 358 device_xname(sc->sc_dev)); 359 return; 360 } 361 sbt->sparc_intr_establish = sbus_intr_establish; 362 363 /* 364 * Get the SBus burst transfer size if burst transfers are supported 365 */ 366 sc->sc_burst = prom_getpropint(busnode, "burst-sizes", 0); 367 368 369 if (CPU_ISSUN4M) { 370 /* 371 * Some models (e.g. SS20) erroneously report 64-bit 372 * burst capability. We mask it out here for all SUN4Ms, 373 * since probably no member of that class supports 374 * 64-bit Sbus bursts. 375 */ 376 sc->sc_burst &= ~SBUS_BURST_64; 377 } 378 379 /* 380 * Collect address translations from the OBP. 381 */ 382 error = prom_getprop(busnode, "ranges", sizeof(struct rom_range), 383 &sbt->nranges, &sbt->ranges); 384 switch (error) { 385 case 0: 386 break; 387 case ENOENT: 388 /* Fall back to our own `range' construction */ 389 sbt->ranges = sbus_translations; 390 sbt->nranges = 391 sizeof(sbus_translations)/sizeof(sbus_translations[0]); 392 break; 393 default: 394 panic("%s: error getting ranges property", 395 device_xname(sc->sc_dev)); 396 } 397 398 /* 399 * Loop through ROM children, fixing any relative addresses 400 * and then configuring each device. 401 * `specials' is an array of device names that are treated 402 * specially: 403 */ 404 node0 = firstchild(busnode); 405 for (ssp = specials ; ssp != NULL && *(sp = *ssp) != 0; ssp++) { 406 if ((node = findnode(node0, sp)) == 0) { 407 panic("could not find %s amongst %s devices", 408 sp, busname); 409 } 410 411 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 412 node, &sa) != 0) { 413 panic("sbus_attach: %s: incomplete", sp); 414 } 415 (void) config_found(sc->sc_dev, (void *)&sa, sbus_print); 416 sbus_destroy_attach_args(&sa); 417 } 418 419 for (node = node0; node; node = nextsibling(node)) { 420 char *name = prom_getpropstring(node, "name"); 421 for (ssp = specials, sp = NULL; 422 ssp != NULL && (sp = *ssp) != NULL; 423 ssp++) 424 if (strcmp(name, sp) == 0) 425 break; 426 427 if (sp != NULL) 428 /* Already configured as an "early" device */ 429 continue; 430 431 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 432 node, &sa) != 0) { 433 printf("sbus_attach: %s: incomplete\n", name); 434 continue; 435 } 436 (void) config_found(sc->sc_dev, (void *)&sa, sbus_print); 437 sbus_destroy_attach_args(&sa); 438 } 439 } 440 441 int 442 sbus_setup_attach_args(struct sbus_softc *sc, 443 bus_space_tag_t bustag, bus_dma_tag_t dmatag, int node, 444 struct sbus_attach_args *sa) 445 { 446 int n, error; 447 448 memset(sa, 0, sizeof(struct sbus_attach_args)); 449 error = prom_getprop(node, "name", 1, &n, &sa->sa_name); 450 if (error != 0) 451 return (error); 452 KASSERT(sa->sa_name[n-1] == '\0'); 453 454 sa->sa_bustag = bustag; 455 sa->sa_dmatag = dmatag; 456 sa->sa_node = node; 457 sa->sa_frequency = sc->sc_clockfreq; 458 459 error = prom_getprop(node, "reg", sizeof(struct openprom_addr), 460 &sa->sa_nreg, &sa->sa_reg); 461 if (error != 0) { 462 char buf[32]; 463 if (error != ENOENT || 464 !node_has_property(node, "device_type") || 465 strcmp(prom_getpropstringA(node, "device_type", buf, sizeof buf), 466 "hierarchical") != 0) 467 return (error); 468 } 469 for (n = 0; n < sa->sa_nreg; n++) { 470 /* Convert to relative addressing, if necessary */ 471 uint32_t base = sa->sa_reg[n].oa_base; 472 if (SBUS_ABS(base)) { 473 sa->sa_reg[n].oa_space = SBUS_ABS_TO_SLOT(base); 474 sa->sa_reg[n].oa_base = SBUS_ABS_TO_OFFSET(base); 475 } 476 } 477 478 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr)) != 0) 479 return (error); 480 481 error = prom_getprop(node, "address", sizeof(uint32_t), 482 &sa->sa_npromvaddrs, &sa->sa_promvaddrs); 483 if (error != 0 && error != ENOENT) 484 return (error); 485 486 return (0); 487 } 488 489 void 490 sbus_destroy_attach_args(struct sbus_attach_args *sa) 491 { 492 493 if (sa->sa_name != NULL) 494 free(sa->sa_name, M_DEVBUF); 495 496 if (sa->sa_nreg != 0) 497 free(sa->sa_reg, M_DEVBUF); 498 499 if (sa->sa_intr) 500 free(sa->sa_intr, M_DEVBUF); 501 502 if (sa->sa_promvaddrs) 503 free(sa->sa_promvaddrs, M_DEVBUF); 504 505 memset(sa, 0, sizeof(struct sbus_attach_args));/*DEBUG*/ 506 } 507 508 bus_addr_t 509 sbus_bus_addr(bus_space_tag_t t, u_int btype, u_int offset) 510 { 511 512 /* XXX: sbus_bus_addr should be g/c'ed */ 513 return (BUS_ADDR(btype, offset)); 514 } 515 516 517 /* 518 * Get interrupt attributes for an Sbus device. 519 */ 520 static int 521 sbus_get_intr(struct sbus_softc *sc, int node, 522 struct openprom_intr **ipp, int *np) 523 { 524 int error, n; 525 uint32_t *ipl = NULL; 526 527 /* 528 * The `interrupts' property contains the Sbus interrupt level. 529 */ 530 if (prom_getprop(node, "interrupts", sizeof(int), np, 531 &ipl) == 0) { 532 /* Change format to an `struct openprom_intr' array */ 533 struct openprom_intr *ip; 534 ip = malloc(*np * sizeof(struct openprom_intr), M_DEVBUF, 535 M_WAITOK); 536 for (n = 0; n < *np; n++) { 537 ip[n].oi_pri = ipl[n]; 538 ip[n].oi_vec = 0; 539 } 540 free(ipl, M_DEVBUF); 541 *ipp = ip; 542 return (0); 543 } 544 545 /* 546 * Fall back on `intr' property. 547 */ 548 *ipp = NULL; 549 error = prom_getprop(node, "intr", sizeof(struct openprom_intr), 550 np, ipp); 551 switch (error) { 552 case 0: 553 for (n = *np; n-- > 0;) { 554 (*ipp)[n].oi_pri &= 0xf; 555 (*ipp)[n].oi_pri |= SBUS_INTR_COMPAT; 556 } 557 break; 558 case ENOENT: 559 error = 0; 560 break; 561 } 562 563 return (error); 564 } 565 566 567 /* 568 * Install an interrupt handler for an Sbus device. 569 */ 570 static void * 571 sbus_intr_establish(bus_space_tag_t t, int pri, int level, 572 int (*handler)(void *), void *arg, 573 void (*fastvec)(void)) 574 { 575 struct sbus_softc *sc = t->cookie; 576 struct intrhand *ih; 577 int pil; 578 579 ih = kmem_alloc(sizeof(struct intrhand), KM_SLEEP); 580 581 /* 582 * Translate Sbus interrupt priority to CPU interrupt level 583 */ 584 if ((pri & SBUS_INTR_COMPAT) != 0) 585 pil = pri & ~SBUS_INTR_COMPAT; 586 else 587 pil = sc->sc_intr2ipl[pri]; 588 589 ih->ih_fun = handler; 590 ih->ih_arg = arg; 591 intr_establish(pil, level, ih, fastvec, false); 592 return (ih); 593 } 594 595 #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D) 596 static int 597 sbus_error(void) 598 { 599 struct sbus_softc *sc = sbus_sc; 600 bus_space_handle_t bh = sc->sc_bh; 601 uint32_t afsr, afva; 602 char bits[64]; 603 static int straytime, nstray; 604 int timesince; 605 606 afsr = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFSR_REG); 607 afva = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFAR_REG); 608 snprintb(bits, sizeof(bits), SBUS_AFSR_BITS, afsr); 609 printf("sbus error:\n\tAFSR %s\n", bits); 610 printf("\taddress: 0x%x%x\n", afsr & SBUS_AFSR_PAH, afva); 611 612 /* For now, do the same dance as on stray interrupts */ 613 timesince = time_uptime - straytime; 614 if (timesince <= 10) { 615 if (++nstray > 9) 616 panic("too many SBus errors"); 617 } else { 618 straytime = time_uptime; 619 nstray = 1; 620 } 621 622 /* Unlock registers and clear interrupt */ 623 bus_space_write_4(sc->sc_bustag, bh, SBUS_AFSR_REG, afsr); 624 625 return (0); 626 } 627 #endif 628