1 /* $NetBSD: sbus.c,v 1.60 2004/03/17 17:04:59 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. Neither the name of the University nor the names of its contributors 61 * may be used to endorse or promote products derived from this software 62 * without specific prior written permission. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 * 76 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 77 */ 78 79 /* 80 * Sbus stuff. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: sbus.c,v 1.60 2004/03/17 17:04:59 pk Exp $"); 85 86 #include <sys/param.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #include <machine/autoconf.h> 95 #include <machine/bus.h> 96 #include <sparc/dev/sbusreg.h> 97 #include <dev/sbus/sbusvar.h> 98 #include <dev/sbus/xboxvar.h> 99 100 #include <sparc/sparc/iommuvar.h> 101 102 void sbusreset __P((int)); 103 104 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 105 static int sbus_get_intr __P((struct sbus_softc *, int, 106 struct openprom_intr **, int *)); 107 static void *sbus_intr_establish __P(( 108 bus_space_tag_t, 109 int, /*Sbus interrupt level*/ 110 int, /*`device class' priority*/ 111 int (*) __P((void *)), /*handler*/ 112 void *, /*handler arg*/ 113 void (*) __P((void)))); /*fast handler*/ 114 115 116 /* autoconfiguration driver */ 117 int sbus_match_mainbus __P((struct device *, struct cfdata *, void *)); 118 int sbus_match_iommu __P((struct device *, struct cfdata *, void *)); 119 int sbus_match_xbox __P((struct device *, struct cfdata *, void *)); 120 void sbus_attach_mainbus __P((struct device *, struct device *, void *)); 121 void sbus_attach_iommu __P((struct device *, struct device *, void *)); 122 void sbus_attach_xbox __P((struct device *, struct device *, void *)); 123 124 static int sbus_error __P((void)); 125 int (*sbuserr_handler) __P((void)); 126 127 CFATTACH_DECL(sbus_mainbus, sizeof(struct sbus_softc), 128 sbus_match_mainbus, sbus_attach_mainbus, NULL, NULL); 129 130 CFATTACH_DECL(sbus_iommu, sizeof(struct sbus_softc), 131 sbus_match_iommu, sbus_attach_iommu, NULL, NULL); 132 133 CFATTACH_DECL(sbus_xbox, sizeof(struct sbus_softc), 134 sbus_match_xbox, sbus_attach_xbox, NULL, NULL); 135 136 extern struct cfdriver sbus_cd; 137 138 /* The "primary" Sbus */ 139 struct sbus_softc *sbus_sc; 140 141 /* If the PROM does not provide the `ranges' property, we make up our own */ 142 struct openprom_range sbus_translations[] = { 143 /* Assume a maximum of 4 Sbus slots, all mapped to on-board io space */ 144 { 0, 0, PMAP_OBIO, SBUS_ADDR(0,0), 1 << 25 }, 145 { 1, 0, PMAP_OBIO, SBUS_ADDR(1,0), 1 << 25 }, 146 { 2, 0, PMAP_OBIO, SBUS_ADDR(2,0), 1 << 25 }, 147 { 3, 0, PMAP_OBIO, SBUS_ADDR(3,0), 1 << 25 } 148 }; 149 150 /* 151 * Child devices receive the Sbus interrupt level in their attach 152 * arguments. We translate these to CPU IPLs using the following 153 * tables. Note: obio bus interrupt levels are identical to the 154 * processor IPL. 155 * 156 * The second set of tables is used when the Sbus interrupt level 157 * cannot be had from the PROM as an `interrupt' property. We then 158 * fall back on the `intr' property which contains the CPU IPL. 159 */ 160 161 /* Translate Sbus interrupt level to processor IPL */ 162 static int intr_sbus2ipl_4c[] = { 163 0, 1, 2, 3, 5, 7, 8, 9 164 }; 165 static int intr_sbus2ipl_4m[] = { 166 0, 2, 3, 5, 7, 9, 11, 13 167 }; 168 169 /* 170 * This value is or'ed into the attach args' interrupt level cookie 171 * if the interrupt level comes from an `intr' property, i.e. it is 172 * not an Sbus interrupt level. 173 */ 174 #define SBUS_INTR_COMPAT 0x80000000 175 176 177 /* 178 * Print the location of some sbus-attached device (called just 179 * before attaching that device). If `sbus' is not NULL, the 180 * device was found but not configured; print the sbus as well. 181 * Return UNCONF (config_find ignores this if the device was configured). 182 */ 183 int 184 sbus_print(args, busname) 185 void *args; 186 const char *busname; 187 { 188 struct sbus_attach_args *sa = args; 189 int i; 190 191 if (busname) 192 aprint_normal("%s at %s", sa->sa_name, busname); 193 aprint_normal(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset); 194 for (i = 0; i < sa->sa_nintr; i++) { 195 u_int32_t level = sa->sa_intr[i].oi_pri; 196 struct sbus_softc *sc = 197 (struct sbus_softc *) sa->sa_bustag->cookie; 198 199 aprint_normal(" level %d", level & ~SBUS_INTR_COMPAT); 200 if ((level & SBUS_INTR_COMPAT) == 0) { 201 int ipl = sc->sc_intr2ipl[level]; 202 if (ipl != level) 203 aprint_normal(" (ipl %d)", ipl); 204 } 205 } 206 return (UNCONF); 207 } 208 209 int 210 sbus_match_mainbus(parent, cf, aux) 211 struct device *parent; 212 struct cfdata *cf; 213 void *aux; 214 { 215 struct mainbus_attach_args *ma = aux; 216 217 if (CPU_ISSUN4) 218 return (0); 219 220 return (strcmp(cf->cf_name, ma->ma_name) == 0); 221 } 222 223 int 224 sbus_match_iommu(parent, cf, aux) 225 struct device *parent; 226 struct cfdata *cf; 227 void *aux; 228 { 229 struct iommu_attach_args *ia = aux; 230 231 if (CPU_ISSUN4) 232 return (0); 233 234 return (strcmp(cf->cf_name, ia->iom_name) == 0); 235 } 236 237 int 238 sbus_match_xbox(parent, cf, aux) 239 struct device *parent; 240 struct cfdata *cf; 241 void *aux; 242 { 243 struct xbox_attach_args *xa = aux; 244 245 if (CPU_ISSUN4) 246 return (0); 247 248 return (strcmp(cf->cf_name, xa->xa_name) == 0); 249 } 250 251 /* 252 * Attach an Sbus. 253 */ 254 void 255 sbus_attach_mainbus(parent, self, aux) 256 struct device *parent; 257 struct device *self; 258 void *aux; 259 { 260 struct sbus_softc *sc = (struct sbus_softc *)self; 261 struct mainbus_attach_args *ma = aux; 262 int node = ma->ma_node; 263 264 /* 265 * XXX there is only one Sbus, for now -- do not know how to 266 * address children on others 267 */ 268 if (sc->sc_dev.dv_unit > 0) { 269 printf(" unsupported\n"); 270 return; 271 } 272 273 sc->sc_bustag = ma->ma_bustag; 274 sc->sc_dmatag = ma->ma_dmatag; 275 276 #if 0 /* sbus at mainbus (sun4c): `reg' prop is not control space */ 277 if (ma->ma_size == 0) 278 printf("%s: no Sbus registers", self->dv_xname); 279 280 if (bus_space_map(ma->ma_bustag, 281 ma->ma_paddr, 282 ma->ma_size, 283 BUS_SPACE_MAP_LINEAR, 284 &sc->sc_bh) != 0) { 285 panic("%s: can't map sbusbusreg", self->dv_xname); 286 } 287 #endif 288 289 /* Setup interrupt translation tables */ 290 sc->sc_intr2ipl = CPU_ISSUN4C 291 ? intr_sbus2ipl_4c 292 : intr_sbus2ipl_4m; 293 294 /* 295 * Record clock frequency for synchronous SCSI. 296 * IS THIS THE CORRECT DEFAULT?? 297 */ 298 sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000); 299 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 300 301 sbus_sc = sc; 302 sbus_attach_common(sc, "sbus", node, NULL); 303 } 304 305 306 void 307 sbus_attach_iommu(parent, self, aux) 308 struct device *parent; 309 struct device *self; 310 void *aux; 311 { 312 struct sbus_softc *sc = (struct sbus_softc *)self; 313 struct iommu_attach_args *ia = aux; 314 int node = ia->iom_node; 315 316 sc->sc_bustag = ia->iom_bustag; 317 sc->sc_dmatag = ia->iom_dmatag; 318 319 if (ia->iom_nreg == 0) 320 panic("%s: no Sbus registers", self->dv_xname); 321 322 if (bus_space_map(ia->iom_bustag, 323 BUS_ADDR(ia->iom_reg[0].oa_space, 324 ia->iom_reg[0].oa_base), 325 (bus_size_t)ia->iom_reg[0].oa_size, 326 BUS_SPACE_MAP_LINEAR, 327 &sc->sc_bh) != 0) { 328 panic("%s: can't map sbusbusreg", self->dv_xname); 329 } 330 331 /* Setup interrupt translation tables */ 332 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 333 334 /* 335 * Record clock frequency for synchronous SCSI. 336 * IS THIS THE CORRECT DEFAULT?? 337 */ 338 sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000); 339 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 340 341 sbus_sc = sc; 342 sbuserr_handler = sbus_error; 343 sbus_attach_common(sc, "sbus", node, NULL); 344 } 345 346 void 347 sbus_attach_xbox(parent, self, aux) 348 struct device *parent; 349 struct device *self; 350 void *aux; 351 { 352 struct sbus_softc *sc = (struct sbus_softc *)self; 353 struct xbox_attach_args *xa = aux; 354 int node = xa->xa_node; 355 356 sc->sc_bustag = xa->xa_bustag; 357 sc->sc_dmatag = xa->xa_dmatag; 358 359 /* Setup interrupt translation tables */ 360 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 361 362 /* 363 * Record clock frequency for synchronous SCSI. 364 * IS THIS THE CORRECT DEFAULT?? 365 */ 366 sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000); 367 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 368 369 sbus_attach_common(sc, "sbus", node, NULL); 370 } 371 372 void 373 sbus_attach_common(sc, busname, busnode, specials) 374 struct sbus_softc *sc; 375 char *busname; 376 int busnode; 377 const char * const *specials; 378 { 379 int node0, node, error; 380 const char *sp; 381 const char *const *ssp; 382 bus_space_tag_t sbt; 383 struct sbus_attach_args sa; 384 385 sbt = sbus_alloc_bustag(sc); 386 387 /* 388 * Get the SBus burst transfer size if burst transfers are supported 389 */ 390 sc->sc_burst = prom_getpropint(busnode, "burst-sizes", 0); 391 392 393 if (CPU_ISSUN4M) { 394 /* 395 * Some models (e.g. SS20) erroneously report 64-bit 396 * burst capability. We mask it out here for all SUN4Ms, 397 * since probably no member of that class supports 398 * 64-bit Sbus bursts. 399 */ 400 sc->sc_burst &= ~SBUS_BURST_64; 401 } 402 403 /* 404 * Collect address translations from the OBP. 405 */ 406 error = prom_getprop(busnode, "ranges", sizeof(struct rom_range), 407 &sbt->nranges, &sbt->ranges); 408 switch (error) { 409 case 0: 410 break; 411 case ENOENT: 412 /* Fall back to our own `range' construction */ 413 sbt->ranges = sbus_translations; 414 sbt->nranges = 415 sizeof(sbus_translations)/sizeof(sbus_translations[0]); 416 break; 417 default: 418 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 419 } 420 421 /* 422 * Loop through ROM children, fixing any relative addresses 423 * and then configuring each device. 424 * `specials' is an array of device names that are treated 425 * specially: 426 */ 427 node0 = firstchild(busnode); 428 for (ssp = specials ; ssp != NULL && *(sp = *ssp) != 0; ssp++) { 429 if ((node = findnode(node0, sp)) == 0) { 430 panic("could not find %s amongst %s devices", 431 sp, busname); 432 } 433 434 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 435 node, &sa) != 0) { 436 panic("sbus_attach: %s: incomplete", sp); 437 } 438 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 439 sbus_destroy_attach_args(&sa); 440 } 441 442 for (node = node0; node; node = nextsibling(node)) { 443 char *name = prom_getpropstring(node, "name"); 444 for (ssp = specials, sp = NULL; 445 ssp != NULL && (sp = *ssp) != NULL; 446 ssp++) 447 if (strcmp(name, sp) == 0) 448 break; 449 450 if (sp != NULL) 451 /* Already configured as an "early" device */ 452 continue; 453 454 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 455 node, &sa) != 0) { 456 printf("sbus_attach: %s: incomplete\n", name); 457 continue; 458 } 459 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 460 sbus_destroy_attach_args(&sa); 461 } 462 } 463 464 int 465 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 466 struct sbus_softc *sc; 467 bus_space_tag_t bustag; 468 bus_dma_tag_t dmatag; 469 int node; 470 struct sbus_attach_args *sa; 471 { 472 int n, error; 473 474 bzero(sa, sizeof(struct sbus_attach_args)); 475 error = prom_getprop(node, "name", 1, &n, &sa->sa_name); 476 if (error != 0) 477 return (error); 478 sa->sa_name[n] = '\0'; 479 480 sa->sa_bustag = bustag; 481 sa->sa_dmatag = dmatag; 482 sa->sa_node = node; 483 sa->sa_frequency = sc->sc_clockfreq; 484 485 error = prom_getprop(node, "reg", sizeof(struct openprom_addr), 486 &sa->sa_nreg, &sa->sa_reg); 487 if (error != 0) { 488 char buf[32]; 489 if (error != ENOENT || 490 !node_has_property(node, "device_type") || 491 strcmp(prom_getpropstringA(node, "device_type", buf, sizeof buf), 492 "hierarchical") != 0) 493 return (error); 494 } 495 for (n = 0; n < sa->sa_nreg; n++) { 496 /* Convert to relative addressing, if necessary */ 497 u_int32_t base = sa->sa_reg[n].oa_base; 498 if (SBUS_ABS(base)) { 499 sa->sa_reg[n].oa_space = SBUS_ABS_TO_SLOT(base); 500 sa->sa_reg[n].oa_base = SBUS_ABS_TO_OFFSET(base); 501 } 502 } 503 504 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr)) != 0) 505 return (error); 506 507 error = prom_getprop(node, "address", sizeof(u_int32_t), 508 &sa->sa_npromvaddrs, &sa->sa_promvaddrs); 509 if (error != 0 && error != ENOENT) 510 return (error); 511 512 return (0); 513 } 514 515 void 516 sbus_destroy_attach_args(sa) 517 struct sbus_attach_args *sa; 518 { 519 if (sa->sa_name != NULL) 520 free(sa->sa_name, M_DEVBUF); 521 522 if (sa->sa_nreg != 0) 523 free(sa->sa_reg, M_DEVBUF); 524 525 if (sa->sa_intr) 526 free(sa->sa_intr, M_DEVBUF); 527 528 if (sa->sa_promvaddrs) 529 free(sa->sa_promvaddrs, M_DEVBUF); 530 531 bzero(sa, sizeof(struct sbus_attach_args));/*DEBUG*/ 532 } 533 534 bus_addr_t 535 sbus_bus_addr(t, btype, offset) 536 bus_space_tag_t t; 537 u_int btype; 538 u_int offset; 539 { 540 541 /* XXX: sbus_bus_addr should be g/c'ed */ 542 return (BUS_ADDR(btype, offset)); 543 } 544 545 546 /* 547 * Each attached device calls sbus_establish after it initializes 548 * its sbusdev portion. 549 */ 550 void 551 sbus_establish(sd, dev) 552 register struct sbusdev *sd; 553 register struct device *dev; 554 { 555 register struct sbus_softc *sc; 556 register struct device *curdev; 557 558 /* 559 * We have to look for the sbus by name, since it is not necessarily 560 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 561 * We don't just use the device structure of the above-attached 562 * sbus, since we might (in the future) support multiple sbus's. 563 */ 564 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 565 if (!curdev || !curdev->dv_xname) 566 panic("sbus_establish: can't find sbus parent for %s", 567 sd->sd_dev->dv_xname 568 ? sd->sd_dev->dv_xname 569 : "<unknown>" ); 570 571 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 572 break; 573 } 574 sc = (struct sbus_softc *) curdev; 575 576 sd->sd_dev = dev; 577 sd->sd_bchain = sc->sc_sbdev; 578 sc->sc_sbdev = sd; 579 } 580 581 /* 582 * Reset the given sbus. (???) 583 */ 584 void 585 sbusreset(sbus) 586 int sbus; 587 { 588 register struct sbusdev *sd; 589 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 590 struct device *dev; 591 592 printf("reset %s:", sc->sc_dev.dv_xname); 593 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 594 if (sd->sd_reset) { 595 dev = sd->sd_dev; 596 (*sd->sd_reset)(dev); 597 printf(" %s", dev->dv_xname); 598 } 599 } 600 } 601 602 603 /* 604 * Get interrupt attributes for an Sbus device. 605 */ 606 int 607 sbus_get_intr(sc, node, ipp, np) 608 struct sbus_softc *sc; 609 int node; 610 struct openprom_intr **ipp; 611 int *np; 612 { 613 int error, n; 614 u_int32_t *ipl = NULL; 615 616 /* 617 * The `interrupts' property contains the Sbus interrupt level. 618 */ 619 if (prom_getprop(node, "interrupts", sizeof(int), np, 620 &ipl) == 0) { 621 /* Change format to an `struct openprom_intr' array */ 622 struct openprom_intr *ip; 623 ip = malloc(*np * sizeof(struct openprom_intr), M_DEVBUF, 624 M_NOWAIT); 625 if (ip == NULL) { 626 free(ipl, M_DEVBUF); 627 return (ENOMEM); 628 } 629 for (n = 0; n < *np; n++) { 630 ip[n].oi_pri = ipl[n]; 631 ip[n].oi_vec = 0; 632 } 633 free(ipl, M_DEVBUF); 634 *ipp = ip; 635 return (0); 636 } 637 638 /* 639 * Fall back on `intr' property. 640 */ 641 *ipp = NULL; 642 error = prom_getprop(node, "intr", sizeof(struct openprom_intr), 643 np, ipp); 644 switch (error) { 645 case 0: 646 for (n = *np; n-- > 0;) { 647 (*ipp)[n].oi_pri &= 0xf; 648 (*ipp)[n].oi_pri |= SBUS_INTR_COMPAT; 649 } 650 break; 651 case ENOENT: 652 error = 0; 653 break; 654 } 655 656 return (error); 657 } 658 659 660 /* 661 * Install an interrupt handler for an Sbus device. 662 */ 663 void * 664 sbus_intr_establish(t, pri, level, handler, arg, fastvec) 665 bus_space_tag_t t; 666 int pri; 667 int level; 668 int (*handler) __P((void *)); 669 void *arg; 670 void (*fastvec) __P((void)); 671 { 672 struct sbus_softc *sc = t->cookie; 673 struct intrhand *ih; 674 int pil; 675 676 ih = (struct intrhand *) 677 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 678 if (ih == NULL) 679 return (NULL); 680 681 /* 682 * Translate Sbus interrupt priority to CPU interrupt level 683 */ 684 if ((pri & SBUS_INTR_COMPAT) != 0) 685 pil = pri & ~SBUS_INTR_COMPAT; 686 else 687 pil = sc->sc_intr2ipl[pri]; 688 689 ih->ih_fun = handler; 690 ih->ih_arg = arg; 691 intr_establish(pil, level, ih, fastvec); 692 return (ih); 693 } 694 695 static bus_space_tag_t 696 sbus_alloc_bustag(sc) 697 struct sbus_softc *sc; 698 { 699 bus_space_tag_t sbt; 700 701 sbt = (bus_space_tag_t) 702 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 703 if (sbt == NULL) 704 return (NULL); 705 706 bzero(sbt, sizeof *sbt); 707 sbt->cookie = sc; 708 sbt->parent = sc->sc_bustag; 709 sbt->sparc_bus_map = sc->sc_bustag->sparc_bus_map; 710 sbt->sparc_bus_mmap = sc->sc_bustag->sparc_bus_mmap; 711 sbt->sparc_intr_establish = sbus_intr_establish; 712 return (sbt); 713 } 714 715 int 716 sbus_error() 717 { 718 struct sbus_softc *sc = sbus_sc; 719 bus_space_handle_t bh = sc->sc_bh; 720 u_int32_t afsr, afva; 721 char bits[64]; 722 static int straytime, nstray; 723 int timesince; 724 725 afsr = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFSR_REG); 726 afva = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFAR_REG); 727 printf("sbus error:\n\tAFSR %s\n", 728 bitmask_snprintf(afsr, SBUS_AFSR_BITS, bits, sizeof(bits))); 729 printf("\taddress: 0x%x%x\n", afsr & SBUS_AFSR_PAH, afva); 730 731 /* For now, do the same dance as on stray interrupts */ 732 timesince = time.tv_sec - straytime; 733 if (timesince <= 10) { 734 if (++nstray > 9) 735 panic("too many SBus errors"); 736 } else { 737 straytime = time.tv_sec; 738 nstray = 1; 739 } 740 741 /* Unlock registers and clear interrupt */ 742 bus_space_write_4(sc->sc_bustag, bh, SBUS_AFSR_REG, afsr); 743 744 return (0); 745 } 746