1 /* $NetBSD: scr.c,v 1.22 2007/03/04 06:00:43 christos Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** 39 ** FACILITY: 40 ** 41 ** Driver for smart card 42 ** 43 ** ABSTRACT: 44 ** 45 ** The driver provides access to a Smart Card for the DNARD. 46 ** 47 ** There is no Smart Card silicon. Several i/o pins 48 ** connect to the pads on the Smart Card, and the driver is 49 ** is responsible for driving the signals in accordance with 50 ** ISO 7816-3 (the Smart Card spec) 51 ** 52 ** This driver puts a high load on the system due to the need 53 ** to interrupt at a high rate (up to 50 kHz) during bit detection. 54 ** 55 ** 56 ** The driver is dived into the standard top half ioctl, and bottom 57 ** half interrupt. The interrupt is FIQ, which requires its own stack. 58 ** disable_interrupts and restore_interrupts must be used to protect from 59 ** a FIQ. Since splxxx functions do not use this, the bottom half cannot 60 ** use any standard functions (ie like wakeup, timeout, etc. 61 ** Thus the communication from the bottom half 62 ** to the top half uses a "done" bit called masterDone. This bit 63 ** is set by the master state machine when all bottom half work is 64 ** complete. The top half checks/sleeps on this masterDone bit. 65 ** 66 ** The FIQ is driven by Timer 2 (T2)in the sequoia. All times are 67 ** referenced to T2 counts. 68 ** 69 ** The bottom half is done as a several linked state machines. 70 ** The top level machine is the maserSM (ie master State Machine). This 71 ** machine calls mid level protocol machines, ie ATRSM (Answer To Reset 72 ** State Machine), t0SendSM (T=0 Send State Machine), and t0RecvSM (T=0 Recv 73 ** State Machine). These mid level protocol machines in turn call low level 74 ** bit-bashing machines, ie coldResetSM, t0SendByteSM, T0RecvByteSM. 75 ** 76 ** Smart Cards are driven in a command/response mode. Ie you issue a command 77 ** to the Smart Card and it responds. This command/response mode is reflected 78 ** in the structure of the driver. Ie the ioctl gets a command, it 79 ** gives it to the bottom half to execute and goes to sleep. The bottom half 80 ** executes the command and gets the response to from the card and then 81 ** notifies the top half that it has completed. Commands usually complete 82 ** in under a second. 83 ** 84 ** 85 ** 86 ** AUTHORS: 87 ** 88 ** E. J. Grohn 89 ** Digital Equipment Corporation. 90 ** 91 ** CREATION DATE: 92 ** 93 ** 27-July-97 94 ** 95 **-- 96 */ 97 98 /* 99 ** 100 ** INCLUDE FILES 101 ** 102 */ 103 104 #include <sys/cdefs.h> 105 __KERNEL_RCSID(0, "$NetBSD: scr.c,v 1.22 2007/03/04 06:00:43 christos Exp $"); 106 107 #include "opt_ddb.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/ioctl.h> 112 /* #include <sys/select.h> */ 113 /* #include <sys/tty.h> */ 114 #include <sys/proc.h> 115 /* #include <sys/user.h> */ 116 #include <sys/conf.h> 117 /* #include <sys/file.h> */ 118 /* #include <sys/uio.h> */ 119 #include <sys/kernel.h> 120 /* #include <sys/syslog.h> */ 121 #include <sys/types.h> 122 #include <sys/device.h> 123 #include <dev/isa/isavar.h> 124 #include <arm/cpufunc.h> 125 126 127 /* SCR_DEBUG is the master switch for turning on debugging */ 128 //#define SCR_DEBUG 1 129 #ifdef SCR_DEBUG 130 #define KERNEL_DEBUG 131 #ifdef DDB 132 #define DEBUGGER printf("file = %s, line = %d\n",__FILE__,__LINE__);Debugger() 133 #else 134 #define DEBUGGER panic("file = %s, line = %d",__FILE__,__LINE__); 135 #endif 136 #else 137 #define DEBUGGER 138 #endif 139 140 141 #include <machine/kerndebug.h> 142 //#include <machine/intr.h> 143 #include <dev/ic/i8253reg.h> 144 #include <shark/shark/hat.h> 145 #include <shark/shark/sequoia.h> 146 #include <machine/scrio.h> 147 148 149 150 151 /* 152 ** 153 ** MACRO DEFINITIONS 154 ** 155 */ 156 157 158 #define scr_lcr scr_cfcr 159 160 /* 161 ** Macro to extract the minor device number from the device Identifier 162 */ 163 #define SCRUNIT(x) (minor(x)) 164 165 /* 166 ** some macros to assist in debugging 167 */ 168 #ifdef SCR_DEBUG 169 #define KERNEL_DEBUG 170 #define ASSERT(f) do { if (!(f)) { DEBUGGER;} }while(0) 171 #define TOGGLE_TEST_PIN() scrToggleTestPin() 172 #define INVALID_STATE_CMD(sc,state,cmd) invalidStateCmd(sc,state,cmd,__LINE__); 173 #else 174 #define ASSERT(f) 175 #define TOGGLE_TEST_PIN() 176 //#define INVALID_STATE_CMD(sc,state,cmd) panic("scr: invalid state/cmd, sc = %X, state = %X, cmd = %X, line = %d",sc,state,cmd,__LINE__); 177 #define INVALID_STATE_CMD(sc,state,cmd) sc->bigTrouble = true; 178 179 #endif 180 181 182 /* 183 ** The first and last bytes of the debug control variables is reserved for 184 ** the standard KERN_DEBUG_xxx macros, so we can tailor the middle two bytes 185 */ 186 #define SCRPROBE_DEBUG_INFO 0x00000100 187 #define SCRATTACH_DEBUG_INFO 0x00000200 188 #define SCROPEN_DEBUG_INFO 0x00000400 189 #define SCRCLOSE_DEBUG_INFO 0x00000800 190 #define SCRREAD_DEBUG_INFO 0x00001000 191 #define SCRWRITE_DEBUG_INFO 0x00002000 192 #define SCRIOCTL_DEBUG_INFO 0x00004000 193 #define MASTER_SM_DEBUG_INFO 0x00008000 194 #define COLD_RESET_SM_DEBUG_INFO 0x00010000 195 #define ATR_SM_DEBUG_INFO 0x00020000 196 #define T0_RECV_BYTE_SM_DEBUG_INFO 0x00040000 197 #define T0_SEND_BYTE_SM_DEBUG_INFO 0x00080000 198 #define T0_RECV_SM_DEBUG_INFO 0x00100000 199 #define T0_SEND_SM_DEBUG_INFO 0x00200000 200 201 202 int scrdebug = //SCRPROBE_DEBUG_INFO | 203 //SCRATTACH_DEBUG_INFO | 204 //SCROPEN_DEBUG_INFO | 205 //SCRCLOSE_DEBUG_INFO | 206 //SCRREAD_DEBUG_INFO | 207 //SCRWRITE_DEBUG_INFO | 208 //SCRIOCTL_DEBUG_INFO | 209 //MASTER_SM_DEBUG_INFO | 210 //COLD_RESET_SM_DEBUG_INFO| 211 //ATR_SM_DEBUG_INFO | 212 //T0_RECV_BYTE_SM_DEBUG_INFO | 213 //T0_SEND_BYTE_SM_DEBUG_INFO | 214 //T0_RECV_SM_DEBUG_INFO | 215 //T0_SEND_SM_DEBUG_INFO | 216 0; 217 218 219 220 221 222 223 /* 224 ** the bottom half of the driver is done as several linked state machines 225 ** below are all the states of the machines, and the commands that are 226 ** sent to each machine 227 */ 228 229 /* commands to Master State Machine from ioctl */ 230 #define mcOn 0x0100 /* ioctl on */ 231 #define mcT0DataSend 0x0102 /* ioctl send */ 232 #define mcT0DataRecv 0x0103 /* ioctl recv */ 233 234 /* commands to Master State Machine from lower state machines */ 235 #define mcColdReset 0x0105 /* cold reset finished */ 236 #define mcATR 0x0106 /* ATR has finished */ 237 #define mcT0Send 0x0108 /* T0 send finished */ 238 #define mcT0Recv 0x010a /* T0 recv finished */ 239 240 /* states in Master state machine (ms = Master State) */ 241 #define msIdleOff 0x0200 /* in idle state, card powered off */ 242 #define msColdReset 0x0201 /* turning on power, clock, reset */ 243 #define msATR 0x0202 /* getting ATR sequence from card */ 244 #define msIdleOn 0x0203 /* idle, put card powered on */ 245 #define msT0Send 0x0204 /* sending T0 data */ 246 #define msT0Recv 0x0205 /* recving T0 data */ 247 248 249 250 251 /* commands to T0 send state machine */ 252 #define t0scStart 0x0300 /* start */ 253 #define t0scTWorkWaiting 0x0301 /* work waiting timeout */ 254 255 /* states in T0 send state machine */ 256 #define t0ssIdle 0x0400 /* idle state */ 257 #define t0ssSendHeader 0x0401 /* send 5 header bytes */ 258 #define t0ssRecvProcedure 0x0402 /* wait for procedure byte */ 259 #define t0ssSendByte 0x0403 /* send 1 byte */ 260 #define t0ssSendData 0x0404 /* send all bytes */ 261 #define t0ssRecvSW1 0x0405 /* wait for sw1 */ 262 #define t0ssRecvSW2 0x0406 /* wait for sw2 */ 263 264 265 266 267 268 /* commands to T0 recv state machine */ 269 #define t0rcStart 0x0500 /* start */ 270 #define t0rcTWorkWaiting 0x0501 /* work waiting timeout */ 271 272 /* states in T0 recv state machine */ 273 #define t0rsIdle 0x0600 /* idle state */ 274 #define t0rsSendHeader 0x0601 /* send 5 header bytes */ 275 #define t0rsRecvProcedure 0x0602 /* wait for procedure byte */ 276 #define t0rsRecvByte 0x0603 /* recv 1 byte */ 277 #define t0rsRecvData 0x0604 /* recv all bytes */ 278 #define t0rsRecvSW1 0x0605 /* wait for sw1 */ 279 #define t0rsRecvSW2 0x0606 /* wait for sw2 */ 280 281 282 283 /* commands to Cold Reset state machine */ 284 #define crcStart 0x0900 /* start */ 285 #define crcT2 0x0902 /* timeout T2 ISO 7816-3, P6, Figure 2 */ 286 287 /* states in cold reset state machine */ 288 #define crsIdle 0x0a00 /* idle */ 289 #define crsT2Wait 0x0a01 /* wait for T2 ISO 7816-3.P6. Figure 2 */ 290 291 292 293 294 295 /* commands to Answer To Reset (ATR) state machine */ 296 #define atrcStart 0x0b00 /* start */ 297 #define atrcT3 0x0b04 /* got T3 timeout */ 298 #define atrcTWorkWaiting 0x0b05 /* work waiting timeout */ 299 300 /* states in Answer To Reset (ATR) state machine */ 301 #define atrsIdle 0x0c00 /* idle */ 302 #define atrsTS 0x0c01 /* looking for TS, (initial bytes) */ 303 #define atrsT0 0x0c02 /* looking for T0, (format bytes) */ 304 #define atrsTABCD 0x0c03 /* looking for TAx (interface bytes)*/ 305 #define atrsTK 0x0c04 /* looking for TK (history bytes) */ 306 #define atrsTCK 0x0c05 /* looking for TCK (check bytes */ 307 308 309 /* commands to T0 Recv Byte state machine */ 310 #define t0rbcStart 0x0d00 /* start */ 311 #define t0rbcAbort 0x0d01 /* abort */ 312 #define t0rbcTFindStartEdge 0x0d02 /* start bit edge search */ 313 #define t0rbcTFindStartMid 0x0d03 /* start bit mid search */ 314 #define t0rbcTClockData 0x0d04 /* data bit search */ 315 #define t0rbcTErrorStart 0x0d05 /* start to send error */ 316 #define t0rbcTErrorStop 0x0d06 /* stop sending error */ 317 318 /* states in T0 Recv Byte state machine */ 319 #define t0rbsIdle 0x0e00 /* idle */ 320 #define t0rbsFindStartEdge 0x0e01 /* looking for start bit */ 321 #define t0rbsFindStartMid 0x0e02 /* looking for start bit */ 322 #define t0rbsClockData 0x0e03 /* looking for data bits */ 323 #define t0rbsSendError 0x0e04 /* output error bit */ 324 325 326 327 328 /* commands to T0 Send Byte state machine */ 329 #define t0sbcStart 0x0f00 /* start the machine */ 330 #define t0sbcAbort 0x0f01 /* abort the machine */ 331 #define t0sbcTGuardTime 0x0f02 /* guard time finished */ 332 #define t0sbcTClockData 0x0f03 /* clock time finished */ 333 #define t0sbcTError 0x0f04 /* start to send error */ 334 #define t0sbcTResend 0x0f05 /* if parity error, then wait unfill we can re-send */ 335 336 337 338 /* states in T0 Send Byte state machine */ 339 #define t0sbsIdle 0x1000 /* idle */ 340 #define t0sbsWaitGuardTime 0x1001 /* wait for guard time to finish */ 341 #define t0sbsClockData 0x1002 /* clocking out data & parity */ 342 #define t0sbsWaitError 0x1003 /* waiting for error indicator */ 343 #define t0sbsWaitResend 0x1004 /* waiting to start re-send if error */ 344 345 346 347 348 /* 349 ** generic middle level state machine commands 350 ** sent by T0 Send Byte & T0 recv Byte to T0 Send and T0 Recv 351 */ 352 #define gcT0RecvByte 0x1100 /* receive finished */ 353 #define gcT0RecvByteErr 0x1101 /* receive got error */ 354 #define gcT0SendByte 0x1102 /* send finished */ 355 #define gcT0SendByteErr 0x1103 /* send got error */ 356 357 358 359 360 361 362 /* 363 ** 364 ** below are definitions associated with Smart Card 365 ** 366 */ 367 368 369 /* 370 ** Frequency of clock sent to card 371 ** NCI's card is running at 1/2 freq, so in debug we can make 372 ** use of this to toggle more debug signals and still be within 373 ** interrupt time budget 374 */ 375 #ifdef SCR_DEBUG 376 #define CARD_FREQ_DEF (3579000/2) 377 #else 378 #define CARD_FREQ_DEF (3579000) 379 #endif 380 381 382 383 /* byte logic level and msb/lsb coding */ 384 #define CONVENTION_UNKNOWN 0 385 #define CONVENTION_INVERSE 1 386 #define CONVENTION_DIRECT 2 387 #define CONVENIONT_INVERSE_ID 0x3f 388 #define CONVENTION_DIRECT_FIX 0x3b 389 #define CONVENTION_DIRECT_ID 0x23 390 391 392 /* macros that help us set the T2 count for bit bashing */ 393 #define CLK_COUNT_START (((372 * TIMER_FREQ) / sc->cardFreq) /5) 394 #define CLK_COUNT_DATA (((372 * TIMER_FREQ) / sc->cardFreq) ) 395 #define START_2_DATA 5 396 397 /* default settings to use if not specified in ATR */ 398 #define N_DEFAULT 0 /* guard time default */ 399 #define Fi_DEFAULT 372 /* clock rate conversion default */ 400 #define Di_DEFAULT 1 /* bit rate adjustment factor */ 401 #define Wi_DEFAULT 10 /* waiting time */ 402 403 404 /* table for clock rate adjustment in ATR */ 405 int FI2Fi[16] = {372, 372, 558, 744,1116,1488,1860, 0, 406 0, 512, 768,1024,1536,2048, 0, 0}; 407 408 /* table for bit rate adjustment in ATR*/ 409 int DI2Di[16] = { 0, 1, 2, 4, 8, 16, 32, 0, 410 12, 20, 0, 0, 0, 0, 0, 0}; 411 412 /* values of atrY in the ATR sequence*/ 413 #define ATR_Y_TA 0x10 414 #define ATR_Y_TB 0x20 415 #define ATR_Y_TC 0x40 416 #define ATR_Y_TD 0x80 417 418 /* T0,T1,etc information in ATR sequence*/ 419 #define PROTOCOL_T0 0x0001 /* bit 0 for T0 */ 420 #define PROTOCOL_T1 0x0002 /* bit 1 for T1 */ 421 #define PROTOCOL_T2 0x0004 /* bit 2 for T2*/ 422 #define PROTOCOL_T3 0x0008 /* bit 3 for T3*/ 423 /* etc */ 424 425 426 /* timeouts for various places - see ISO 7816-3 */ 427 #define T_t2 ((300 * TIMER_FREQ) / sc->cardFreq) 428 #define T_t3 ((40000 * (TIMER_FREQ/1024)) / (sc->cardFreq/1024)) 429 #define T_WORK_WAITING (((960 * sc->Wi * sc->Fi ) / (sc->cardFreq/1024)) * (TIMER_FREQ/1024)) 430 #define PARITY_ERROR_MAX 3 /* maximum parity errors on 1 byte before giving up */ 431 432 /* 433 ** its possible for the HAT to wedge. If that happens, all timing is sick, so 434 ** we use timeout below (driven of system sleeps) as a "watchdog" 435 */ 436 #define MAX_FIQ_TIME 5 /* maximum time we are willing to run the FIQ */ 437 438 439 /* used to decode T0 commands */ 440 #define CMD_BUF_INS_OFF 1 /* offset to INS in header */ 441 #define CMD_BUF_DATA_LEN_OFF 4 /* offset to data length in header */ 442 443 444 /* 445 ** 446 ** DATA STRUCTURES 447 ** 448 */ 449 typedef unsigned char BYTE; 450 451 /* our soft c structure */ 452 struct scr_softc 453 { 454 struct device dev; 455 int open; 456 457 /* configuration information */ 458 int status; /* status to be returned */ 459 int cardFreq; /* freq supplied to card */ 460 int convention; /* ie direct or inverse */ 461 int protocolType; /* bit 0 indicates T0, bit 1 indicates T1,etc */ 462 int N; /* guard time */ 463 int Fi; /* clock rate */ 464 int Di; /* bit rate adjustment */ 465 int Wi; /* work waiting time */ 466 int clkCountStartRecv; /* count for clock start bits on recv */ 467 int clkCountDataRecv; /* count for clock data bits on recv*/ 468 int clkCountDataSend; /* count for clock data bits on send */ 469 470 /* state machines */ 471 int masterS ; 472 int t0RecvS; 473 int t0SendS; 474 int coldResetS; 475 int ATRS; 476 int t0RecvByteS; 477 int t0SendByteS; 478 479 /* extra stuff kept for t0send state machine */ 480 int commandCount; /* number of command bytes sent */ 481 int dataCount; /* number of data bytes send/recv */ 482 int dataMax; /* max number of data bytes to send/recv */ 483 484 /* extra stuff kept for t0RecvByteS, t0SendByteS machines */ 485 void (*t0ByteParent) __P((struct scr_softc *,int)); /* state machine that is controlling this SM */ 486 int shiftBits; /* number of bits shifted */ 487 BYTE shiftByte; /* intermediate value of bit being shifted */ 488 BYTE dataByte; /* actual value of byte */ 489 int shiftParity; /* value of parity */ 490 int shiftParityCount; /* number of retries due to parity error */ 491 492 /* extra stuff kept for ATR machine */ 493 int atrY; /* indicates if TA,TB,TC,TD is to follow */ 494 int atrK; /* number of historical characters*/ 495 int atrKCount; /* progressive could of historical characters*/ 496 int atrTABCDx; /* the 'i' in TA(i), TB(i), TC(i) and TD(i) */ 497 int atrFi; /* value of Fi */ 498 int atrDi; /* value of Di */ 499 500 int masterDone; /* flag used by bottom half to tell top half its done */ 501 int bigTrouble; /* david/jim, remove this when the dust settles */ 502 503 /* pointers used by ioctl */ 504 ScrOn * pIoctlOn; /* pointer to on ioctl data */ 505 ScrT0 * pIoctlT0; /* pointer to T0 ioctl data */ 506 }; 507 508 /* number of devices */ 509 static int devices = 0; 510 511 /* used as reference for tsleep */ 512 static int tsleepIdent; 513 514 515 /* 516 ** only 1 device is using the hat at any one time 517 ** variable below must be acquired using splhigh before using the hat 518 */ 519 static int hatLock = false; 520 521 522 523 524 /* 525 ** data structures associated with our timeout queue that we run for the 526 ** bottom half of the driver 527 */ 528 529 /* timeout callout structure */ 530 typedef struct callout_t 531 { 532 struct callout_t *c_next; /* next callout in queue */ 533 struct scr_softc *c_sc; /* soft c */ 534 int c_arg; /* function argument */ 535 void (*c_func) __P((struct scr_softc*,int)); /* function to call */ 536 int c_time; /* ticks to the event */ 537 }Callout; 538 539 /* actual callout array */ 540 #define SCR_CLK_CALLOUT_COUNT 10 541 static Callout scrClkCalloutArray[SCR_CLK_CALLOUT_COUNT]; 542 543 /* callout lists */ 544 static Callout *scrClkCallFree; /* free queue */ 545 static Callout scrClkCallTodo; /* todo queue */ 546 547 /* 548 ** information kept for the clock/FIQ that drives our timeout queue 549 */ 550 static int scrClkEnable = 0; /* true if clock enabled */ 551 static void myHatWedge(int nFIQs); /* callback that informs us if FIQ has wedged */ 552 static int scrClkCount; /* number used to set t2 that drives FIQ */ 553 554 #define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ 555 static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used during a FIQ */ 556 557 558 559 560 561 562 563 564 565 566 567 568 /* 569 ** 570 ** FUNCTIONAL PROTOTYPES 571 ** 572 */ 573 574 /* 575 ** 576 ** functions in top half of driver 577 ** 578 */ 579 580 /* configure routines */ 581 int scrprobe __P((struct device *, struct cfdata *, void *)); 582 void scrattach __P((struct device *, struct device *, void *)); 583 584 static void initStates __P((struct scr_softc * sc)); 585 586 587 588 589 /* 590 ** 591 ** functions in bottom half of driver 592 ** 593 */ 594 595 /* top level state machine */ 596 static void masterSM __P((struct scr_softc * sc,int cmd)); 597 598 /* mid level state machines, ie protocols */ 599 static void t0SendSM __P((struct scr_softc * sc,int cnd)); 600 static void t0RecvSM __P((struct scr_softc * sc,int cnd)); 601 static void ATRSM __P((struct scr_softc * sc,int cnd)); 602 603 /* low level state machines, ie bash hardware bits */ 604 static void coldResetSM __P((struct scr_softc * sc,int cnd)); 605 606 static void t0SendByteSM __P((struct scr_softc * sc,int cnd)); 607 static void t0RecvByteSM __P((struct scr_softc * sc,int cnd)); 608 609 static void cardOff __P((struct scr_softc * sc)); 610 611 /* 612 ** functions used for our own timeout routines. 613 ** we cannot use system ones as we are running at a spl level 614 ** that can interrupt the system timeout routines 615 */ 616 static void scrClkInit __P((void)); 617 static void scrClkStart __P((struct scr_softc* sc,int countPerTick)); 618 static void scrClkAdj __P((int count)); 619 static void scrClkStop __P((void)); 620 static void hatClkIrq __P((int count)); 621 622 static void scrTimeout __P((void (*func)(struct scr_softc*,int), struct scr_softc*, int arg, int count)); 623 static void scrUntimeout __P((void (*func)(struct scr_softc*,int), struct scr_softc*, int arg)); 624 625 626 /* debug functions */ 627 #ifdef SCR_DEBUG 628 static void invalidStateCmd __P((struct scr_softc* sc,int state,int cmd, int line)); 629 static char * getText __P((int x)); 630 #endif 631 632 633 634 635 636 CFATTACH_DECL(scr, sizeof(struct scr_softc), 637 scrprobe, scrattach, NULL, NULL); 638 639 extern struct cfdriver scr_cd; 640 641 dev_type_open(scropen); 642 dev_type_close(scrclose); 643 dev_type_ioctl(scrioctl); 644 645 const struct cdevsw scr_cdevsw = { 646 scropen, scrclose, noread, nowrite, scrioctl, 647 nostop, notty, nopoll, nommap, nokqfilter, D_TTY 648 }; 649 650 /* 651 **++ 652 ** FUNCTIONAL DESCRIPTION: 653 ** 654 ** scrProbe 655 ** 656 ** This is the probe routine for the Smart Card. Because the 657 ** Smart Card is hard wired, there is no probing to peform. The 658 ** function ensures that a succesfull problem occurs only once. 659 ** 660 ** FORMAL PARAMETERS: 661 ** 662 ** parent - input : pointer to the parent device 663 ** match - not used 664 ** aux - output : pointer to an isa_attach_args structure. 665 ** 666 ** IMPLICIT INPUTS: 667 ** 668 ** none. 669 ** 670 ** IMPLICIT OUTPUTS: 671 ** 672 ** none. 673 ** 674 ** FUNCTION VALUE: 675 ** 676 ** 0 - Probe failed to find the requested device. 677 ** 1 - Probe successfully talked to the device. 678 ** 679 ** SIDE EFFECTS: 680 ** 681 ** none. 682 **-- 683 */ 684 int scrprobe(parent, match, aux) 685 struct device *parent; 686 struct cfdata *match; 687 void *aux; 688 { 689 struct isa_attach_args *ia = aux; 690 int rv = 0; 691 692 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: called, name = %s\n", 693 device_cfdata(parent)->cf_name)); 694 695 if (device_is_a(parent, "ofisascr") && devices == 0) 696 { 697 /* set "devices" to ensure that we respond only once */ 698 devices++; 699 700 /* tell the caller that we are not using any resource */ 701 ia->ia_nio = 0; 702 ia->ia_niomem = 0; 703 ia->ia_nirq = 0; 704 ia->ia_ndrq = 0; 705 rv = 1; 706 707 708 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: successful \n")); 709 710 } 711 712 713 return (rv); 714 715 } /* End scrprobe() */ 716 717 718 /* 719 **++ 720 ** FUNCTIONAL DESCRIPTION: 721 ** 722 ** scrattach 723 ** 724 ** Initialize the clock and state machines 725 ** 726 ** FORMAL PARAMETERS: 727 ** 728 ** parent - input : pointer to my parents device structure. 729 ** self - output : pointer to my softc with device structure at front. 730 ** aux - input : pointer to the isa_attach_args structure. 731 ** 732 ** IMPLICIT INPUTS: 733 ** 734 ** nill 735 ** 736 ** IMPLICIT OUTPUTS: 737 ** 738 ** scrconsinit - clock callout functions set 739 ** state machines all at idle 740 ** 741 ** FUNCTION VALUE: 742 ** 743 ** none. 744 ** 745 ** SIDE EFFECTS: 746 ** 747 ** none. 748 **-- 749 */ 750 void scrattach(parent, self, aux) 751 struct device *parent; 752 struct device *self; 753 void *aux; 754 { 755 struct scr_softc *sc = (void *)self; 756 757 printf("\n"); 758 if (device_is_a(parent, "ofisascr")) 759 { 760 KERN_DEBUG (scrdebug, SCRATTACH_DEBUG_INFO,("scrattach: called \n")); 761 762 /* set initial state machine values */ 763 scrClkInit(); 764 initStates(sc); 765 sc->open = false; 766 } 767 768 else 769 { 770 panic("scrattach: not on an ISA bus, attach impossible"); 771 } /* End else we aren't on ISA and we can't handle it */ 772 773 774 return; 775 } /* End scrattach() */ 776 777 778 /* 779 **++ 780 ** FUNCTIONAL DESCRIPTION: 781 ** 782 ** initStates 783 ** 784 ** sets the state of all machines to idle 785 ** 786 ** FORMAL PARAMETERS: 787 ** 788 ** sc - Pointer to the softc structure. 789 ** 790 ** IMPLICIT INPUTS: 791 ** 792 ** nill 793 ** 794 ** IMPLICIT OUTPUTS: 795 ** 796 ** nill 797 ** 798 ** FUNCTION VALUE: 799 ** 800 ** nill 801 ** 802 ** SIDE EFFECTS: 803 ** 804 ** nill 805 **-- 806 */ 807 static void initStates(struct scr_softc * sc) 808 { 809 sc->masterS = msIdleOff; 810 sc->t0RecvS = t0rsIdle; 811 sc->t0SendS = t0ssIdle; 812 sc->coldResetS = crsIdle; 813 sc->ATRS = atrsIdle; 814 sc->t0RecvByteS = t0rbsIdle; 815 sc->t0SendByteS = t0sbsIdle; 816 } 817 818 819 820 /* 821 **++ 822 ** FUNCTIONAL DESCRIPTION: 823 ** 824 ** scrOpen 825 ** 826 ** Opens the driver. We only let the device be opened 827 ** once for security reasons 828 ** 829 ** FORMAL PARAMETERS: 830 ** 831 ** dev - input : Device identifier consisting of major and minor numbers. 832 ** flag - input : Indicates if this is a blocking I/O call. 833 ** mode - not used. 834 ** l - input : Pointer to the lwp structure of the light weight process 835 ** performing the open. 836 ** 837 ** IMPLICIT INPUTS: 838 ** 839 ** none. 840 ** 841 ** IMPLICIT OUTPUTS: 842 ** 843 ** none. 844 ** 845 ** FUNCTION VALUE: 846 ** 847 ** ENXIO - invalid device specified for open. 848 ** EBUSY - The unit is already open 849 ** 850 ** SIDE EFFECTS: 851 ** 852 ** none. 853 **-- 854 */ 855 int scropen(dev, flag, mode, l) 856 dev_t dev; 857 int flag; 858 int mode; 859 struct lwp *l; 860 { 861 int unit = SCRUNIT(dev); 862 struct scr_softc *sc; 863 864 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO, 865 ("scropen: called with minor device %d and flag 0x%x\n", 866 unit, flag)); 867 868 /* Sanity check the minor device number we have been instructed 869 ** to open and set up our softc structure pointer. 870 */ 871 if (unit >= scr_cd.cd_ndevs) 872 { 873 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 874 return (ENXIO); 875 } 876 sc = scr_cd.cd_devs[unit]; 877 if (!sc) 878 { 879 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 880 return (ENXIO); 881 } 882 883 884 // david,jim - remove ifdef this when NCI can cope with only 1 open 885 #if 0 886 if (sc->open) 887 { 888 889 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return EBUSY\n")); 890 return (EBUSY); 891 } 892 893 894 /* set all initial conditions */ 895 sc->open = true; 896 #endif 897 898 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("scropen: success \n")); 899 /* Now invoke the line discipline open routine 900 */ 901 902 return 0; 903 904 } /* End scropen() */ 905 906 907 /* 908 **++ 909 ** FUNCTIONAL DESCRIPTION: 910 ** 911 ** This function closed the driver 912 ** 913 ** FORMAL PARAMETERS: 914 ** 915 ** dev - input : Device identifier consisting of major and minor numbers. 916 ** flag - Not used. 917 ** mode - Not used. 918 ** p - Not used. 919 ** 920 ** IMPLICIT INPUTS: 921 ** 922 ** scr_cd - used to locate the softc structure for the device unit 923 ** identified by dev. 924 ** 925 ** IMPLICIT OUTPUTS: 926 ** 927 ** The device is put into an idle state. 928 ** 929 ** FUNCTION VALUE: 930 ** 931 ** 0 - Always returns success. 932 ** 933 ** SIDE EFFECTS: 934 ** 935 ** none. 936 **-- 937 */ 938 int scrclose(dev, flag, mode, l) 939 dev_t dev; 940 int flag; 941 int mode; 942 struct lwp *l; 943 { 944 #if 0 945 int unit = SCRUNIT(dev); 946 struct scr_softc *sc = scr_cd.cd_devs[unit]; 947 #endif 948 949 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO, 950 ("scrclose: called for minor device %d flag 0x%x\n", 951 SCRUNIT(dev), flag)); 952 953 // david,jim - remove ifdef this when NCI can cope with only 1 open 954 #if 0 955 /* Check we are open in the first place 956 */ 957 if (sc->open) 958 { 959 /* put everything in the idle state */ 960 scrClkInit(); 961 initStates(sc); 962 sc->open = false; 963 964 } 965 966 967 else 968 { 969 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("\t scrclose, device not open\n")); 970 } 971 #endif 972 973 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("scrclose exiting\n")); 974 return(0); 975 } 976 977 /* 978 **++ 979 ** FUNCTIONAL DESCRIPTION: 980 ** 981 ** This routine is responsible for performing I/O controls. 982 ** 983 ** There are 4 commands. Status, On, T0 and Off. 984 ** 985 ** Status checks to see if the card is inserted. This command 986 ** does not use the state machines 987 ** 988 ** On turns the card on and gets the ATR sequence from the card. 989 ** This command does use the state machines 990 ** 991 ** T0 is used to read and write the card. This command does use 992 ** the state machines 993 ** 994 ** Off turns the card off. This command does not use the state 995 ** machines. 996 ** 997 ** 998 ** FORMAL PARAMETERS: 999 ** 1000 ** dev - input : Device identifier consisting of major and minor numbers. 1001 ** cmd - input : The requested IOCTL command to be performed. 1002 ** See scrio.h for details 1003 ** 1004 ** 1005 ** Bit Position { 3322222222221111111111 1006 ** { 10987654321098765432109876543210 1007 ** Meaning | DDDLLLLLLLLLLLLLGGGGGGGGCCCCCCCC 1008 ** 1009 ** D - Command direction, in/out/both. 1010 ** L - Command argument length. 1011 ** G - Command group, 't' used for tty. 1012 ** C - Actual command enumeration. 1013 ** 1014 ** data - input/output : Direction depends on the command. 1015 ** flag - input : Not used by us but passed to line discipline and ttioctl 1016 ** l - input : pointer to lwp structure of user. 1017 ** 1018 ** IMPLICIT INPUTS: 1019 ** 1020 ** none. 1021 ** 1022 ** IMPLICIT OUTPUTS: 1023 ** 1024 ** sc->masterS state of master state machine 1025 ** 1026 ** 1027 ** FUNCTION VALUE: 1028 ** 1029 ** ENOTTY if not correct ioctl 1030 ** 1031 ** 1032 ** SIDE EFFECTS: 1033 ** 1034 **-- 1035 */ 1036 int 1037 scrioctl(dev, cmd, data, flag, l) 1038 dev_t dev; 1039 u_long cmd; 1040 void * data; 1041 int flag; 1042 struct lwp *l; 1043 { 1044 int unit = SCRUNIT(dev); 1045 struct scr_softc* sc = scr_cd.cd_devs[unit]; 1046 1047 int error = 0; /* error value returned */ 1048 int masterDoneRetries= 0; /* nuber of times we looked at masterDone */ 1049 int done; /* local copy of masterDone */ 1050 1051 ScrStatus * pIoctlStatus; /* pointer to status ioctl */ 1052 ScrOff * pIoctlOff; /* pointer to off ioctl */ 1053 1054 u_int savedInts; /* saved interrupts */ 1055 int s; /* saved spl value */ 1056 1057 1058 1059 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1060 ("scrioctl: called for device 0x%x, command 0x%lx, " 1061 "flag 0x%x\n", 1062 unit, cmd, flag)); 1063 1064 1065 1066 switch (cmd) 1067 { 1068 /* 1069 ** get the status of the card, ie is it in, in but off, in and on 1070 */ 1071 case SCRIOSTATUS: 1072 pIoctlStatus = (ScrStatus*)data; 1073 if (scrGetDetect()) 1074 { 1075 savedInts = disable_interrupts(I32_bit | F32_bit); 1076 if (sc->masterS == msIdleOn) 1077 { 1078 pIoctlStatus->status = CARD_ON; 1079 } 1080 else 1081 { 1082 ASSERT(sc->masterS == msIdleOff); 1083 pIoctlStatus->status = CARD_INSERTED; 1084 } 1085 restore_interrupts(savedInts); 1086 } 1087 1088 else 1089 { 1090 pIoctlStatus->status = CARD_REMOVED; 1091 } 1092 break; 1093 1094 1095 1096 /* 1097 ** turn the card on and get the ATR sequence 1098 */ 1099 case SCRIOON: 1100 sc->pIoctlOn = (ScrOn*)data; 1101 // acquire the hat lock. 1102 while (1) 1103 { 1104 s = splhigh(); 1105 if(!hatLock) 1106 { 1107 hatLock = true; 1108 splx(s); 1109 break; 1110 } 1111 splx(s); 1112 1113 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1114 } 1115 1116 1117 // check to see if the card is in 1118 if(!scrGetDetect()) 1119 { 1120 initStates(sc); 1121 cardOff(sc); 1122 // do not call scrClkInit() as it is idle already 1123 sc->pIoctlOn->status = ERROR_CARD_REMOVED; 1124 } 1125 1126 1127 // check to see if we are already on 1128 else if(sc->masterS == msIdleOn) 1129 { 1130 sc->pIoctlOn->status = ERROR_CARD_ON; 1131 } 1132 1133 // card was in, card is off, so lets start it 1134 else 1135 { 1136 // set up the top half 1137 sc->masterDone = false; 1138 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1139 1140 1141 1142 // start bottom half 1143 scrClkStart (sc,400); 1144 savedInts = disable_interrupts(I32_bit | F32_bit); 1145 masterSM(sc,mcOn); 1146 restore_interrupts(savedInts); 1147 1148 1149 1150 // see if bottom half done 1151 while (1) 1152 { 1153 // check that we have not looped too many times 1154 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1155 { 1156 //printf("MAX_FIQ_TIME reached \n"); 1157 // big problems, so reset bottom 1158 savedInts = disable_interrupts(I32_bit | F32_bit); 1159 scrClkInit(); 1160 initStates(sc); 1161 cardOff(sc); 1162 sc->status = ERROR_CARD_REMOVED; 1163 sc->masterDone = true; 1164 restore_interrupts(savedInts); 1165 // dont stop clock, done at bottom of case 1166 } 1167 masterDoneRetries++; 1168 1169 // get done bit 1170 savedInts = disable_interrupts(I32_bit | F32_bit); 1171 done = sc->masterDone; 1172 restore_interrupts(savedInts); 1173 1174 // see if all done 1175 if(done) 1176 { 1177 break; 1178 } 1179 1180 1181 // wait for a while 1182 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1183 } 1184 1185 1186 // stop bottom half 1187 scrClkStop(); 1188 1189 1190 /* need to fix up count bits in non hat interrupt time, so */ 1191 if (sc->status == ERROR_OK) 1192 { 1193 sc->clkCountStartRecv = CLK_COUNT_START; 1194 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1195 sc->clkCountDataSend = CLK_COUNT_DATA; 1196 } 1197 1198 1199 1200 /* takes while to turn off all lines, so keep out of hat */ 1201 if (sc->masterS != msIdleOn) 1202 { 1203 cardOff(sc); 1204 } 1205 // get the status back from the state machine 1206 sc->pIoctlOn->status = sc->status; 1207 1208 1209 } 1210 1211 1212 // release the hat lock. 1213 s = splhigh(); 1214 ASSERT(hatlock); 1215 hatLock = false; 1216 splx(s); 1217 1218 // david,jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1219 if (sc->pIoctlOn->status != ERROR_OK) 1220 { 1221 sc->pIoctlOn->atrLen = 0; 1222 } 1223 break; 1224 1225 1226 /* 1227 ** turn the card off 1228 */ 1229 case SCRIOOFF: 1230 pIoctlOff = (ScrOff*)data; 1231 // card off does not requires any state processing, so do work here 1232 initStates(sc); 1233 cardOff(sc); 1234 // do not call scrClkInit() as it is idle already 1235 pIoctlOff->status = ERROR_OK; 1236 break; 1237 1238 1239 /* 1240 ** do a T0 read or write 1241 */ 1242 case SCRIOT0: 1243 sc->pIoctlT0 = (ScrT0*)data; 1244 1245 // acquire the hat lock. 1246 while (1) 1247 { 1248 s = splhigh(); 1249 if(!hatLock) 1250 { 1251 hatLock = true; 1252 splx(s); 1253 break; 1254 } 1255 splx(s); 1256 1257 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1258 } 1259 1260 // check to see if the card is in 1261 if(!scrGetDetect()) 1262 { 1263 initStates(sc); 1264 cardOff(sc); 1265 // do not call scrClkInit() as it is idle already 1266 sc->pIoctlT0->status = ERROR_CARD_REMOVED; 1267 } 1268 1269 1270 // check to see if card is off 1271 else if(sc->masterS == msIdleOff) 1272 { 1273 sc->pIoctlT0->status = ERROR_CARD_OFF; 1274 } 1275 1276 // card was in, card is on, lets do command 1277 else 1278 1279 { 1280 // set up the top half 1281 sc->masterDone = false; 1282 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1283 1284 // start bottom half 1285 scrClkStart (sc,sc->clkCountDataSend); 1286 savedInts = disable_interrupts(I32_bit | F32_bit); 1287 if (sc->pIoctlT0->writeBuffer) 1288 { 1289 masterSM(sc,mcT0DataSend); 1290 } 1291 else 1292 { 1293 masterSM(sc,mcT0DataRecv); 1294 } 1295 restore_interrupts(savedInts); 1296 1297 1298 // see if bottom half done 1299 while (1) 1300 { 1301 // check that we have not looped too many times 1302 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1303 { 1304 //printf("MAX_FIQ_TIME reached \n"); 1305 // big problems, so reset bottom 1306 savedInts = disable_interrupts(I32_bit | F32_bit); 1307 scrClkInit(); 1308 initStates(sc); 1309 cardOff(sc); 1310 sc->status = ERROR_CARD_REMOVED; 1311 sc->masterDone = true; 1312 restore_interrupts(savedInts); 1313 } 1314 masterDoneRetries++; 1315 1316 1317 // get done bit 1318 savedInts = disable_interrupts(I32_bit | F32_bit); 1319 done = sc->masterDone; 1320 restore_interrupts(savedInts); 1321 1322 1323 // see if all done 1324 if(done) 1325 { 1326 break; 1327 } 1328 1329 1330 // wait for a while 1331 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1332 } 1333 1334 // stop bottom half 1335 scrClkStop(); 1336 1337 1338 1339 // get the status back from the state machine 1340 sc->pIoctlT0->status = sc->status; 1341 } 1342 1343 1344 // release the hat lock. 1345 s = splhigh(); 1346 hatLock = false; 1347 splx(s); 1348 1349 1350 1351 // david, jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1352 if (sc->pIoctlT0->status != ERROR_OK) 1353 { 1354 sc->pIoctlT0->dataLen = 0; 1355 } 1356 break; 1357 1358 default: 1359 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO,("\t scrioctl: unknown command, ENOTTY \n")); 1360 error = ENOTTY; 1361 break; 1362 } 1363 1364 1365 1366 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1367 ("scrioctl: exiting with sc->status %d\n", error)); 1368 return (error); 1369 } /* End scrioctl */ 1370 1371 1372 1373 1374 1375 1376 /* 1377 ** 1378 ** All functions below this point are the bottom half of the driver 1379 ** 1380 ** All are called during a FIQ, except for some functions in masterSM which 1381 ** provides the interface between the bottom half and top half of 1382 ** the driver (nb masterDone() helps masterSM() out with this interface 1383 ** between top and bottom parts of the driver. 1384 ** 1385 */ 1386 1387 1388 /* 1389 **++ 1390 ** FUNCTIONAL DESCRIPTION: 1391 ** 1392 ** masterSM 1393 ** 1394 ** This state machine implements the top level state control It 1395 ** receives commands to turn the card on, and do T0 reads and T0 writes 1396 ** from the scrioctl. It then calls mid level state machine to action 1397 ** these commands. 1398 ** 1399 ** This machine is the only machine to keep state between scrioctl calls. 1400 ** Between calls, the state will be either msIdleOff, or msIdleOn. msIdleOff 1401 ** indicates that no signals are applied to the card. msidleOn indicates that 1402 ** power and clock are supplied to the card, and that the card has performed 1403 ** a successful ATR sequence. 1404 ** 1405 ** This routine gets called during FIQ interrupts and from scrioctl. It is a 1406 ** requirement that the scrioctl disables interrupts before calling this function. 1407 ** 1408 ** NB:- there is no way for the machine to get from msIdleOn to msIdleOff. Since 1409 ** this is just a mater of turning all signals off and resetting state machines, 1410 ** scrioctl takes a shortcut and resets everything itself. Ie it hits everything 1411 ** with a big hammer!! 1412 ** 1413 ** FORMAL PARAMETERS: 1414 ** 1415 ** sc - Pointer to the softc structure. 1416 ** cmd - command to the state machine, can be from ioctl, or mid level SM 1417 ** 1418 ** IMPLICIT INPUTS: 1419 ** 1420 ** sc->masterS state of this machine 1421 ** sc->pIoctlT0 pointer to T0 ioctl 1422 ** 1423 ** IMPLICIT OUTPUTS: 1424 ** 1425 ** 1426 ** FUNCTION VALUE: 1427 ** 1428 ** nill 1429 ** 1430 ** SIDE EFFECTS: 1431 ** 1432 ** power and clock applied to card if successful ATR 1433 **-- 1434 */ 1435 static void masterSM(struct scr_softc * sc,int cmd) 1436 { 1437 1438 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1439 1440 switch (sc->masterS) 1441 { 1442 case msIdleOff: 1443 switch (cmd) 1444 { 1445 case mcOn: 1446 if (scrGetDetect()) 1447 { 1448 /* 1449 ** the card is off, and we want it on 1450 */ 1451 1452 /* set initial values */ 1453 sc->status = 0; 1454 sc->convention = CONVENTION_UNKNOWN; 1455 sc->protocolType = 0; 1456 sc->N = N_DEFAULT; 1457 sc->Fi = Fi_DEFAULT; 1458 sc->Di = Di_DEFAULT; 1459 sc->Wi = Wi_DEFAULT; 1460 sc->cardFreq = CARD_FREQ_DEF; 1461 sc->clkCountStartRecv = CLK_COUNT_START; 1462 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1463 sc->clkCountDataSend = CLK_COUNT_DATA; 1464 1465 /* get coldResetSM to turn on power, clock, reset */ 1466 sc->masterS = msColdReset; 1467 coldResetSM(sc,crcStart); 1468 } 1469 else 1470 { 1471 /* card not inserted, so just set status and give up */ 1472 sc->status = ERROR_CARD_REMOVED; 1473 sc->masterDone = true; 1474 } 1475 break; 1476 1477 default: 1478 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1479 break; 1480 } 1481 break; 1482 1483 case msColdReset: 1484 switch (cmd) 1485 { 1486 case mcColdReset: 1487 /* 1488 ** coldResetSM has turned on power, clock , reset 1489 ** tell ATRSM to get the ATR sequence from the card 1490 */ 1491 sc->masterS = msATR; 1492 ATRSM(sc,atrcStart); 1493 break; 1494 1495 default: 1496 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1497 break; 1498 } 1499 break; 1500 1501 case msATR: 1502 switch (cmd) 1503 { 1504 case mcATR: 1505 /* 1506 ** ATRSM has tried to get ATR sequence, so give 1507 ** back results to scrioctl. ATR sequence data 1508 ** was copied directly into ioctl data area, so 1509 ** no need to copy data 1510 */ 1511 if(sc->status == ERROR_OK) 1512 { 1513 sc->masterS = msIdleOn; 1514 } 1515 else 1516 { 1517 sc->masterS = msIdleOff; 1518 } 1519 sc->masterDone = true; 1520 break; 1521 1522 1523 default: 1524 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1525 break; 1526 } 1527 break; 1528 1529 case msIdleOn: 1530 switch (cmd) 1531 { 1532 // nb there is no command to go to the IdleOff state. This 1533 // is a reset of the state machine, so is done in ioctl 1534 1535 case mcT0DataSend: 1536 /* 1537 ** card is on, and we want to T0 Send, so 1538 ** as t0SendSM to do work 1539 */ 1540 sc->status = ERROR_OK; 1541 sc->masterS = msT0Send; 1542 t0SendSM(sc,t0scStart); 1543 break; 1544 1545 case mcT0DataRecv: 1546 /* 1547 ** card is on, and we want to T0 Recv, so 1548 ** as t0RecvSM to do work 1549 */ 1550 sc->status = ERROR_OK; 1551 sc->masterS = msT0Recv; 1552 t0RecvSM(sc,t0rcStart); 1553 break; 1554 1555 default: 1556 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1557 break; 1558 } 1559 1560 break; 1561 1562 case msT0Send: 1563 switch (cmd) 1564 { 1565 case mcT0Send: 1566 /* 1567 ** t0SendSM has tried to send , so lets give back results 1568 */ 1569 sc->masterS = msIdleOn; 1570 sc->masterDone = true; 1571 break; 1572 1573 default: 1574 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1575 break; 1576 } 1577 break; 1578 1579 case msT0Recv: 1580 switch (cmd) 1581 { 1582 case mcT0Recv: 1583 /* 1584 ** t0RecvSM has tried to recv , so lets give back results 1585 ** data was written directly into ioctl data area, so we 1586 ** do not need to copy any data 1587 */ 1588 sc->pIoctlT0->dataLen = sc->dataCount; 1589 sc->masterS = msIdleOn; 1590 sc->masterDone = true; 1591 break; 1592 1593 default: 1594 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1595 break; 1596 } 1597 break; 1598 1599 default: 1600 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1601 break; 1602 1603 } 1604 } 1605 1606 1607 1608 1609 /* 1610 **++ 1611 ** FUNCTIONAL DESCRIPTION: 1612 ** 1613 ** t0SendSM 1614 ** 1615 ** This is the T=0 Send State Machine. It is responsible 1616 ** for performing the send part of the ISO 7816-3 T=0 1617 ** protocol. It is mid level protocol state machine. 1618 ** 1619 ** Once started, this machine is driven entirely via the 1620 ** FIQ/timeout structure . 1621 ** 1622 ** 1623 ** 1624 ** FORMAL PARAMETERS: 1625 ** 1626 ** sc - Pointer to the softc structure. 1627 ** cmd - command to this machine 1628 ** 1629 ** IMPLICIT INPUTS: 1630 ** 1631 ** sc->t0SendS state of this machine 1632 ** sc->pIoctlT0->command command to send to card 1633 ** sc->pIoctlT0->data data to send to card 1634 ** 1635 ** IMPLICIT OUTPUTS: 1636 ** 1637 ** sc->status error status from this machine 1638 ** sc->pIoctlT0->sw1 command status from card 1639 ** sc->pIoctlT0->sw2 command status from card 1640 ** sc->status error status from this machine 1641 ** 1642 ** FUNCTION VALUE: 1643 ** 1644 ** nill 1645 ** 1646 ** SIDE EFFECTS: 1647 ** 1648 ** nill 1649 **-- 1650 */ 1651 static void t0SendSM (struct scr_softc * sc, int cmd) 1652 { 1653 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1654 /* 1655 ** check for major failures that are common to most states 1656 */ 1657 if (cmd == t0scTWorkWaiting || 1658 cmd == gcT0RecvByteErr || 1659 cmd == gcT0SendByteErr 1660 ) 1661 { 1662 switch(cmd) 1663 { 1664 case t0scTWorkWaiting: 1665 ASSERT(sc->t0SendS != t0ssIdle); 1666 1667 /* kill all lower machines */ 1668 t0SendByteSM(sc,t0sbcAbort); 1669 t0RecvByteSM(sc,t0rbcAbort); 1670 1671 /* set status */ 1672 sc->status = ERROR_WORK_WAITING; 1673 break; 1674 1675 case gcT0RecvByteErr: // fall through 1676 case gcT0SendByteErr: 1677 scrUntimeout(t0SendSM, sc, t0scTWorkWaiting); 1678 // done set status, already set in lower machine 1679 break; 1680 1681 default: 1682 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1683 break; 1684 } 1685 1686 /* change states */ 1687 sc->t0SendS = t0ssIdle; 1688 masterSM(sc,mcT0Send); 1689 return; 1690 } 1691 1692 switch (sc->t0SendS) 1693 { 1694 case t0ssIdle: 1695 switch (cmd) 1696 { 1697 case t0scStart: 1698 /* set initial values */ 1699 sc->t0SendS = t0ssSendHeader; 1700 sc->t0ByteParent = t0SendSM; 1701 sc->commandCount = 0; 1702 sc->dataCount = 0; 1703 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1704 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1705 1706 // get a byte 1707 t0SendByteSM(sc,t0sbcStart); 1708 break; 1709 1710 default: 1711 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1712 break; 1713 } 1714 break; 1715 1716 case t0ssSendHeader: 1717 switch (cmd) 1718 { 1719 case gcT0SendByte: 1720 sc->commandCount++; 1721 if (sc->commandCount < CMD_BUF_LEN) 1722 { 1723 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1724 t0SendByteSM(sc,t0sbcStart); 1725 } 1726 else 1727 { 1728 ASSERT(sc->commandCount == CMD_BUF_LEN); 1729 1730 sc->t0SendS = t0ssRecvProcedure; 1731 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1732 t0RecvByteSM(sc,t0rbcStart); 1733 } 1734 break; 1735 1736 default: 1737 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1738 break; 1739 } 1740 break; 1741 1742 case t0ssRecvProcedure: 1743 switch (cmd) 1744 { 1745 case gcT0RecvByte: 1746 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1747 /* see if we should send all remaining bytes */ 1748 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 1749 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 1750 { 1751 ASSERT(sc->dataCount < sc->dataMax); 1752 sc->t0SendS = t0ssSendData; 1753 sc->dataByte = sc->pIoctlT0->data[sc->dataCount]; 1754 t0SendByteSM(sc,t0sbcStart); 1755 sc->dataCount++; 1756 } 1757 1758 /* see if we should send one data byte */ 1759 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 1760 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 1761 { 1762 ASSERT(sc->dataCount < sc->dataMax); 1763 sc->t0SendS = t0ssSendByte; 1764 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1765 t0SendByteSM(sc,t0sbcStart); 1766 sc->dataCount++; 1767 } 1768 1769 /* see if we should extend the work waiting period */ 1770 else if (sc->dataByte == 0x60) 1771 { 1772 t0RecvByteSM(sc,t0rbcStart); 1773 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1774 } 1775 1776 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 1777 /* see if we have a SW1 byte */ 1778 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 1779 && 1780 sc->dataByte != 0x60) 1781 #else /* XXX XXX XXX cgd */ 1782 /* see if we have a SW1 byte */ 1783 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 1784 && 1785 sc->dataByte != 0x60) 1786 #endif /* XXX XXX XXX cgd */ 1787 { 1788 sc->pIoctlT0->sw1 = sc->dataByte; 1789 sc->t0SendS = t0ssRecvSW2; 1790 t0RecvByteSM(sc,t0rbcStart); 1791 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1792 } 1793 1794 /* got bad data byte, log error and get out */ 1795 else 1796 { 1797 sc->status = ERROR_BAD_PROCEDURE_BYTE; 1798 1799 /* change state */ 1800 sc->t0SendS = t0ssIdle; 1801 masterSM(sc,mcT0Send); 1802 } 1803 break; 1804 1805 default: 1806 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1807 break; 1808 } 1809 break; 1810 1811 case t0ssSendByte: 1812 switch (cmd) 1813 { 1814 case gcT0SendByte: 1815 if (sc->dataCount < sc->dataMax) 1816 { 1817 sc->t0SendS = t0ssRecvProcedure; 1818 } 1819 1820 /* wait for sw1 byte */ 1821 else 1822 { 1823 ASSERT(sc->dataCount == sc->dataMax); 1824 sc->t0SendS = t0ssRecvSW1; 1825 } 1826 1827 // ask for another byte 1828 t0RecvByteSM(sc,t0rbcStart); 1829 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1830 break; 1831 1832 default: 1833 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1834 break; 1835 } 1836 break; 1837 1838 case t0ssSendData: 1839 switch (cmd) 1840 { 1841 case gcT0SendByte: 1842 /* send data */ 1843 if (sc->dataCount < sc->dataMax) 1844 { 1845 sc->t0SendS = t0ssSendData; 1846 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1847 t0SendByteSM(sc,t0sbcStart); 1848 sc->dataCount++; 1849 } 1850 1851 /* wait for sw1 byte */ 1852 else 1853 { 1854 ASSERT(sc->dataCount == sc->dataMax); 1855 sc->t0SendS = t0ssRecvSW1; 1856 t0RecvByteSM(sc,t0rbcStart); 1857 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1858 } 1859 break; 1860 1861 default: 1862 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1863 break; 1864 } 1865 break; 1866 1867 case t0ssRecvSW1: 1868 switch (cmd) 1869 { 1870 case gcT0RecvByte: 1871 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1872 sc->pIoctlT0->sw1 = sc->dataByte; 1873 sc->t0SendS = t0ssRecvSW2; 1874 t0RecvByteSM(sc,t0rbcStart); 1875 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1876 break; 1877 default: 1878 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1879 break; 1880 } 1881 break; 1882 1883 case t0ssRecvSW2: 1884 switch (cmd) 1885 { 1886 case gcT0RecvByte: 1887 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1888 sc->pIoctlT0->sw2 = sc->dataByte; 1889 sc->t0SendS = t0ssIdle; 1890 masterSM(sc,mcT0Send); 1891 break; 1892 1893 default: 1894 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1895 break; 1896 } 1897 break; 1898 1899 default: 1900 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1901 break; 1902 } 1903 } 1904 1905 1906 1907 /* 1908 **++ 1909 ** FUNCTIONAL DESCRIPTION: 1910 ** 1911 ** t0RecvSM 1912 ** 1913 ** This is the T=0 Recv State Machine. It is responsible 1914 ** for performing the recv part of the ISO 7816-3 T=0 1915 ** protocol. It is mid level protocol state machine. 1916 ** 1917 ** Once started, this machine is driven entirely via the 1918 ** FIQ/timeout structure . 1919 ** 1920 ** FORMAL PARAMETERS: 1921 ** 1922 ** sc - Pointer to the softc structure. 1923 ** cmd - command to this machine 1924 ** 1925 ** IMPLICIT INPUTS: 1926 ** 1927 ** sc->t0RecvS state of this machine 1928 ** sc->pIoctlT0->command command to send to card 1929 ** 1930 ** IMPLICIT OUTPUTS: 1931 ** 1932 ** sc->pIoctlT0->data data from card 1933 ** sc->pIoctlT0->dataLen size of data from card 1934 ** sc->pIoctlT0->sw1 command status from card 1935 ** sc->pIoctlT0->sw2 command status from card 1936 ** sc->status error status from this machine 1937 ** 1938 ** FUNCTION VALUE: 1939 ** 1940 ** nill 1941 ** 1942 ** SIDE EFFECTS: 1943 ** 1944 ** nill 1945 **-- 1946 */ 1947 static void t0RecvSM (struct scr_softc * sc,int cmd) 1948 { 1949 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1950 1951 /* 1952 ** check for major failures that are common to most states 1953 */ 1954 if (cmd == t0rcTWorkWaiting || 1955 cmd == gcT0RecvByteErr || 1956 cmd == gcT0SendByteErr ) 1957 1958 { 1959 switch(cmd) 1960 { 1961 1962 case t0rcTWorkWaiting: 1963 ASSERT(sc->t0RecvS != t0rsIdle); 1964 1965 /* kill all lower level machines */ 1966 t0SendByteSM(sc,t0sbcAbort); 1967 t0RecvByteSM(sc,t0rbcAbort); 1968 1969 /* set status */ 1970 sc->status = ERROR_WORK_WAITING; 1971 break; 1972 1973 case gcT0RecvByteErr: // fall through 1974 case gcT0SendByteErr: 1975 /* kill all the timers */ 1976 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 1977 break; 1978 1979 default: 1980 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1981 break; 1982 1983 } 1984 1985 1986 1987 /* change state */ 1988 sc->t0RecvS = t0rsIdle; 1989 masterSM(sc,mcT0Recv); 1990 1991 /* all done */ 1992 return; 1993 } 1994 1995 switch (sc->t0RecvS) 1996 { 1997 case t0rsIdle: 1998 switch (cmd) 1999 { 2000 case t0rcStart: 2001 /* set initial values */ 2002 sc->t0RecvS = t0rsSendHeader; 2003 sc->t0ByteParent = t0RecvSM; 2004 sc->commandCount = 0; 2005 sc->dataCount = 0; 2006 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 2007 if (sc->dataMax == 0) 2008 { 2009 sc->dataMax = 256; 2010 } 2011 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2012 t0SendByteSM(sc,t0sbcStart); 2013 break; 2014 2015 default: 2016 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2017 break; 2018 } 2019 break; 2020 2021 case t0rsSendHeader: 2022 switch (cmd) 2023 { 2024 case gcT0SendByte: 2025 sc->commandCount++; 2026 if (sc->commandCount < CMD_BUF_LEN) 2027 { 2028 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2029 t0SendByteSM(sc,t0sbcStart); 2030 } 2031 else 2032 { 2033 ASSERT(sc->commandCount == CMD_BUF_LEN); 2034 2035 sc->t0RecvS = t0rsRecvProcedure; 2036 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2037 t0RecvByteSM(sc,t0rbcStart); 2038 } 2039 break; 2040 2041 default: 2042 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2043 break; 2044 } 2045 break; 2046 2047 case t0rsRecvProcedure: 2048 switch (cmd) 2049 { 2050 case gcT0RecvByte: 2051 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2052 2053 /* see if we should recv all remaining bytes */ 2054 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 2055 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 2056 { 2057 ASSERT(sc->dataCount < sc->dataMax); 2058 2059 sc->t0RecvS = t0rsRecvData; 2060 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2061 t0RecvByteSM(sc,t0rbcStart); 2062 } 2063 2064 /* see if we should send one data byte */ 2065 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 2066 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 2067 { 2068 ASSERT(sc->dataCount < sc->dataMax); 2069 sc->t0RecvS = t0rsRecvByte; 2070 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2071 t0RecvByteSM(sc,t0rbcStart); 2072 } 2073 2074 /* see if we should extend the work waiting period */ 2075 else if (sc->dataByte == 0x60) 2076 { 2077 t0RecvByteSM(sc,t0rbcStart); 2078 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2079 } 2080 2081 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 2082 /* see if we have a SW1 byte */ 2083 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 2084 && 2085 sc->dataByte != 0x60) 2086 #else /* XXX XXX XXX cgd */ 2087 /* see if we have a SW1 byte */ 2088 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 2089 && 2090 sc->dataByte != 0x60) 2091 #endif /* XXX XXX XXX cgd */ 2092 { 2093 sc->pIoctlT0->sw1 = sc->dataByte; 2094 sc->t0RecvS = t0rsRecvSW2; 2095 t0RecvByteSM(sc,t0rbcStart); 2096 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2097 } 2098 2099 /* got bad data byte, log error and get out */ 2100 else 2101 { 2102 sc->status = ERROR_BAD_PROCEDURE_BYTE; 2103 2104 /* change state */ 2105 sc->t0RecvS = t0rsIdle; 2106 masterSM(sc,mcT0Recv); 2107 } 2108 break; 2109 2110 default: 2111 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2112 break; 2113 } 2114 break; 2115 2116 case t0rsRecvByte: 2117 switch (cmd) 2118 { 2119 case gcT0RecvByte: 2120 /* clock in byte */ 2121 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2122 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2123 sc->dataCount++; 2124 2125 2126 if (sc->dataCount < sc->dataMax) 2127 { 2128 /* get procedure byte */ 2129 sc->t0RecvS = t0rsRecvProcedure; 2130 } 2131 2132 else 2133 { 2134 ASSERT(sc->dataCount == sc->dataMax); 2135 sc->t0RecvS = t0rsRecvSW1; 2136 } 2137 2138 // ask for another byte 2139 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2140 t0RecvByteSM(sc,t0rbcStart); 2141 break; 2142 2143 default: 2144 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2145 break; 2146 } 2147 break; 2148 2149 case t0rsRecvData: 2150 switch (cmd) 2151 { 2152 case gcT0RecvByte: 2153 /* clock in data */ 2154 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2155 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2156 sc->dataCount++; 2157 2158 /* decide if we have all data */ 2159 if (sc->dataCount >= sc->dataMax) 2160 { 2161 KERN_DEBUG (scrdebug, T0_RECV_SM_DEBUG_INFO,("\t\tt0RecvSM: changing state to t0rsRecvSW1\n")); 2162 ASSERT(sc->dataCount == sc->dataMax); 2163 sc->t0RecvS = t0rsRecvSW1; 2164 } 2165 2166 /* ask for another byte */ 2167 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2168 t0RecvByteSM(sc,t0rbcStart); 2169 break; 2170 2171 default: 2172 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2173 break; 2174 } 2175 break; 2176 2177 case t0rsRecvSW1: 2178 switch (cmd) 2179 { 2180 case gcT0RecvByte: 2181 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2182 sc->pIoctlT0->sw1 = sc->dataByte; 2183 2184 sc->t0RecvS = t0rsRecvSW2; 2185 t0RecvByteSM(sc,t0rbcStart); 2186 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2187 break; 2188 default: 2189 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2190 break; 2191 } 2192 break; 2193 2194 case t0rsRecvSW2: 2195 switch (cmd) 2196 { 2197 case gcT0RecvByte: 2198 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2199 sc->pIoctlT0->sw2 = sc->dataByte; 2200 2201 sc->t0RecvS = t0rsIdle; 2202 masterSM(sc,mcT0Recv); 2203 break; 2204 2205 default: 2206 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2207 break; 2208 } 2209 break; 2210 2211 default: 2212 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2213 break; 2214 } 2215 } 2216 2217 2218 /* 2219 **++ 2220 ** FUNCTIONAL DESCRIPTION: 2221 ** 2222 ** coldResetSM 2223 ** 2224 ** This state machine switches on the power, clock and reset pins 2225 ** in the correct order/timing. 2226 ** It is a low level bit-bashing state machine. 2227 ** 2228 ** 2229 ** FORMAL PARAMETERS: 2230 ** 2231 ** sc - Pointer to the softc structure. 2232 ** cmd - command to this machine 2233 ** 2234 ** IMPLICIT INPUTS: 2235 ** 2236 ** sc->coldResetS state of this machine 2237 ** 2238 ** IMPLICIT OUTPUTS: 2239 ** 2240 ** nill 2241 ** 2242 ** FUNCTION VALUE: 2243 ** 2244 ** nill 2245 ** 2246 ** SIDE EFFECTS: 2247 ** 2248 ** signals to card are on 2249 **-- 2250 */ 2251 static void coldResetSM(struct scr_softc * sc,int cmd) 2252 { 2253 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2254 2255 switch (sc->coldResetS) 2256 { 2257 case crsIdle: 2258 switch (cmd) 2259 { 2260 case crcStart: 2261 scrSetReset(true); 2262 scrSetClock(true); 2263 scrSetDataHighZ(); 2264 scrSetPower(true); 2265 2266 /* start a t2 timer */ 2267 scrTimeout(coldResetSM,sc,crcT2,T_t2); 2268 sc->coldResetS = crsT2Wait; 2269 break; 2270 2271 default: 2272 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2273 break; 2274 } 2275 break; 2276 2277 case crsT2Wait: 2278 switch (cmd) 2279 { 2280 case crcT2: 2281 /* turn off rst */ 2282 scrSetReset(false); 2283 2284 /* tell master state machine that we are all done */ 2285 sc->coldResetS = crsIdle; 2286 masterSM(sc,mcColdReset); 2287 break; 2288 2289 default: 2290 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2291 break; 2292 } 2293 break; 2294 2295 2296 default: 2297 INVALID_STATE_CMD(sc,sc->coldResetS,cmd); 2298 break; 2299 } 2300 } 2301 2302 /* 2303 **++ 2304 ** FUNCTIONAL DESCRIPTION: 2305 ** 2306 ** ATRSM 2307 ** 2308 ** This is the Answer To Reset State Machine. It is responsible 2309 ** for performing the Answer To Reset as specified in ISO 7816-3. 2310 ** It is mid level protocol state machine. 2311 ** 2312 ** Once started, this machine is driven entirely via the 2313 ** FIQ/timeout structure. 2314 ** 2315 ** 2316 ** During the first byte, we have to check if the card is operating 2317 ** at full speed or half speed. The first couple of bits are 2318 ** checked to see if it is 1/2 speed, and if so, the clock is changed 2319 ** and the state adjustes 2320 ** 2321 ** At the end of the first byte we have to determin the logic being 2322 ** used by the card, ie is it active high/low and msb/lsb. 2323 ** 2324 ** 2325 ** FORMAL PARAMETERS: 2326 ** 2327 ** sc - Pointer to the softc structure. 2328 ** cmd - command to this machine 2329 ** 2330 ** IMPLICIT INPUTS: 2331 ** 2332 ** sc->pIoctlAtr->atr data from card 2333 ** sc->pIoctlT0->sw1 command status from card 2334 ** sc->pIoctlT0->sw2 command status from card 2335 ** sc->status error status from this machine 2336 ** 2337 ** IMPLICIT OUTPUTS: 2338 ** 2339 ** sc->pIoctlOn->atrBuf data from ATR sequence 2340 ** sc->pIoctlOn->atrLen size of data from ATR sequence 2341 ** sc->status error status from this machine 2342 ** 2343 ** 2344 ** FUNCTION VALUE: 2345 ** 2346 ** nill 2347 ** 2348 ** SIDE EFFECTS: 2349 ** 2350 ** nill 2351 **-- 2352 */ 2353 static void ATRSM (struct scr_softc * sc,int cmd) 2354 { 2355 int lc; 2356 int tck; 2357 2358 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2359 2360 /* 2361 ** check for major failures that are common to most states 2362 */ 2363 if (cmd == atrcT3 || 2364 cmd == atrcTWorkWaiting || 2365 cmd == gcT0RecvByteErr 2366 ) 2367 { 2368 switch(cmd) 2369 { 2370 case atrcT3: 2371 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2372 sc->status = ERROR_ATR_T3; 2373 t0RecvByteSM(sc,t0rbcAbort); 2374 break; 2375 2376 case atrcTWorkWaiting: 2377 scrUntimeout (ATRSM,sc,atrcT3); 2378 sc->status = ERROR_WORK_WAITING; 2379 t0RecvByteSM(sc,t0rbcAbort); 2380 break; 2381 2382 case gcT0RecvByteErr: 2383 scrUntimeout (ATRSM,sc,atrcT3); 2384 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2385 /* done set status, its already set */ 2386 break; 2387 2388 default: 2389 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2390 break; 2391 } 2392 2393 /* change state */ 2394 sc->ATRS = atrsIdle; 2395 masterSM(sc,mcATR); 2396 return; 2397 } 2398 2399 switch (sc->ATRS) 2400 { 2401 case atrsIdle: 2402 switch (cmd) 2403 { 2404 case atrcStart: 2405 /* lets start looking */ 2406 sc->ATRS = atrsTS; 2407 sc->pIoctlOn->atrLen = 0; 2408 sc->t0ByteParent = ATRSM; 2409 scrTimeout(ATRSM,sc,atrcT3,T_t3 *2); /* by 2 to accommodate 1/2 freq cards */ 2410 t0RecvByteSM(sc,t0rbcStart); 2411 break; 2412 2413 default: 2414 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2415 break; 2416 } 2417 break; 2418 2419 case atrsTS: 2420 switch (cmd) 2421 { 2422 case gcT0RecvByte: 2423 scrUntimeout(ATRSM,sc,atrcT3); 2424 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2425 sc->pIoctlOn->atrLen++; 2426 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2427 { 2428 #ifdef SCR_DEBUG 2429 DEBUGGER; 2430 #endif 2431 sc->status = ERROR_ATR_TCK; 2432 sc->ATRS = atrsIdle; 2433 masterSM(sc,mcATR); 2434 } 2435 else 2436 { 2437 /* move onto recv T0 */ 2438 sc->ATRS = atrsT0; 2439 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2440 t0RecvByteSM(sc,t0rbcStart); 2441 } 2442 break; 2443 2444 default: 2445 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2446 break; 2447 } 2448 break; 2449 2450 case atrsT0: 2451 switch (cmd) 2452 { 2453 case gcT0RecvByte: 2454 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2455 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2456 sc->pIoctlOn->atrLen++; 2457 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2458 { 2459 #ifdef SCR_DEBUG 2460 printf("atrLen >= ATR_BUF_MAX\n"); 2461 DEBUGGER; 2462 #endif 2463 sc->status = ERROR_ATR_TCK; 2464 sc->ATRS = atrsIdle; 2465 masterSM(sc,mcATR); 2466 } 2467 else 2468 { 2469 /* store Y & K */ 2470 sc->atrY = sc->dataByte & 0xf0; 2471 sc->atrK = sc->dataByte & 0x0f; 2472 2473 sc->atrTABCDx = 1; 2474 sc->atrKCount = 1; 2475 2476 /* if there are no TDx following set T0 protocol */ 2477 if (!ISSET(sc->atrY,ATR_Y_TD)) 2478 { 2479 sc->protocolType = PROTOCOL_T0; 2480 } 2481 2482 2483 if (sc->atrY) 2484 { 2485 2486 sc->ATRS = atrsTABCD; 2487 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2488 t0RecvByteSM(sc,t0rbcStart); 2489 } 2490 2491 else if (sc->atrK) 2492 { 2493 sc->ATRS = atrsTK; 2494 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2495 t0RecvByteSM(sc,t0rbcStart); 2496 } 2497 2498 else if (sc->protocolType != PROTOCOL_T0) 2499 { 2500 sc->ATRS = atrsTCK; 2501 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2502 t0RecvByteSM(sc,t0rbcStart); 2503 } 2504 2505 else /* got all of ATR */ 2506 { 2507 sc->ATRS = atrsIdle; 2508 masterSM(sc,mcATR); 2509 } 2510 } 2511 break; 2512 2513 2514 default: 2515 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2516 break; 2517 } 2518 break; 2519 2520 2521 case atrsTABCD: 2522 switch (cmd) 2523 { 2524 case gcT0RecvByte: 2525 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2526 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2527 sc->pIoctlOn->atrLen++; 2528 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2529 { 2530 #ifdef SCR_DEBUG 2531 printf("atrLen >= ATR_BUF_MAX\n"); 2532 DEBUGGER; 2533 #endif 2534 sc->status = ERROR_ATR_TCK; 2535 sc->ATRS = atrsIdle; 2536 masterSM(sc,mcATR); 2537 } 2538 else 2539 { 2540 if (sc->atrY & ATR_Y_TA) 2541 { 2542 sc->atrY &= ~ATR_Y_TA; 2543 if (sc->atrTABCDx == 1) 2544 { 2545 sc->Fi = FI2Fi[((sc->dataByte >> 4) & 0x0f)]; 2546 if (sc->Fi == 0) 2547 { 2548 sc->status = ERROR_ATR_FI_INVALID; 2549 sc->Fi = Fi_DEFAULT; 2550 } 2551 2552 sc->Di = DI2Di[(sc->dataByte & 0x0f)]; 2553 if (sc->Di == 0) 2554 { 2555 sc->status = ERROR_ATR_DI_INVALID; 2556 sc->Di = Di_DEFAULT; 2557 } 2558 2559 } 2560 } 2561 2562 else if (sc->atrY & ATR_Y_TB) 2563 { 2564 sc->atrY &= ~ATR_Y_TB; 2565 } 2566 2567 else if (sc->atrY & ATR_Y_TC) 2568 { 2569 sc->atrY &= ~ATR_Y_TC; 2570 if (sc->atrTABCDx == 1) 2571 { 2572 sc->N = sc->dataByte; 2573 } 2574 2575 if (sc->atrTABCDx == 2) 2576 { 2577 sc->Wi = sc->dataByte; 2578 } 2579 } 2580 2581 else 2582 { 2583 ASSERT(sc->atrY & ATR_Y_TD); 2584 sc->atrY &= ~ATR_Y_TD; 2585 2586 /* copy across the y section of TD */ 2587 sc->atrY = sc->dataByte; 2588 sc->atrY &= 0xf0; 2589 2590 /* step to the next group of TABCD */ 2591 sc->atrTABCDx++; 2592 2593 /* store protocols */ 2594 sc->protocolType = (1 << (sc->dataByte &0x0f)); 2595 } 2596 2597 2598 /* see what we should do next */ 2599 if (sc->atrY) 2600 { 2601 /* just stay in the same state */ 2602 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2603 t0RecvByteSM(sc,t0rbcStart); 2604 } 2605 2606 else if (sc->atrK) 2607 { 2608 sc->ATRS = atrsTK; 2609 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2610 t0RecvByteSM(sc,t0rbcStart); 2611 } 2612 2613 else if (sc->protocolType != PROTOCOL_T0) 2614 { 2615 sc->ATRS = atrsTCK; 2616 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2617 t0RecvByteSM(sc,t0rbcStart); 2618 } 2619 2620 else /* got all of ATR */ 2621 { 2622 sc->ATRS = atrsIdle; 2623 masterSM(sc,mcATR); 2624 } 2625 } 2626 2627 break; 2628 2629 2630 default: 2631 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2632 break; 2633 } 2634 break; 2635 2636 case atrsTK: 2637 switch (cmd) 2638 { 2639 case gcT0RecvByte: 2640 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2641 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2642 sc->pIoctlOn->atrLen++; 2643 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2644 { 2645 #ifdef SCR_DEBUG 2646 printf("atrLen >= ATR_BUF_MAX\n"); 2647 DEBUGGER; 2648 #endif 2649 sc->status = ERROR_ATR_TCK; 2650 sc->ATRS = atrsIdle; 2651 masterSM(sc,mcATR); 2652 } 2653 else 2654 { 2655 2656 if (sc->atrKCount < sc->atrK) 2657 { 2658 sc->atrKCount++; 2659 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2660 t0RecvByteSM(sc,t0rbcStart); 2661 } 2662 2663 2664 else if (sc->protocolType != PROTOCOL_T0) 2665 { 2666 sc->ATRS = atrsTCK; 2667 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2668 t0RecvByteSM(sc,t0rbcStart); 2669 } 2670 2671 else /* got all of ATR */ 2672 { 2673 sc->ATRS = atrsIdle; 2674 masterSM(sc,mcATR); 2675 } 2676 } 2677 break; 2678 2679 default: 2680 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2681 break; 2682 } 2683 break; 2684 2685 case atrsTCK: 2686 switch (cmd) 2687 { 2688 case gcT0RecvByte: 2689 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2690 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2691 sc->pIoctlOn->atrLen++; 2692 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2693 { 2694 #ifdef SCR_DEBUG 2695 printf("atrLen >= ATR_BUF_MAX\n"); 2696 DEBUGGER; 2697 #endif 2698 sc->status = ERROR_ATR_TCK; 2699 sc->ATRS = atrsIdle; 2700 masterSM(sc,mcATR); 2701 } 2702 else 2703 { 2704 tck = 0; 2705 for (lc = 1; lc < sc->pIoctlOn->atrLen-1; lc++) 2706 { 2707 tck ^= sc->pIoctlOn->atrBuf[lc]; 2708 } 2709 2710 if (tck == sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen-1]) 2711 { 2712 sc->ATRS = atrsIdle; 2713 masterSM(sc,mcATR); 2714 } 2715 else 2716 { 2717 sc->status = ERROR_ATR_TCK; 2718 sc->ATRS = atrsIdle; 2719 masterSM(sc,mcATR); 2720 } 2721 } 2722 break; 2723 2724 default: 2725 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2726 break; 2727 } 2728 break; 2729 2730 2731 2732 default: 2733 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2734 break; 2735 } 2736 } 2737 2738 2739 2740 /* 2741 **++ 2742 ** FUNCTIONAL DESCRIPTION: 2743 ** 2744 ** t0RecvByteSM 2745 ** 2746 ** This state machine attempts to read 1 byte from a card. 2747 ** It is a low level bit-bashing state machine. 2748 ** 2749 ** Data from the card is async, so the machine scans at 2750 ** 5 times the data rate looking for a state bit. Once 2751 ** a start bit has been found, it waits for the middle of 2752 ** the bit and starts sampling at the bit rate. 2753 ** 2754 ** Several mid level machines can use this machine, so the value 2755 ** sc->t0ByteParent is used to point to back to the mid level machine 2756 ** 2757 ** 2758 ** FORMAL PARAMETERS: 2759 ** 2760 ** sc - Pointer to the softc structure. 2761 ** cmd - command to this machine 2762 ** 2763 ** IMPLICIT INPUTS: 2764 ** 2765 ** sc->t0RecvByteS state of this machine 2766 ** sc->t0ByteParent mid level machine that started this machine 2767 ** 2768 ** IMPLICIT OUTPUTS: 2769 ** 2770 ** sc->shiftByte byte read from the card 2771 ** sc->status error value if could not read byte 2772 ** 2773 ** FUNCTION VALUE: 2774 ** 2775 ** nill 2776 ** 2777 ** SIDE EFFECTS: 2778 ** 2779 ** nill 2780 **-- 2781 */ 2782 static void t0RecvByteSM(struct scr_softc* sc,int cmd) 2783 { 2784 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2785 2786 if (cmd == t0rbcAbort) 2787 { 2788 /* kill all the timers */ 2789 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartEdge); 2790 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartMid); 2791 scrUntimeout(t0RecvByteSM, sc,t0rbcTClockData); 2792 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStart); 2793 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStop); 2794 2795 scrSetDataHighZ(); 2796 sc->t0RecvByteS = t0rbsIdle; 2797 return; 2798 } 2799 2800 2801 switch (sc->t0RecvByteS) 2802 { 2803 case t0rbsIdle: 2804 switch (cmd) 2805 { 2806 case t0rbcStart: 2807 /* set initial conditions */ 2808 sc->shiftBits = 0; 2809 sc->shiftByte = 0; 2810 sc->shiftParity = 0; 2811 sc->shiftParityCount = 0; 2812 scrClkAdj(sc->clkCountStartRecv); /* recv data clock running at 5 times */ 2813 2814 /* check if start bit is already here */ 2815 //if (scrGetData()) 2816 if (1) 2817 { 2818 /* didn't find it, keep looking */ 2819 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2820 sc->t0RecvByteS = t0rbsFindStartEdge; 2821 } 2822 else 2823 { 2824 /* found start bit, look for mid bit */ 2825 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv); 2826 sc->t0RecvByteS = t0rbsFindStartMid; 2827 } 2828 break; 2829 2830 2831 2832 default: 2833 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2834 break; 2835 } 2836 break; 2837 2838 2839 case t0rbsFindStartEdge: 2840 switch (cmd) 2841 { 2842 case t0rbcTFindStartEdge: 2843 if (scrGetData()) 2844 { 2845 /* didn't find it, keep looking */ 2846 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2847 } 2848 else 2849 { 2850 /* found start bit, look for mid bit */ 2851 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv * 2); 2852 sc->t0RecvByteS = t0rbsFindStartMid; 2853 } 2854 break; 2855 2856 2857 default: 2858 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2859 break; 2860 } 2861 break; 2862 2863 case t0rbsFindStartMid: 2864 switch (cmd) 2865 { 2866 case t0rbcTFindStartMid: 2867 if (scrGetData()) 2868 { 2869 /* found glitch, so just go back to hunting */ 2870 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2871 sc->t0RecvByteS = t0rbsFindStartEdge; 2872 } 2873 else 2874 { 2875 /* found start bit, start clocking in data */ 2876 TOGGLE_TEST_PIN(); 2877 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2878 sc->t0RecvByteS = t0rbsClockData; 2879 } 2880 break; 2881 2882 2883 default: 2884 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2885 break; 2886 } 2887 break; 2888 2889 2890 case t0rbsClockData: 2891 TOGGLE_TEST_PIN(); 2892 switch (cmd) 2893 { 2894 case t0rbcTClockData: 2895 if (sc->shiftBits < 8) 2896 { 2897 if (sc->convention == CONVENTION_INVERSE || 2898 sc->convention == CONVENTION_UNKNOWN) 2899 { 2900 /* logic 1 is low, msb is first */ 2901 sc->shiftByte <<= 1; 2902 sc->shiftByte &= 0xfe; 2903 if (!scrGetData()) 2904 { 2905 sc->shiftByte |= 0x01; 2906 sc->shiftParity++; 2907 } 2908 } 2909 else 2910 { 2911 ASSERT(sc->convention == CONVENTION_DIRECT); 2912 /* logic 1 is high, lsb is first */ 2913 sc->shiftByte = sc->shiftByte >> 1; 2914 sc->shiftByte &= 0x7f; 2915 if (scrGetData()) 2916 { 2917 sc->shiftParity++; 2918 sc->shiftByte |= 0x80; 2919 } 2920 } 2921 sc->shiftBits++; 2922 2923 2924 /* in TS byte, check if we have a card that works at 1/2 freq */ 2925 if (sc->convention == CONVENTION_UNKNOWN && /* in TS byte */ 2926 sc->shiftBits == 3 && /* test at bit 3 in word */ 2927 sc->shiftByte == 4 && /* check for 1/2 freq pattern */ 2928 sc->cardFreq == CARD_FREQ_DEF) /* only do this if at full freq */ 2929 { 2930 /* adjust counts down to 1/2 freq */ 2931 sc->cardFreq = CARD_FREQ_DEF / 2; 2932 sc->clkCountStartRecv = sc->clkCountStartRecv *2; 2933 sc->clkCountDataRecv = sc->clkCountDataRecv *2; 2934 sc->clkCountDataSend = sc->clkCountDataSend *2; 2935 2936 2937 /* adjust this so that we have clocked in only fist bit of TS */ 2938 sc->shiftParity = 0; 2939 sc->shiftByte = 0; 2940 sc->shiftBits = 1; 2941 2942 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,(sc->clkCountDataRecv * 3) /4); 2943 } 2944 else 2945 { 2946 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2947 } 2948 } 2949 2950 /* clock in parity bit */ 2951 else if (sc->shiftBits == 8) 2952 { 2953 if (sc->convention == CONVENTION_INVERSE) 2954 { 2955 if (!scrGetData()) 2956 { 2957 sc->shiftParity++; 2958 } 2959 } 2960 else if (sc->convention == CONVENTION_DIRECT) 2961 { 2962 if (scrGetData()) 2963 { 2964 sc->shiftParity++; 2965 } 2966 } 2967 2968 2969 else 2970 { 2971 /* sc->convention not set so sort it out */ 2972 ASSERT(sc->convention == CONVENTION_UNKNOWN); 2973 if (sc->shiftByte == CONVENIONT_INVERSE_ID && scrGetData()) 2974 { 2975 sc->convention = CONVENTION_INVERSE; 2976 sc->shiftParity = 0; /* force good parity */ 2977 } 2978 2979 else if (sc->shiftByte == CONVENTION_DIRECT_ID && scrGetData()) 2980 { 2981 sc->shiftByte = CONVENTION_DIRECT_FIX; 2982 sc->convention = CONVENTION_DIRECT; 2983 sc->shiftParity = 0; /* force good parity */ 2984 } 2985 2986 else 2987 { 2988 sc->shiftParity = 1; /* force bad parity */ 2989 } 2990 } 2991 2992 2993 if ((sc->shiftParity & 01) == 0) 2994 { 2995 sc->shiftBits++; 2996 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2997 } 2998 else 2999 { 3000 /* got parity error */ 3001 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3002 { 3003 sc->shiftParityCount++; 3004 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStart,sc->clkCountDataRecv); 3005 sc->t0RecvByteS = t0rbsSendError; 3006 } 3007 else 3008 3009 { 3010 /* too many parity errors, just give up on this sc->dataByte */ 3011 sc->status = ERROR_PARITY; 3012 sc->t0RecvByteS = t0rbsIdle; 3013 sc->t0ByteParent(sc,gcT0RecvByteErr); 3014 } 3015 } 3016 } 3017 3018 else 3019 { 3020 sc->dataByte = sc->shiftByte; 3021 sc->t0RecvByteS = t0rbsIdle; 3022 sc->t0ByteParent(sc,gcT0RecvByte); 3023 } 3024 break; 3025 3026 default: 3027 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3028 break; 3029 } 3030 break; 3031 3032 3033 case t0rbsSendError: 3034 TOGGLE_TEST_PIN(); 3035 switch (cmd) 3036 { 3037 case t0rbcTErrorStart: 3038 /* start sending error bit */ 3039 scrSetData(false); 3040 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStop,sc->clkCountDataRecv * 2); 3041 break; 3042 3043 case t0rbcTErrorStop: 3044 /* stop sending parity error & reset information*/ 3045 scrSetData(true); 3046 sc->shiftBits = 0; 3047 sc->shiftByte = 0; 3048 sc->shiftParity = 0; 3049 3050 /* start looking for start bit */ 3051 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,1); 3052 sc->t0RecvByteS = t0rbsFindStartEdge; 3053 break; 3054 3055 default: 3056 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3057 break; 3058 } 3059 break; 3060 3061 3062 default: 3063 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3064 break; 3065 } 3066 } 3067 3068 /* 3069 **++ 3070 ** FUNCTIONAL DESCRIPTION: 3071 ** 3072 ** t0SendByteSM 3073 ** 3074 ** This state machine writes 1 byte to a card. 3075 ** It is a low level bit-bashing state machine. 3076 ** 3077 ** 3078 ** Several mid level machines can use this machine, so the value 3079 ** sc->t0ByteParent is used to point to back to the mid level machine 3080 ** 3081 ** FORMAL PARAMETERS: 3082 ** 3083 ** sc - Pointer to the softc structure. 3084 ** cmd - command to this machine 3085 ** 3086 ** IMPLICIT INPUTS: 3087 ** 3088 ** sc->t0SendByteS state of this machine 3089 ** sc->shiftByte byte to write to the card 3090 ** 3091 ** IMPLICIT OUTPUTS: 3092 ** 3093 ** sc->status error value if could not read byte 3094 ** 3095 ** FUNCTION VALUE: 3096 ** 3097 ** nill 3098 ** 3099 ** SIDE EFFECTS: 3100 ** 3101 ** nill 3102 **-- 3103 */ 3104 //int bigTroubleTest = 0; 3105 static void t0SendByteSM (struct scr_softc * sc,int cmd) 3106 { 3107 //if(bigTroubleTest == 2000) 3108 //{ 3109 // INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3110 // bigTroubleTest = 0; 3111 //} 3112 // 3113 //bigTroubleTest++; 3114 3115 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 3116 3117 if (cmd == t0sbcAbort) 3118 { 3119 /* kill all the timers */ 3120 scrUntimeout(t0SendByteSM, sc, t0sbcTGuardTime); 3121 scrUntimeout(t0SendByteSM, sc, t0sbcTClockData); 3122 scrUntimeout(t0SendByteSM, sc, t0sbcTError); 3123 3124 scrSetDataHighZ(); 3125 return; 3126 } 3127 3128 3129 switch (sc->t0SendByteS) 3130 { 3131 case t0sbsIdle: 3132 switch (cmd) 3133 { 3134 case t0sbcStart: 3135 /* set initial conditions */ 3136 sc->shiftBits = 0; 3137 sc->shiftParity = 0; 3138 sc->shiftParityCount = 0; 3139 sc->shiftByte = sc->dataByte; 3140 3141 scrClkAdj(sc->clkCountDataSend); /* send data clock running at 1 ETU */ 3142 3143 /* check if we have to wait for guard time */ 3144 if (0) /* possible optimization here */ 3145 { 3146 /* can send start bit now */ 3147 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3148 scrSetData(false); 3149 sc->t0SendByteS = t0sbsClockData; 3150 } 3151 else 3152 { 3153 /* need to wait for guard time */ 3154 scrTimeout(t0SendByteSM,sc,t0sbcTGuardTime,sc->clkCountDataSend * (12 + sc->N)); 3155 sc->t0SendByteS = t0sbsWaitGuardTime; 3156 3157 } 3158 break; 3159 3160 default: 3161 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3162 break; 3163 } 3164 break; 3165 3166 3167 case t0sbsWaitGuardTime: 3168 switch (cmd) 3169 { 3170 case t0sbcTGuardTime: 3171 TOGGLE_TEST_PIN(); 3172 /* set start bit */ 3173 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3174 scrSetData(false); 3175 sc->t0SendByteS = t0sbsClockData; 3176 break; 3177 3178 default: 3179 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3180 break; 3181 } 3182 break; 3183 3184 3185 case t0sbsClockData: 3186 switch (cmd) 3187 { 3188 case t0sbcTClockData: 3189 TOGGLE_TEST_PIN(); 3190 /* clock out data bit */ 3191 if (sc->shiftBits < 8) 3192 { 3193 if (sc->convention == CONVENTION_INVERSE) 3194 { 3195 if (sc->shiftByte & 0x80) 3196 { 3197 scrSetData(false); 3198 sc->shiftParity++; 3199 } 3200 else 3201 { 3202 scrSetData(true); 3203 } 3204 sc->shiftByte = sc->shiftByte << 1; 3205 } 3206 else 3207 { 3208 ASSERT(sc->convention == CONVENTION_DIRECT); 3209 if (sc->shiftByte & 0x01) 3210 { 3211 scrSetData(true); 3212 sc->shiftParity++; 3213 } 3214 else 3215 { 3216 scrSetData(false); 3217 } 3218 sc->shiftByte = sc->shiftByte >> 1; 3219 } 3220 sc->shiftBits++; 3221 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3222 } 3223 3224 /* clock out parity bit */ 3225 else if (sc->shiftBits == 8) 3226 { 3227 if ( ((sc->shiftParity & 0x01) && (sc->convention == CONVENTION_INVERSE)) || 3228 (!(sc->shiftParity & 0x01) && (sc->convention == CONVENTION_DIRECT)) ) 3229 { 3230 scrSetData(false); 3231 } 3232 else 3233 { 3234 scrSetData(true); 3235 } 3236 sc->shiftBits++; 3237 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3238 } 3239 3240 /* all data shifted out, move onto next state */ 3241 else 3242 { 3243 ASSERT(sc->shiftBits > 8); 3244 scrSetData(true); 3245 scrTimeout(t0SendByteSM,sc,t0sbcTError,sc->clkCountDataSend); 3246 sc->t0SendByteS = t0sbsWaitError; 3247 } 3248 break; 3249 3250 default: 3251 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3252 break; 3253 } 3254 break; 3255 3256 case t0sbsWaitError: 3257 switch (cmd) 3258 { 3259 case t0sbcTError: 3260 /* no error indicated*/ 3261 if (scrGetData()) 3262 { 3263 sc->t0SendByteS = t0sbsIdle; 3264 sc->t0ByteParent(sc,gcT0SendByte); 3265 } 3266 3267 /* got error */ 3268 else 3269 { 3270 /* got parity error */ 3271 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3272 { 3273 sc->shiftParityCount++; 3274 scrTimeout(t0SendByteSM,sc,t0sbcTResend,sc->clkCountDataSend * 2); 3275 sc->t0SendByteS = t0sbsWaitResend; 3276 } 3277 else 3278 { 3279 /* too many parity errors, just give up on this sc->dataByte */ 3280 sc->status = ERROR_PARITY; 3281 sc->t0SendByteS = t0sbsIdle; 3282 sc->t0ByteParent(sc,gcT0SendByteErr); 3283 } 3284 } 3285 break; 3286 3287 default: 3288 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3289 break; 3290 } 3291 break; 3292 3293 case t0sbsWaitResend: 3294 switch (cmd) 3295 { 3296 case t0sbcTResend: 3297 sc->shiftBits = 0; 3298 sc->shiftParity = 0; 3299 sc->shiftByte = sc->dataByte; 3300 /* set start bit */ 3301 3302 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3303 scrSetData(false); 3304 sc->t0SendByteS = t0sbsClockData; 3305 break; 3306 3307 default: 3308 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3309 break; 3310 } 3311 break; 3312 3313 3314 default: 3315 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3316 break; 3317 } 3318 } 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 /* 3331 **++ 3332 ** FUNCTIONAL DESCRIPTION: 3333 ** 3334 ** cardOff 3335 ** 3336 ** Turn all signals to the card off 3337 ** 3338 ** FORMAL PARAMETERS: 3339 ** 3340 ** sc - Pointer to the softc structure. 3341 ** 3342 ** IMPLICIT INPUTS: 3343 ** 3344 ** nill 3345 ** 3346 ** IMPLICIT OUTPUTS: 3347 ** 3348 ** nill 3349 ** 3350 ** FUNCTION VALUE: 3351 ** 3352 ** nill 3353 ** 3354 ** SIDE EFFECTS: 3355 ** 3356 ** nill 3357 **-- 3358 */ 3359 static void cardOff (struct scr_softc * sc) 3360 { 3361 scrSetReset(true); 3362 scrSetDataHighZ(); 3363 scrSetClock(false); 3364 scrSetPower(false); 3365 } 3366 3367 3368 3369 3370 /* 3371 ** 3372 ** 3373 ** **************** timer routines *************** 3374 ** 3375 */ 3376 3377 /* 3378 **++ 3379 ** FUNCTIONAL DESCRIPTION: 3380 ** 3381 ** scrClkInit 3382 ** 3383 ** Init the callout queues. The callout queues are used 3384 ** by the timeout/untimeout queues 3385 ** 3386 ** FORMAL PARAMETERS: 3387 ** 3388 ** nill 3389 ** 3390 ** IMPLICIT INPUTS: 3391 ** 3392 ** nill 3393 ** 3394 ** IMPLICIT OUTPUTS: 3395 ** 3396 ** nill 3397 ** 3398 ** FUNCTION VALUE: 3399 ** 3400 ** nill 3401 ** 3402 ** SIDE EFFECTS: 3403 ** 3404 ** nill 3405 **-- 3406 */ 3407 static void scrClkInit(void) 3408 { 3409 3410 int lc; 3411 Callout *c; 3412 Callout *new; 3413 3414 scrClkCallTodo.c_next = NULL; 3415 scrClkCallFree = &scrClkCalloutArray[0]; 3416 c = scrClkCallFree; 3417 3418 for (lc = 1; lc < SCR_CLK_CALLOUT_COUNT; lc++) 3419 { 3420 new = &scrClkCalloutArray[lc]; 3421 c->c_next = new; 3422 c = new; 3423 } 3424 3425 c->c_next = NULL; 3426 } 3427 3428 3429 /* 3430 **++ 3431 ** FUNCTIONAL DESCRIPTION: 3432 ** 3433 ** scrClkStart 3434 ** 3435 ** This function starts the clock running. The clock is reall the 3436 ** HAT clock (High Available Timer) that is using a FIQ (fast interrupt 3437 ** request). 3438 ** 3439 ** FORMAL PARAMETERS: 3440 ** 3441 ** sc - Pointer to the softc structure. 3442 ** countPerTick - value for T2 timer that drives FIQ 3443 ** 3444 ** IMPLICIT INPUTS: 3445 ** 3446 ** nill 3447 ** 3448 ** IMPLICIT OUTPUTS: 3449 ** 3450 ** nill 3451 ** 3452 ** FUNCTION VALUE: 3453 ** 3454 ** nill 3455 ** 3456 ** SIDE EFFECTS: 3457 ** 3458 ** nill 3459 **-- 3460 */ 3461 static void scrClkStart(struct scr_softc * sc,int countPerTick) 3462 { 3463 u_int savedInts; 3464 3465 savedInts = disable_interrupts(I32_bit | F32_bit); 3466 3467 3468 3469 ASSERT(scrClkCallTodo.c_next == NULL); 3470 ASSERT(!scrClkEnable); 3471 scrClkEnable = 1; 3472 scrClkCount = countPerTick; 3473 3474 hatClkOn(countPerTick, 3475 hatClkIrq, 3476 0xdeadbeef, 3477 hatStack + HATSTACKSIZE - sizeof(unsigned), 3478 myHatWedge); 3479 3480 restore_interrupts(savedInts); 3481 } 3482 3483 /* 3484 **++ 3485 ** FUNCTIONAL DESCRIPTION: 3486 ** 3487 ** scrClkAdj 3488 ** 3489 ** Adjusts the frequence of the clock 3490 ** 3491 ** FORMAL PARAMETERS: 3492 ** 3493 ** count - new value for T2 timer that drives FIQ 3494 ** 3495 ** IMPLICIT INPUTS: 3496 ** 3497 ** nill 3498 ** 3499 ** IMPLICIT OUTPUTS: 3500 ** 3501 ** nill 3502 ** 3503 ** FUNCTION VALUE: 3504 ** 3505 ** nill 3506 ** 3507 ** SIDE EFFECTS: 3508 ** 3509 ** nill 3510 **-- 3511 */ 3512 static void scrClkAdj (int count) 3513 { 3514 u_int savedInts; 3515 3516 if (count != scrClkCount) 3517 { 3518 savedInts = disable_interrupts(I32_bit | F32_bit); 3519 3520 ASSERT(scrClkEnable); 3521 3522 scrClkCount = count; 3523 hatClkAdjust(count); 3524 3525 restore_interrupts(savedInts); 3526 } 3527 } 3528 3529 /* 3530 **++ 3531 ** FUNCTIONAL DESCRIPTION: 3532 ** 3533 ** scrClkStop 3534 ** 3535 ** Stops the clock 3536 ** 3537 ** FORMAL PARAMETERS: 3538 ** 3539 ** nill 3540 ** 3541 ** 3542 ** IMPLICIT INPUTS: 3543 ** 3544 ** nill 3545 ** 3546 ** IMPLICIT OUTPUTS: 3547 ** 3548 ** nill 3549 ** 3550 ** FUNCTION VALUE: 3551 ** 3552 ** nill 3553 ** 3554 ** SIDE EFFECTS: 3555 ** 3556 ** nill 3557 **-- 3558 */ 3559 static void scrClkStop(void) 3560 { 3561 u_int savedInts; 3562 savedInts = disable_interrupts(I32_bit | F32_bit); 3563 3564 ASSERT(scrClkEnable); 3565 scrClkEnable = 0; 3566 ASSERT(scrClkCallTodo.c_next == NULL); 3567 hatClkOff(); 3568 3569 restore_interrupts(savedInts); 3570 } 3571 3572 3573 3574 /* 3575 **++ 3576 ** FUNCTIONAL DESCRIPTION: 3577 ** 3578 ** hatClkIrq 3579 ** 3580 ** This is what the HAT clock calls. This call drives 3581 ** the timeout queues, which in turn drive the state machines 3582 ** 3583 ** Be very carefully when calling a timeout as the function 3584 ** that is called may in turn do timeout/untimeout calls 3585 ** before returning 3586 ** 3587 ** FORMAL PARAMETERS: 3588 ** 3589 ** int x - not used 3590 ** 3591 ** IMPLICIT INPUTS: 3592 ** 3593 ** nill 3594 ** 3595 ** IMPLICIT OUTPUTS: 3596 ** 3597 ** nill 3598 ** 3599 ** FUNCTION VALUE: 3600 ** 3601 ** nill 3602 ** 3603 ** SIDE EFFECTS: 3604 ** 3605 ** a timeout may be called if it is due 3606 **-- 3607 */ 3608 static void hatClkIrq(int x) 3609 { 3610 register Callout *p1; 3611 register int needsoft =0; 3612 register Callout *c; 3613 register int arg; 3614 register void (*func) __P((struct scr_softc*,int)); 3615 struct scr_softc * sc; 3616 3617 ASSERT(scrClkEnable); 3618 for (p1 = scrClkCallTodo.c_next; p1 != NULL; p1 = p1->c_next) 3619 { 3620 p1->c_time -= scrClkCount; 3621 3622 if (p1->c_time > 0) 3623 { 3624 break; 3625 } 3626 needsoft = 1; 3627 if (p1->c_time == 0) 3628 { 3629 break; 3630 } 3631 } 3632 3633 3634 if (needsoft) 3635 { 3636 while ((c = scrClkCallTodo.c_next) != NULL && c->c_time <= 0) 3637 { 3638 func = c->c_func; 3639 sc = c->c_sc; 3640 arg = c->c_arg; 3641 scrClkCallTodo.c_next = c->c_next; 3642 c->c_next = scrClkCallFree; 3643 scrClkCallFree = c; 3644 (*func)(sc,arg); 3645 } 3646 } 3647 } 3648 3649 /* 3650 **++ 3651 ** FUNCTIONAL DESCRIPTION: 3652 ** 3653 ** myHatWedge 3654 ** 3655 ** Called if the HAT timer becomes clogged/wedged. Not 3656 ** used by this driver, we let upper layers recover 3657 ** from this condition 3658 ** 3659 ** FORMAL PARAMETERS: 3660 ** 3661 ** int nFIQs - not used 3662 ** 3663 ** IMPLICIT INPUTS: 3664 ** 3665 ** nill 3666 ** 3667 ** IMPLICIT OUTPUTS: 3668 ** 3669 ** nill 3670 ** 3671 ** FUNCTION VALUE: 3672 ** 3673 ** nill 3674 ** 3675 ** SIDE EFFECTS: 3676 ** 3677 ** nill 3678 **-- 3679 */ 3680 static void myHatWedge(int nFIQs) 3681 { 3682 #ifdef DEBUG 3683 printf("myHatWedge: nFIQ = %d\n",nFIQs); 3684 #endif 3685 } 3686 3687 3688 3689 /* 3690 **++ 3691 ** FUNCTIONAL DESCRIPTION: 3692 ** 3693 ** scrTimeout 3694 ** 3695 ** Execute a function after a specified length of time. 3696 ** 3697 ** 3698 ** FORMAL PARAMETERS: 3699 ** 3700 ** ftn - function to execute 3701 ** sc - pointer to soft c 3702 ** arg - argument passed to function 3703 ** count - number of T2 counts for timeout 3704 ** 3705 ** IMPLICIT INPUTS: 3706 ** 3707 ** nill 3708 ** 3709 ** IMPLICIT OUTPUTS: 3710 ** 3711 ** nill 3712 ** 3713 ** FUNCTION VALUE: 3714 ** 3715 ** nill 3716 ** 3717 ** SIDE EFFECTS: 3718 ** 3719 ** nill 3720 **-- 3721 */ 3722 3723 static void scrTimeout(ftn, sc, arg, count) 3724 void (*ftn) __P((struct scr_softc*,int)); 3725 struct scr_softc* sc; 3726 int arg; 3727 register int count; 3728 { 3729 3730 register Callout *new, *p, *t; 3731 ASSERT(scrClkEnable); 3732 3733 3734 if (count <= 0) 3735 { 3736 count = 1; 3737 } 3738 3739 3740 /* Fill in the next free fcallout structure. */ 3741 if (scrClkCallFree == NULL) 3742 { 3743 panic("timeout table full"); 3744 } 3745 3746 new = scrClkCallFree; 3747 scrClkCallFree = new->c_next; 3748 new->c_sc = sc; 3749 new->c_arg = arg; 3750 new->c_func = ftn; 3751 3752 /* 3753 * The time for each event is stored as a difference from the time 3754 * of the previous event on the queue. Walk the queue, correcting 3755 * the counts argument for queue entries passed. Correct the counts 3756 * value for the queue entry immediately after the insertion point 3757 * as well. Watch out for negative c_time values; these represent 3758 * overdue events. 3759 */ 3760 for (p = &scrClkCallTodo; (t = p->c_next) != NULL && count > t->c_time; p = t) 3761 { 3762 if (t->c_time > 0) 3763 { 3764 count -= t->c_time; 3765 } 3766 } 3767 3768 3769 new->c_time = count; 3770 if (t != NULL) 3771 { 3772 t->c_time -= count; 3773 } 3774 3775 /* Insert the new entry into the queue. */ 3776 p->c_next = new; 3777 new->c_next = t; 3778 } 3779 3780 /* 3781 **++ 3782 ** FUNCTIONAL DESCRIPTION: 3783 ** 3784 ** scrUntimeout 3785 ** 3786 ** Cancel previous timeout function call. 3787 ** 3788 ** FORMAL PARAMETERS: 3789 ** 3790 ** ftn - function of timeout to cancel 3791 ** sc - sc of timeout to cancel 3792 ** arg - arg of timeout to cancel 3793 ** 3794 ** IMPLICIT INPUTS: 3795 ** 3796 ** nill 3797 ** 3798 ** IMPLICIT OUTPUTS: 3799 ** 3800 ** nill 3801 ** 3802 ** FUNCTION VALUE: 3803 ** 3804 ** nill 3805 ** 3806 ** SIDE EFFECTS: 3807 ** 3808 ** nill 3809 **-- 3810 */ 3811 static void scrUntimeout(ftn, sc, arg) 3812 void (*ftn) __P((struct scr_softc*,int)); 3813 struct scr_softc* sc; 3814 int arg; 3815 { 3816 register Callout *p, *t; 3817 ASSERT(scrClkEnable); 3818 3819 for (p = &scrClkCallTodo; (t = p->c_next) != NULL; p = t) 3820 { 3821 if (t->c_func == ftn && t->c_sc == sc && t->c_arg == arg) 3822 { 3823 /* Increment next entry's count. */ 3824 if (t->c_next && t->c_time > 0) 3825 { 3826 t->c_next->c_time += t->c_time; 3827 } 3828 3829 /* Move entry from fcallout queue to scrClkCallFree queue. */ 3830 p->c_next = t->c_next; 3831 t->c_next = scrClkCallFree; 3832 scrClkCallFree = t; 3833 break; 3834 } 3835 } 3836 } 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 /******************* routines used only during debugging */ 3853 #ifdef SCR_DEBUG 3854 3855 /* 3856 **++ 3857 ** FUNCTIONAL DESCRIPTION: 3858 ** 3859 ** invalidStateCmd 3860 ** 3861 ** Debugging function. Printout information about problem 3862 ** and then kick in the debugger or panic 3863 ** 3864 ** FORMAL PARAMETERS: 3865 ** 3866 ** sc - pointer to soft c 3867 ** state - state of machine 3868 ** cmd - command of machine 3869 ** line - line that problem was detected 3870 ** 3871 ** 3872 ** IMPLICIT INPUTS: 3873 ** 3874 ** nill 3875 ** 3876 ** IMPLICIT OUTPUTS: 3877 ** 3878 ** nill 3879 ** 3880 ** FUNCTION VALUE: 3881 ** 3882 ** nill 3883 ** 3884 ** SIDE EFFECTS: 3885 ** 3886 ** nill 3887 **-- 3888 */ 3889 void invalidStateCmd (struct scr_softc* sc,int state,int cmd,int line) 3890 { 3891 printf("INVALID_STATE_CMD: sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,line); 3892 DEBUGGER; 3893 } 3894 3895 /* 3896 **++ 3897 ** FUNCTIONAL DESCRIPTION: 3898 ** 3899 ** getText 3900 ** 3901 ** Get text representation of state or command 3902 ** 3903 ** FORMAL PARAMETERS: 3904 ** 3905 ** x - state or command 3906 ** 3907 ** IMPLICIT INPUTS: 3908 ** 3909 ** nill 3910 ** 3911 ** IMPLICIT OUTPUTS: 3912 ** 3913 ** nill 3914 ** 3915 ** FUNCTION VALUE: 3916 ** 3917 ** nill 3918 ** 3919 ** SIDE EFFECTS: 3920 ** 3921 ** nill 3922 **-- 3923 */ 3924 char * getText(int x) 3925 { 3926 switch (x) 3927 { 3928 /* commands to Master State Machine (mc = Master Command )*/ 3929 case mcOn: return "mcOn"; 3930 case mcT0DataSend: return "mcT0DataSend"; 3931 case mcT0DataRecv: return "mcT0DataRecv"; 3932 case mcColdReset: return "mcColdReset"; 3933 case mcATR: return "mcATR"; 3934 case mcT0Send: return "mcT0Send"; 3935 case mcT0Recv: return "mcT0Recv"; 3936 3937 /* states in Master state machine (ms = Master State) */ 3938 case msIdleOff: return "msIdleOff"; 3939 case msColdReset: return "msColdReset"; 3940 case msATR: return "msATR"; 3941 case msIdleOn: return "msIdleOn"; 3942 case msT0Send: return "msT0Send"; 3943 case msT0Recv: return "msT0Recv"; 3944 3945 3946 3947 /* commands to T0 send state machine */ 3948 case t0scStart: return "t0scStart"; 3949 case t0scTWorkWaiting: return "t0scTWorkWaiting"; 3950 3951 3952 /* states in T0 send state machine */ 3953 case t0ssIdle: return "t0ssIdle"; 3954 case t0ssSendHeader: return "t0ssSendHeader"; 3955 case t0ssRecvProcedure: return "t0ssRecvProcedu"; 3956 case t0ssSendByte: return "t0ssSendByte"; 3957 case t0ssSendData: return "t0ssSendData"; 3958 case t0ssRecvSW1: return "t0ssRecvSW1"; 3959 case t0ssRecvSW2: return "t0ssRecvSW2"; 3960 3961 3962 /* commands to T0 recv state machine */ 3963 case t0rcStart: return "t0rcStart"; 3964 case t0rcTWorkWaiting: return "t0rcTWorkWaiting"; 3965 3966 /* states in T0 recv state machine */ 3967 case t0rsIdle: return "t0rsIdle"; 3968 case t0rsSendHeader: return "t0rsSendHeader"; 3969 case t0rsRecvProcedure: return "t0rsRecvProcedure"; 3970 case t0rsRecvByte: return "t0rsRecvByte"; 3971 case t0rsRecvData: return "t0rsRecvData"; 3972 case t0rsRecvSW1: return "t0rsRecvSW1"; 3973 case t0rsRecvSW2: return "t0rsRecvSW2"; 3974 3975 3976 3977 3978 3979 /* commands to Answer To Reset (ATR) state machine */ 3980 case atrcStart: return "atrcStart"; 3981 case atrcT3: return "0x0b04"; 3982 case atrcTWorkWaiting: return "atrcTWorkWaiting"; 3983 3984 3985 /* states in in Anser To Reset (ATR) state machine */ 3986 case atrsIdle: return "atrsIdle"; 3987 case atrsTS: return "atrsTS"; 3988 case atrsT0: return "atrsT0"; 3989 case atrsTABCD: return "atrsTABCD"; 3990 case atrsTK: return "atrsTK"; 3991 case atrsTCK: return "atrsTCK"; 3992 3993 3994 3995 /* commands to T0 Recv Byte state machine */ 3996 case t0rbcStart: return "t0rbcStart"; 3997 case t0rbcAbort: return "t0rbcAbort"; 3998 3999 case t0rbcTFindStartEdge:return "t0rbcTFindStartEdge"; 4000 case t0rbcTFindStartMid: return "t0rbcTFindStartMid"; 4001 case t0rbcTClockData: return "t0rbcTClockData"; 4002 case t0rbcTErrorStart: return "t0rbcTErrorStart"; 4003 case t0rbcTErrorStop: return "t0rbcTErrorStop"; 4004 4005 /* states in in TO Recv Byte state machine */ 4006 case t0rbsIdle: return "t0rbsIdle"; 4007 case t0rbsFindStartEdge: return "t0rbcFindStartEdge"; 4008 case t0rbsFindStartMid: return "t0rbcFindStartMid"; 4009 case t0rbsClockData: return "t0rbcClockData"; 4010 case t0rbsSendError: return "t0rbcSendError"; 4011 4012 4013 /* commands to T0 Send Byte state machine */ 4014 case t0sbcStart: return "t0sbcStart"; 4015 case t0sbcAbort: return "t0sbcAbort"; 4016 case t0sbcTGuardTime: return "t0sbcTGuardTime"; 4017 case t0sbcTClockData: return "t0sbcTClockData"; 4018 case t0sbcTError: return "t0sbcTError"; 4019 case t0sbcTResend: return "t0sbcTResend"; 4020 4021 /* states in in T0 Send Byte state machine */ 4022 case t0sbsIdle: return "t0sbsIdle"; 4023 case t0sbsClockData: return "t0sbsClockData"; 4024 case t0sbsWaitError: return "t0sbsWaitError"; 4025 case t0sbsWaitResend: return "t0sbsWaitResend"; 4026 case t0sbsWaitGuardTime: return "t0sbsWaitGuardTime"; 4027 4028 4029 case gcT0RecvByte: return "gcT0RecvByte"; 4030 case gcT0RecvByteErr: return "gcT0RecvByteErr"; 4031 case gcT0SendByte: return "gcT0SendByte"; 4032 case gcT0SendByteErr: return "gcT0SendByteErr"; 4033 4034 4035 case crcStart: return "crcStart"; 4036 case crcT2: return "crcT2"; 4037 4038 4039 default: 4040 printf("unknown case, %x\n",x); 4041 break; 4042 } 4043 return "???"; 4044 } 4045 4046 #endif /* SCR_DEBUG */ 4047 4048 4049 4050