1 /* $NetBSD: scr.c,v 1.24 2009/03/14 14:46:07 dsl Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** 39 ** FACILITY: 40 ** 41 ** Driver for smart card 42 ** 43 ** ABSTRACT: 44 ** 45 ** The driver provides access to a Smart Card for the DNARD. 46 ** 47 ** There is no Smart Card silicon. Several i/o pins 48 ** connect to the pads on the Smart Card, and the driver is 49 ** is responsible for driving the signals in accordance with 50 ** ISO 7816-3 (the Smart Card spec) 51 ** 52 ** This driver puts a high load on the system due to the need 53 ** to interrupt at a high rate (up to 50 kHz) during bit detection. 54 ** 55 ** 56 ** The driver is dived into the standard top half ioctl, and bottom 57 ** half interrupt. The interrupt is FIQ, which requires its own stack. 58 ** disable_interrupts and restore_interrupts must be used to protect from 59 ** a FIQ. Since splxxx functions do not use this, the bottom half cannot 60 ** use any standard functions (ie like wakeup, timeout, etc. 61 ** Thus the communication from the bottom half 62 ** to the top half uses a "done" bit called masterDone. This bit 63 ** is set by the master state machine when all bottom half work is 64 ** complete. The top half checks/sleeps on this masterDone bit. 65 ** 66 ** The FIQ is driven by Timer 2 (T2)in the sequoia. All times are 67 ** referenced to T2 counts. 68 ** 69 ** The bottom half is done as a several linked state machines. 70 ** The top level machine is the maserSM (ie master State Machine). This 71 ** machine calls mid level protocol machines, ie ATRSM (Answer To Reset 72 ** State Machine), t0SendSM (T=0 Send State Machine), and t0RecvSM (T=0 Recv 73 ** State Machine). These mid level protocol machines in turn call low level 74 ** bit-bashing machines, ie coldResetSM, t0SendByteSM, T0RecvByteSM. 75 ** 76 ** Smart Cards are driven in a command/response mode. Ie you issue a command 77 ** to the Smart Card and it responds. This command/response mode is reflected 78 ** in the structure of the driver. Ie the ioctl gets a command, it 79 ** gives it to the bottom half to execute and goes to sleep. The bottom half 80 ** executes the command and gets the response to from the card and then 81 ** notifies the top half that it has completed. Commands usually complete 82 ** in under a second. 83 ** 84 ** 85 ** 86 ** AUTHORS: 87 ** 88 ** E. J. Grohn 89 ** Digital Equipment Corporation. 90 ** 91 ** CREATION DATE: 92 ** 93 ** 27-July-97 94 ** 95 **-- 96 */ 97 98 /* 99 ** 100 ** INCLUDE FILES 101 ** 102 */ 103 104 #include <sys/cdefs.h> 105 __KERNEL_RCSID(0, "$NetBSD: scr.c,v 1.24 2009/03/14 14:46:07 dsl Exp $"); 106 107 #include "opt_ddb.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/ioctl.h> 112 /* #include <sys/select.h> */ 113 /* #include <sys/tty.h> */ 114 #include <sys/proc.h> 115 /* #include <sys/user.h> */ 116 #include <sys/conf.h> 117 /* #include <sys/file.h> */ 118 /* #include <sys/uio.h> */ 119 #include <sys/kernel.h> 120 /* #include <sys/syslog.h> */ 121 #include <sys/types.h> 122 #include <sys/device.h> 123 #include <dev/isa/isavar.h> 124 #include <arm/cpufunc.h> 125 126 127 /* SCR_DEBUG is the master switch for turning on debugging */ 128 //#define SCR_DEBUG 1 129 #ifdef SCR_DEBUG 130 #define KERNEL_DEBUG 131 #ifdef DDB 132 #define DEBUGGER printf("file = %s, line = %d\n",__FILE__,__LINE__);Debugger() 133 #else 134 #define DEBUGGER panic("file = %s, line = %d",__FILE__,__LINE__); 135 #endif 136 #else 137 #define DEBUGGER 138 #endif 139 140 141 #include <machine/kerndebug.h> 142 //#include <machine/intr.h> 143 #include <dev/ic/i8253reg.h> 144 #include <shark/shark/hat.h> 145 #include <shark/shark/sequoia.h> 146 #include <machine/scrio.h> 147 148 149 150 151 /* 152 ** 153 ** MACRO DEFINITIONS 154 ** 155 */ 156 157 158 #define scr_lcr scr_cfcr 159 160 /* 161 ** Macro to extract the minor device number from the device Identifier 162 */ 163 #define SCRUNIT(x) (minor(x)) 164 165 /* 166 ** some macros to assist in debugging 167 */ 168 #ifdef SCR_DEBUG 169 #define KERNEL_DEBUG 170 #define ASSERT(f) do { if (!(f)) { DEBUGGER;} }while(0) 171 #define TOGGLE_TEST_PIN() scrToggleTestPin() 172 #define INVALID_STATE_CMD(sc,state,cmd) invalidStateCmd(sc,state,cmd,__LINE__); 173 #else 174 #define ASSERT(f) 175 #define TOGGLE_TEST_PIN() 176 //#define INVALID_STATE_CMD(sc,state,cmd) panic("scr: invalid state/cmd, sc = %X, state = %X, cmd = %X, line = %d",sc,state,cmd,__LINE__); 177 #define INVALID_STATE_CMD(sc,state,cmd) sc->bigTrouble = true; 178 179 #endif 180 181 182 /* 183 ** The first and last bytes of the debug control variables is reserved for 184 ** the standard KERN_DEBUG_xxx macros, so we can tailor the middle two bytes 185 */ 186 #define SCRPROBE_DEBUG_INFO 0x00000100 187 #define SCRATTACH_DEBUG_INFO 0x00000200 188 #define SCROPEN_DEBUG_INFO 0x00000400 189 #define SCRCLOSE_DEBUG_INFO 0x00000800 190 #define SCRREAD_DEBUG_INFO 0x00001000 191 #define SCRWRITE_DEBUG_INFO 0x00002000 192 #define SCRIOCTL_DEBUG_INFO 0x00004000 193 #define MASTER_SM_DEBUG_INFO 0x00008000 194 #define COLD_RESET_SM_DEBUG_INFO 0x00010000 195 #define ATR_SM_DEBUG_INFO 0x00020000 196 #define T0_RECV_BYTE_SM_DEBUG_INFO 0x00040000 197 #define T0_SEND_BYTE_SM_DEBUG_INFO 0x00080000 198 #define T0_RECV_SM_DEBUG_INFO 0x00100000 199 #define T0_SEND_SM_DEBUG_INFO 0x00200000 200 201 202 int scrdebug = //SCRPROBE_DEBUG_INFO | 203 //SCRATTACH_DEBUG_INFO | 204 //SCROPEN_DEBUG_INFO | 205 //SCRCLOSE_DEBUG_INFO | 206 //SCRREAD_DEBUG_INFO | 207 //SCRWRITE_DEBUG_INFO | 208 //SCRIOCTL_DEBUG_INFO | 209 //MASTER_SM_DEBUG_INFO | 210 //COLD_RESET_SM_DEBUG_INFO| 211 //ATR_SM_DEBUG_INFO | 212 //T0_RECV_BYTE_SM_DEBUG_INFO | 213 //T0_SEND_BYTE_SM_DEBUG_INFO | 214 //T0_RECV_SM_DEBUG_INFO | 215 //T0_SEND_SM_DEBUG_INFO | 216 0; 217 218 219 220 221 222 223 /* 224 ** the bottom half of the driver is done as several linked state machines 225 ** below are all the states of the machines, and the commands that are 226 ** sent to each machine 227 */ 228 229 /* commands to Master State Machine from ioctl */ 230 #define mcOn 0x0100 /* ioctl on */ 231 #define mcT0DataSend 0x0102 /* ioctl send */ 232 #define mcT0DataRecv 0x0103 /* ioctl recv */ 233 234 /* commands to Master State Machine from lower state machines */ 235 #define mcColdReset 0x0105 /* cold reset finished */ 236 #define mcATR 0x0106 /* ATR has finished */ 237 #define mcT0Send 0x0108 /* T0 send finished */ 238 #define mcT0Recv 0x010a /* T0 recv finished */ 239 240 /* states in Master state machine (ms = Master State) */ 241 #define msIdleOff 0x0200 /* in idle state, card powered off */ 242 #define msColdReset 0x0201 /* turning on power, clock, reset */ 243 #define msATR 0x0202 /* getting ATR sequence from card */ 244 #define msIdleOn 0x0203 /* idle, put card powered on */ 245 #define msT0Send 0x0204 /* sending T0 data */ 246 #define msT0Recv 0x0205 /* recving T0 data */ 247 248 249 250 251 /* commands to T0 send state machine */ 252 #define t0scStart 0x0300 /* start */ 253 #define t0scTWorkWaiting 0x0301 /* work waiting timeout */ 254 255 /* states in T0 send state machine */ 256 #define t0ssIdle 0x0400 /* idle state */ 257 #define t0ssSendHeader 0x0401 /* send 5 header bytes */ 258 #define t0ssRecvProcedure 0x0402 /* wait for procedure byte */ 259 #define t0ssSendByte 0x0403 /* send 1 byte */ 260 #define t0ssSendData 0x0404 /* send all bytes */ 261 #define t0ssRecvSW1 0x0405 /* wait for sw1 */ 262 #define t0ssRecvSW2 0x0406 /* wait for sw2 */ 263 264 265 266 267 268 /* commands to T0 recv state machine */ 269 #define t0rcStart 0x0500 /* start */ 270 #define t0rcTWorkWaiting 0x0501 /* work waiting timeout */ 271 272 /* states in T0 recv state machine */ 273 #define t0rsIdle 0x0600 /* idle state */ 274 #define t0rsSendHeader 0x0601 /* send 5 header bytes */ 275 #define t0rsRecvProcedure 0x0602 /* wait for procedure byte */ 276 #define t0rsRecvByte 0x0603 /* recv 1 byte */ 277 #define t0rsRecvData 0x0604 /* recv all bytes */ 278 #define t0rsRecvSW1 0x0605 /* wait for sw1 */ 279 #define t0rsRecvSW2 0x0606 /* wait for sw2 */ 280 281 282 283 /* commands to Cold Reset state machine */ 284 #define crcStart 0x0900 /* start */ 285 #define crcT2 0x0902 /* timeout T2 ISO 7816-3, P6, Figure 2 */ 286 287 /* states in cold reset state machine */ 288 #define crsIdle 0x0a00 /* idle */ 289 #define crsT2Wait 0x0a01 /* wait for T2 ISO 7816-3.P6. Figure 2 */ 290 291 292 293 294 295 /* commands to Answer To Reset (ATR) state machine */ 296 #define atrcStart 0x0b00 /* start */ 297 #define atrcT3 0x0b04 /* got T3 timeout */ 298 #define atrcTWorkWaiting 0x0b05 /* work waiting timeout */ 299 300 /* states in Answer To Reset (ATR) state machine */ 301 #define atrsIdle 0x0c00 /* idle */ 302 #define atrsTS 0x0c01 /* looking for TS, (initial bytes) */ 303 #define atrsT0 0x0c02 /* looking for T0, (format bytes) */ 304 #define atrsTABCD 0x0c03 /* looking for TAx (interface bytes)*/ 305 #define atrsTK 0x0c04 /* looking for TK (history bytes) */ 306 #define atrsTCK 0x0c05 /* looking for TCK (check bytes */ 307 308 309 /* commands to T0 Recv Byte state machine */ 310 #define t0rbcStart 0x0d00 /* start */ 311 #define t0rbcAbort 0x0d01 /* abort */ 312 #define t0rbcTFindStartEdge 0x0d02 /* start bit edge search */ 313 #define t0rbcTFindStartMid 0x0d03 /* start bit mid search */ 314 #define t0rbcTClockData 0x0d04 /* data bit search */ 315 #define t0rbcTErrorStart 0x0d05 /* start to send error */ 316 #define t0rbcTErrorStop 0x0d06 /* stop sending error */ 317 318 /* states in T0 Recv Byte state machine */ 319 #define t0rbsIdle 0x0e00 /* idle */ 320 #define t0rbsFindStartEdge 0x0e01 /* looking for start bit */ 321 #define t0rbsFindStartMid 0x0e02 /* looking for start bit */ 322 #define t0rbsClockData 0x0e03 /* looking for data bits */ 323 #define t0rbsSendError 0x0e04 /* output error bit */ 324 325 326 327 328 /* commands to T0 Send Byte state machine */ 329 #define t0sbcStart 0x0f00 /* start the machine */ 330 #define t0sbcAbort 0x0f01 /* abort the machine */ 331 #define t0sbcTGuardTime 0x0f02 /* guard time finished */ 332 #define t0sbcTClockData 0x0f03 /* clock time finished */ 333 #define t0sbcTError 0x0f04 /* start to send error */ 334 #define t0sbcTResend 0x0f05 /* if parity error, then wait unfill we can re-send */ 335 336 337 338 /* states in T0 Send Byte state machine */ 339 #define t0sbsIdle 0x1000 /* idle */ 340 #define t0sbsWaitGuardTime 0x1001 /* wait for guard time to finish */ 341 #define t0sbsClockData 0x1002 /* clocking out data & parity */ 342 #define t0sbsWaitError 0x1003 /* waiting for error indicator */ 343 #define t0sbsWaitResend 0x1004 /* waiting to start re-send if error */ 344 345 346 347 348 /* 349 ** generic middle level state machine commands 350 ** sent by T0 Send Byte & T0 recv Byte to T0 Send and T0 Recv 351 */ 352 #define gcT0RecvByte 0x1100 /* receive finished */ 353 #define gcT0RecvByteErr 0x1101 /* receive got error */ 354 #define gcT0SendByte 0x1102 /* send finished */ 355 #define gcT0SendByteErr 0x1103 /* send got error */ 356 357 358 359 360 361 362 /* 363 ** 364 ** below are definitions associated with Smart Card 365 ** 366 */ 367 368 369 /* 370 ** Frequency of clock sent to card 371 ** NCI's card is running at 1/2 freq, so in debug we can make 372 ** use of this to toggle more debug signals and still be within 373 ** interrupt time budget 374 */ 375 #ifdef SCR_DEBUG 376 #define CARD_FREQ_DEF (3579000/2) 377 #else 378 #define CARD_FREQ_DEF (3579000) 379 #endif 380 381 382 383 /* byte logic level and msb/lsb coding */ 384 #define CONVENTION_UNKNOWN 0 385 #define CONVENTION_INVERSE 1 386 #define CONVENTION_DIRECT 2 387 #define CONVENIONT_INVERSE_ID 0x3f 388 #define CONVENTION_DIRECT_FIX 0x3b 389 #define CONVENTION_DIRECT_ID 0x23 390 391 392 /* macros that help us set the T2 count for bit bashing */ 393 #define CLK_COUNT_START (((372 * TIMER_FREQ) / sc->cardFreq) /5) 394 #define CLK_COUNT_DATA (((372 * TIMER_FREQ) / sc->cardFreq) ) 395 #define START_2_DATA 5 396 397 /* default settings to use if not specified in ATR */ 398 #define N_DEFAULT 0 /* guard time default */ 399 #define Fi_DEFAULT 372 /* clock rate conversion default */ 400 #define Di_DEFAULT 1 /* bit rate adjustment factor */ 401 #define Wi_DEFAULT 10 /* waiting time */ 402 403 404 /* table for clock rate adjustment in ATR */ 405 int FI2Fi[16] = {372, 372, 558, 744,1116,1488,1860, 0, 406 0, 512, 768,1024,1536,2048, 0, 0}; 407 408 /* table for bit rate adjustment in ATR*/ 409 int DI2Di[16] = { 0, 1, 2, 4, 8, 16, 32, 0, 410 12, 20, 0, 0, 0, 0, 0, 0}; 411 412 /* values of atrY in the ATR sequence*/ 413 #define ATR_Y_TA 0x10 414 #define ATR_Y_TB 0x20 415 #define ATR_Y_TC 0x40 416 #define ATR_Y_TD 0x80 417 418 /* T0,T1,etc information in ATR sequence*/ 419 #define PROTOCOL_T0 0x0001 /* bit 0 for T0 */ 420 #define PROTOCOL_T1 0x0002 /* bit 1 for T1 */ 421 #define PROTOCOL_T2 0x0004 /* bit 2 for T2*/ 422 #define PROTOCOL_T3 0x0008 /* bit 3 for T3*/ 423 /* etc */ 424 425 426 /* timeouts for various places - see ISO 7816-3 */ 427 #define T_t2 ((300 * TIMER_FREQ) / sc->cardFreq) 428 #define T_t3 ((40000 * (TIMER_FREQ/1024)) / (sc->cardFreq/1024)) 429 #define T_WORK_WAITING (((960 * sc->Wi * sc->Fi ) / (sc->cardFreq/1024)) * (TIMER_FREQ/1024)) 430 #define PARITY_ERROR_MAX 3 /* maximum parity errors on 1 byte before giving up */ 431 432 /* 433 ** its possible for the HAT to wedge. If that happens, all timing is sick, so 434 ** we use timeout below (driven of system sleeps) as a "watchdog" 435 */ 436 #define MAX_FIQ_TIME 5 /* maximum time we are willing to run the FIQ */ 437 438 439 /* used to decode T0 commands */ 440 #define CMD_BUF_INS_OFF 1 /* offset to INS in header */ 441 #define CMD_BUF_DATA_LEN_OFF 4 /* offset to data length in header */ 442 443 444 /* 445 ** 446 ** DATA STRUCTURES 447 ** 448 */ 449 typedef unsigned char BYTE; 450 451 /* our soft c structure */ 452 struct scr_softc 453 { 454 struct device dev; 455 int open; 456 457 /* configuration information */ 458 int status; /* status to be returned */ 459 int cardFreq; /* freq supplied to card */ 460 int convention; /* ie direct or inverse */ 461 int protocolType; /* bit 0 indicates T0, bit 1 indicates T1,etc */ 462 int N; /* guard time */ 463 int Fi; /* clock rate */ 464 int Di; /* bit rate adjustment */ 465 int Wi; /* work waiting time */ 466 int clkCountStartRecv; /* count for clock start bits on recv */ 467 int clkCountDataRecv; /* count for clock data bits on recv*/ 468 int clkCountDataSend; /* count for clock data bits on send */ 469 470 /* state machines */ 471 int masterS ; 472 int t0RecvS; 473 int t0SendS; 474 int coldResetS; 475 int ATRS; 476 int t0RecvByteS; 477 int t0SendByteS; 478 479 /* extra stuff kept for t0send state machine */ 480 int commandCount; /* number of command bytes sent */ 481 int dataCount; /* number of data bytes send/recv */ 482 int dataMax; /* max number of data bytes to send/recv */ 483 484 /* extra stuff kept for t0RecvByteS, t0SendByteS machines */ 485 void (*t0ByteParent)(struct scr_softc *,int); /* state machine that is controlling this SM */ 486 int shiftBits; /* number of bits shifted */ 487 BYTE shiftByte; /* intermediate value of bit being shifted */ 488 BYTE dataByte; /* actual value of byte */ 489 int shiftParity; /* value of parity */ 490 int shiftParityCount; /* number of retries due to parity error */ 491 492 /* extra stuff kept for ATR machine */ 493 int atrY; /* indicates if TA,TB,TC,TD is to follow */ 494 int atrK; /* number of historical characters*/ 495 int atrKCount; /* progressive could of historical characters*/ 496 int atrTABCDx; /* the 'i' in TA(i), TB(i), TC(i) and TD(i) */ 497 int atrFi; /* value of Fi */ 498 int atrDi; /* value of Di */ 499 500 int masterDone; /* flag used by bottom half to tell top half its done */ 501 int bigTrouble; /* david/jim, remove this when the dust settles */ 502 503 /* pointers used by ioctl */ 504 ScrOn * pIoctlOn; /* pointer to on ioctl data */ 505 ScrT0 * pIoctlT0; /* pointer to T0 ioctl data */ 506 }; 507 508 /* number of devices */ 509 static int devices = 0; 510 511 /* used as reference for tsleep */ 512 static int tsleepIdent; 513 514 515 /* 516 ** only 1 device is using the hat at any one time 517 ** variable below must be acquired using splhigh before using the hat 518 */ 519 static int hatLock = false; 520 521 522 523 524 /* 525 ** data structures associated with our timeout queue that we run for the 526 ** bottom half of the driver 527 */ 528 529 /* timeout callout structure */ 530 typedef struct callout_t 531 { 532 struct callout_t *c_next; /* next callout in queue */ 533 struct scr_softc *c_sc; /* soft c */ 534 int c_arg; /* function argument */ 535 void (*c_func)(struct scr_softc*,int); /* function to call */ 536 int c_time; /* ticks to the event */ 537 }Callout; 538 539 /* actual callout array */ 540 #define SCR_CLK_CALLOUT_COUNT 10 541 static Callout scrClkCalloutArray[SCR_CLK_CALLOUT_COUNT]; 542 543 /* callout lists */ 544 static Callout *scrClkCallFree; /* free queue */ 545 static Callout scrClkCallTodo; /* todo queue */ 546 547 /* 548 ** information kept for the clock/FIQ that drives our timeout queue 549 */ 550 static int scrClkEnable = 0; /* true if clock enabled */ 551 static void myHatWedge(int nFIQs); /* callback that informs us if FIQ has wedged */ 552 static int scrClkCount; /* number used to set t2 that drives FIQ */ 553 554 #define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ 555 static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used during a FIQ */ 556 557 558 559 560 561 562 563 564 565 566 567 568 /* 569 ** 570 ** FUNCTIONAL PROTOTYPES 571 ** 572 */ 573 574 /* 575 ** 576 ** functions in top half of driver 577 ** 578 */ 579 580 /* configure routines */ 581 int scrprobe(struct device *, struct cfdata *, void *); 582 void scrattach(struct device *, struct device *, void *); 583 584 static void initStates(struct scr_softc * sc); 585 586 587 588 589 /* 590 ** 591 ** functions in bottom half of driver 592 ** 593 */ 594 595 /* top level state machine */ 596 static void masterSM(struct scr_softc * sc,int cmd); 597 598 /* mid level state machines, ie protocols */ 599 static void t0SendSM(struct scr_softc * sc,int cnd); 600 static void t0RecvSM(struct scr_softc * sc,int cnd); 601 static void ATRSM(struct scr_softc * sc,int cnd); 602 603 /* low level state machines, ie bash hardware bits */ 604 static void coldResetSM(struct scr_softc * sc,int cnd); 605 606 static void t0SendByteSM(struct scr_softc * sc,int cnd); 607 static void t0RecvByteSM(struct scr_softc * sc,int cnd); 608 609 static void cardOff(struct scr_softc * sc); 610 611 /* 612 ** functions used for our own timeout routines. 613 ** we cannot use system ones as we are running at a spl level 614 ** that can interrupt the system timeout routines 615 */ 616 static void scrClkInit(void); 617 static void scrClkStart(struct scr_softc* sc,int countPerTick); 618 static void scrClkAdj(int count); 619 static void scrClkStop(void); 620 static void hatClkIrq(int count); 621 622 static void scrTimeout(void (*func)(struct scr_softc*,int), struct scr_softc*, int arg, int count); 623 static void scrUntimeout(void (*func)(struct scr_softc*,int), struct scr_softc*, int arg); 624 625 626 /* debug functions */ 627 #ifdef SCR_DEBUG 628 static void invalidStateCmd(struct scr_softc* sc,int state,int cmd, int line); 629 static char * getText(int x); 630 #endif 631 632 633 634 635 636 CFATTACH_DECL(scr, sizeof(struct scr_softc), 637 scrprobe, scrattach, NULL, NULL); 638 639 extern struct cfdriver scr_cd; 640 641 dev_type_open(scropen); 642 dev_type_close(scrclose); 643 dev_type_ioctl(scrioctl); 644 645 const struct cdevsw scr_cdevsw = { 646 scropen, scrclose, noread, nowrite, scrioctl, 647 nostop, notty, nopoll, nommap, nokqfilter, D_TTY 648 }; 649 650 /* 651 **++ 652 ** FUNCTIONAL DESCRIPTION: 653 ** 654 ** scrProbe 655 ** 656 ** This is the probe routine for the Smart Card. Because the 657 ** Smart Card is hard wired, there is no probing to peform. The 658 ** function ensures that a succesfull problem occurs only once. 659 ** 660 ** FORMAL PARAMETERS: 661 ** 662 ** parent - input : pointer to the parent device 663 ** match - not used 664 ** aux - output : pointer to an isa_attach_args structure. 665 ** 666 ** IMPLICIT INPUTS: 667 ** 668 ** none. 669 ** 670 ** IMPLICIT OUTPUTS: 671 ** 672 ** none. 673 ** 674 ** FUNCTION VALUE: 675 ** 676 ** 0 - Probe failed to find the requested device. 677 ** 1 - Probe successfully talked to the device. 678 ** 679 ** SIDE EFFECTS: 680 ** 681 ** none. 682 **-- 683 */ 684 int scrprobe(parent, match, aux) 685 struct device *parent; 686 struct cfdata *match; 687 void *aux; 688 { 689 struct isa_attach_args *ia = aux; 690 int rv = 0; 691 692 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: called, name = %s\n", 693 device_cfdata(parent)->cf_name)); 694 695 if (device_is_a(parent, "ofisascr") && devices == 0) 696 { 697 /* set "devices" to ensure that we respond only once */ 698 devices++; 699 700 /* tell the caller that we are not using any resource */ 701 ia->ia_nio = 0; 702 ia->ia_niomem = 0; 703 ia->ia_nirq = 0; 704 ia->ia_ndrq = 0; 705 rv = 1; 706 707 708 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: successful \n")); 709 710 } 711 712 713 return (rv); 714 715 } /* End scrprobe() */ 716 717 718 /* 719 **++ 720 ** FUNCTIONAL DESCRIPTION: 721 ** 722 ** scrattach 723 ** 724 ** Initialize the clock and state machines 725 ** 726 ** FORMAL PARAMETERS: 727 ** 728 ** parent - input : pointer to my parents device structure. 729 ** self - output : pointer to my softc with device structure at front. 730 ** aux - input : pointer to the isa_attach_args structure. 731 ** 732 ** IMPLICIT INPUTS: 733 ** 734 ** nill 735 ** 736 ** IMPLICIT OUTPUTS: 737 ** 738 ** scrconsinit - clock callout functions set 739 ** state machines all at idle 740 ** 741 ** FUNCTION VALUE: 742 ** 743 ** none. 744 ** 745 ** SIDE EFFECTS: 746 ** 747 ** none. 748 **-- 749 */ 750 void scrattach(parent, self, aux) 751 struct device *parent; 752 struct device *self; 753 void *aux; 754 { 755 struct scr_softc *sc = (void *)self; 756 757 printf("\n"); 758 if (device_is_a(parent, "ofisascr")) 759 { 760 KERN_DEBUG (scrdebug, SCRATTACH_DEBUG_INFO,("scrattach: called \n")); 761 762 /* set initial state machine values */ 763 scrClkInit(); 764 initStates(sc); 765 sc->open = false; 766 } 767 768 else 769 { 770 panic("scrattach: not on an ISA bus, attach impossible"); 771 } /* End else we aren't on ISA and we can't handle it */ 772 773 774 return; 775 } /* End scrattach() */ 776 777 778 /* 779 **++ 780 ** FUNCTIONAL DESCRIPTION: 781 ** 782 ** initStates 783 ** 784 ** sets the state of all machines to idle 785 ** 786 ** FORMAL PARAMETERS: 787 ** 788 ** sc - Pointer to the softc structure. 789 ** 790 ** IMPLICIT INPUTS: 791 ** 792 ** nill 793 ** 794 ** IMPLICIT OUTPUTS: 795 ** 796 ** nill 797 ** 798 ** FUNCTION VALUE: 799 ** 800 ** nill 801 ** 802 ** SIDE EFFECTS: 803 ** 804 ** nill 805 **-- 806 */ 807 static void initStates(struct scr_softc * sc) 808 { 809 sc->masterS = msIdleOff; 810 sc->t0RecvS = t0rsIdle; 811 sc->t0SendS = t0ssIdle; 812 sc->coldResetS = crsIdle; 813 sc->ATRS = atrsIdle; 814 sc->t0RecvByteS = t0rbsIdle; 815 sc->t0SendByteS = t0sbsIdle; 816 } 817 818 819 820 /* 821 **++ 822 ** FUNCTIONAL DESCRIPTION: 823 ** 824 ** scrOpen 825 ** 826 ** Opens the driver. We only let the device be opened 827 ** once for security reasons 828 ** 829 ** FORMAL PARAMETERS: 830 ** 831 ** dev - input : Device identifier consisting of major and minor numbers. 832 ** flag - input : Indicates if this is a blocking I/O call. 833 ** mode - not used. 834 ** l - input : Pointer to the lwp structure of the light weight process 835 ** performing the open. 836 ** 837 ** IMPLICIT INPUTS: 838 ** 839 ** none. 840 ** 841 ** IMPLICIT OUTPUTS: 842 ** 843 ** none. 844 ** 845 ** FUNCTION VALUE: 846 ** 847 ** ENXIO - invalid device specified for open. 848 ** EBUSY - The unit is already open 849 ** 850 ** SIDE EFFECTS: 851 ** 852 ** none. 853 **-- 854 */ 855 int scropen(dev_t dev, int flag, int mode, struct lwp *l) 856 { 857 struct scr_softc *sc; 858 859 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO, 860 ("scropen: called with minor device %d and flag 0x%x\n", 861 SCRUNIT(dev), flag)); 862 863 sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 864 if (!sc) 865 { 866 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 867 return (ENXIO); 868 } 869 870 871 // david,jim - remove ifdef this when NCI can cope with only 1 open 872 #if 0 873 if (sc->open) 874 { 875 876 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return EBUSY\n")); 877 return (EBUSY); 878 } 879 880 881 /* set all initial conditions */ 882 sc->open = true; 883 #endif 884 885 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("scropen: success \n")); 886 /* Now invoke the line discipline open routine 887 */ 888 889 return 0; 890 891 } /* End scropen() */ 892 893 894 /* 895 **++ 896 ** FUNCTIONAL DESCRIPTION: 897 ** 898 ** This function closed the driver 899 ** 900 ** FORMAL PARAMETERS: 901 ** 902 ** dev - input : Device identifier consisting of major and minor numbers. 903 ** flag - Not used. 904 ** mode - Not used. 905 ** p - Not used. 906 ** 907 ** IMPLICIT INPUTS: 908 ** 909 ** scr_cd - used to locate the softc structure for the device unit 910 ** identified by dev. 911 ** 912 ** IMPLICIT OUTPUTS: 913 ** 914 ** The device is put into an idle state. 915 ** 916 ** FUNCTION VALUE: 917 ** 918 ** 0 - Always returns success. 919 ** 920 ** SIDE EFFECTS: 921 ** 922 ** none. 923 **-- 924 */ 925 int scrclose(dev_t dev, int flag, int mode, struct lwp *l) 926 { 927 #if 0 928 struct scr_softc *sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 929 #endif 930 931 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO, 932 ("scrclose: called for minor device %d flag 0x%x\n", 933 SCRUNIT(dev), flag)); 934 935 // david,jim - remove ifdef this when NCI can cope with only 1 open 936 #if 0 937 /* Check we are open in the first place 938 */ 939 if (sc->open) 940 { 941 /* put everything in the idle state */ 942 scrClkInit(); 943 initStates(sc); 944 sc->open = false; 945 946 } 947 948 949 else 950 { 951 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("\t scrclose, device not open\n")); 952 } 953 #endif 954 955 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("scrclose exiting\n")); 956 return(0); 957 } 958 959 /* 960 **++ 961 ** FUNCTIONAL DESCRIPTION: 962 ** 963 ** This routine is responsible for performing I/O controls. 964 ** 965 ** There are 4 commands. Status, On, T0 and Off. 966 ** 967 ** Status checks to see if the card is inserted. This command 968 ** does not use the state machines 969 ** 970 ** On turns the card on and gets the ATR sequence from the card. 971 ** This command does use the state machines 972 ** 973 ** T0 is used to read and write the card. This command does use 974 ** the state machines 975 ** 976 ** Off turns the card off. This command does not use the state 977 ** machines. 978 ** 979 ** 980 ** FORMAL PARAMETERS: 981 ** 982 ** dev - input : Device identifier consisting of major and minor numbers. 983 ** cmd - input : The requested IOCTL command to be performed. 984 ** See scrio.h for details 985 ** 986 ** 987 ** Bit Position { 3322222222221111111111 988 ** { 10987654321098765432109876543210 989 ** Meaning | DDDLLLLLLLLLLLLLGGGGGGGGCCCCCCCC 990 ** 991 ** D - Command direction, in/out/both. 992 ** L - Command argument length. 993 ** G - Command group, 't' used for tty. 994 ** C - Actual command enumeration. 995 ** 996 ** data - input/output : Direction depends on the command. 997 ** flag - input : Not used by us but passed to line discipline and ttioctl 998 ** l - input : pointer to lwp structure of user. 999 ** 1000 ** IMPLICIT INPUTS: 1001 ** 1002 ** none. 1003 ** 1004 ** IMPLICIT OUTPUTS: 1005 ** 1006 ** sc->masterS state of master state machine 1007 ** 1008 ** 1009 ** FUNCTION VALUE: 1010 ** 1011 ** ENOTTY if not correct ioctl 1012 ** 1013 ** 1014 ** SIDE EFFECTS: 1015 ** 1016 **-- 1017 */ 1018 int 1019 scrioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1020 { 1021 struct scr_softc* sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 1022 1023 int error = 0; /* error value returned */ 1024 int masterDoneRetries= 0; /* nuber of times we looked at masterDone */ 1025 int done; /* local copy of masterDone */ 1026 1027 ScrStatus * pIoctlStatus; /* pointer to status ioctl */ 1028 ScrOff * pIoctlOff; /* pointer to off ioctl */ 1029 1030 u_int savedInts; /* saved interrupts */ 1031 int s; /* saved spl value */ 1032 1033 1034 1035 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1036 ("scrioctl: called for device 0x%x, command 0x%lx, " 1037 "flag 0x%x\n", 1038 SCRUNIT(dev), cmd, flag)); 1039 1040 1041 1042 switch (cmd) 1043 { 1044 /* 1045 ** get the status of the card, ie is it in, in but off, in and on 1046 */ 1047 case SCRIOSTATUS: 1048 pIoctlStatus = (ScrStatus*)data; 1049 if (scrGetDetect()) 1050 { 1051 savedInts = disable_interrupts(I32_bit | F32_bit); 1052 if (sc->masterS == msIdleOn) 1053 { 1054 pIoctlStatus->status = CARD_ON; 1055 } 1056 else 1057 { 1058 ASSERT(sc->masterS == msIdleOff); 1059 pIoctlStatus->status = CARD_INSERTED; 1060 } 1061 restore_interrupts(savedInts); 1062 } 1063 1064 else 1065 { 1066 pIoctlStatus->status = CARD_REMOVED; 1067 } 1068 break; 1069 1070 1071 1072 /* 1073 ** turn the card on and get the ATR sequence 1074 */ 1075 case SCRIOON: 1076 sc->pIoctlOn = (ScrOn*)data; 1077 // acquire the hat lock. 1078 while (1) 1079 { 1080 s = splhigh(); 1081 if(!hatLock) 1082 { 1083 hatLock = true; 1084 splx(s); 1085 break; 1086 } 1087 splx(s); 1088 1089 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1090 } 1091 1092 1093 // check to see if the card is in 1094 if(!scrGetDetect()) 1095 { 1096 initStates(sc); 1097 cardOff(sc); 1098 // do not call scrClkInit() as it is idle already 1099 sc->pIoctlOn->status = ERROR_CARD_REMOVED; 1100 } 1101 1102 1103 // check to see if we are already on 1104 else if(sc->masterS == msIdleOn) 1105 { 1106 sc->pIoctlOn->status = ERROR_CARD_ON; 1107 } 1108 1109 // card was in, card is off, so lets start it 1110 else 1111 { 1112 // set up the top half 1113 sc->masterDone = false; 1114 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1115 1116 1117 1118 // start bottom half 1119 scrClkStart (sc,400); 1120 savedInts = disable_interrupts(I32_bit | F32_bit); 1121 masterSM(sc,mcOn); 1122 restore_interrupts(savedInts); 1123 1124 1125 1126 // see if bottom half done 1127 while (1) 1128 { 1129 // check that we have not looped too many times 1130 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1131 { 1132 //printf("MAX_FIQ_TIME reached \n"); 1133 // big problems, so reset bottom 1134 savedInts = disable_interrupts(I32_bit | F32_bit); 1135 scrClkInit(); 1136 initStates(sc); 1137 cardOff(sc); 1138 sc->status = ERROR_CARD_REMOVED; 1139 sc->masterDone = true; 1140 restore_interrupts(savedInts); 1141 // dont stop clock, done at bottom of case 1142 } 1143 masterDoneRetries++; 1144 1145 // get done bit 1146 savedInts = disable_interrupts(I32_bit | F32_bit); 1147 done = sc->masterDone; 1148 restore_interrupts(savedInts); 1149 1150 // see if all done 1151 if(done) 1152 { 1153 break; 1154 } 1155 1156 1157 // wait for a while 1158 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1159 } 1160 1161 1162 // stop bottom half 1163 scrClkStop(); 1164 1165 1166 /* need to fix up count bits in non hat interrupt time, so */ 1167 if (sc->status == ERROR_OK) 1168 { 1169 sc->clkCountStartRecv = CLK_COUNT_START; 1170 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1171 sc->clkCountDataSend = CLK_COUNT_DATA; 1172 } 1173 1174 1175 1176 /* takes while to turn off all lines, so keep out of hat */ 1177 if (sc->masterS != msIdleOn) 1178 { 1179 cardOff(sc); 1180 } 1181 // get the status back from the state machine 1182 sc->pIoctlOn->status = sc->status; 1183 1184 1185 } 1186 1187 1188 // release the hat lock. 1189 s = splhigh(); 1190 ASSERT(hatlock); 1191 hatLock = false; 1192 splx(s); 1193 1194 // david,jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1195 if (sc->pIoctlOn->status != ERROR_OK) 1196 { 1197 sc->pIoctlOn->atrLen = 0; 1198 } 1199 break; 1200 1201 1202 /* 1203 ** turn the card off 1204 */ 1205 case SCRIOOFF: 1206 pIoctlOff = (ScrOff*)data; 1207 // card off does not requires any state processing, so do work here 1208 initStates(sc); 1209 cardOff(sc); 1210 // do not call scrClkInit() as it is idle already 1211 pIoctlOff->status = ERROR_OK; 1212 break; 1213 1214 1215 /* 1216 ** do a T0 read or write 1217 */ 1218 case SCRIOT0: 1219 sc->pIoctlT0 = (ScrT0*)data; 1220 1221 // acquire the hat lock. 1222 while (1) 1223 { 1224 s = splhigh(); 1225 if(!hatLock) 1226 { 1227 hatLock = true; 1228 splx(s); 1229 break; 1230 } 1231 splx(s); 1232 1233 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1234 } 1235 1236 // check to see if the card is in 1237 if(!scrGetDetect()) 1238 { 1239 initStates(sc); 1240 cardOff(sc); 1241 // do not call scrClkInit() as it is idle already 1242 sc->pIoctlT0->status = ERROR_CARD_REMOVED; 1243 } 1244 1245 1246 // check to see if card is off 1247 else if(sc->masterS == msIdleOff) 1248 { 1249 sc->pIoctlT0->status = ERROR_CARD_OFF; 1250 } 1251 1252 // card was in, card is on, lets do command 1253 else 1254 1255 { 1256 // set up the top half 1257 sc->masterDone = false; 1258 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1259 1260 // start bottom half 1261 scrClkStart (sc,sc->clkCountDataSend); 1262 savedInts = disable_interrupts(I32_bit | F32_bit); 1263 if (sc->pIoctlT0->writeBuffer) 1264 { 1265 masterSM(sc,mcT0DataSend); 1266 } 1267 else 1268 { 1269 masterSM(sc,mcT0DataRecv); 1270 } 1271 restore_interrupts(savedInts); 1272 1273 1274 // see if bottom half done 1275 while (1) 1276 { 1277 // check that we have not looped too many times 1278 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1279 { 1280 //printf("MAX_FIQ_TIME reached \n"); 1281 // big problems, so reset bottom 1282 savedInts = disable_interrupts(I32_bit | F32_bit); 1283 scrClkInit(); 1284 initStates(sc); 1285 cardOff(sc); 1286 sc->status = ERROR_CARD_REMOVED; 1287 sc->masterDone = true; 1288 restore_interrupts(savedInts); 1289 } 1290 masterDoneRetries++; 1291 1292 1293 // get done bit 1294 savedInts = disable_interrupts(I32_bit | F32_bit); 1295 done = sc->masterDone; 1296 restore_interrupts(savedInts); 1297 1298 1299 // see if all done 1300 if(done) 1301 { 1302 break; 1303 } 1304 1305 1306 // wait for a while 1307 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1308 } 1309 1310 // stop bottom half 1311 scrClkStop(); 1312 1313 1314 1315 // get the status back from the state machine 1316 sc->pIoctlT0->status = sc->status; 1317 } 1318 1319 1320 // release the hat lock. 1321 s = splhigh(); 1322 hatLock = false; 1323 splx(s); 1324 1325 1326 1327 // david, jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1328 if (sc->pIoctlT0->status != ERROR_OK) 1329 { 1330 sc->pIoctlT0->dataLen = 0; 1331 } 1332 break; 1333 1334 default: 1335 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO,("\t scrioctl: unknown command, ENOTTY \n")); 1336 error = ENOTTY; 1337 break; 1338 } 1339 1340 1341 1342 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1343 ("scrioctl: exiting with sc->status %d\n", error)); 1344 return (error); 1345 } /* End scrioctl */ 1346 1347 1348 1349 1350 1351 1352 /* 1353 ** 1354 ** All functions below this point are the bottom half of the driver 1355 ** 1356 ** All are called during a FIQ, except for some functions in masterSM which 1357 ** provides the interface between the bottom half and top half of 1358 ** the driver (nb masterDone() helps masterSM() out with this interface 1359 ** between top and bottom parts of the driver. 1360 ** 1361 */ 1362 1363 1364 /* 1365 **++ 1366 ** FUNCTIONAL DESCRIPTION: 1367 ** 1368 ** masterSM 1369 ** 1370 ** This state machine implements the top level state control It 1371 ** receives commands to turn the card on, and do T0 reads and T0 writes 1372 ** from the scrioctl. It then calls mid level state machine to action 1373 ** these commands. 1374 ** 1375 ** This machine is the only machine to keep state between scrioctl calls. 1376 ** Between calls, the state will be either msIdleOff, or msIdleOn. msIdleOff 1377 ** indicates that no signals are applied to the card. msidleOn indicates that 1378 ** power and clock are supplied to the card, and that the card has performed 1379 ** a successful ATR sequence. 1380 ** 1381 ** This routine gets called during FIQ interrupts and from scrioctl. It is a 1382 ** requirement that the scrioctl disables interrupts before calling this function. 1383 ** 1384 ** NB:- there is no way for the machine to get from msIdleOn to msIdleOff. Since 1385 ** this is just a mater of turning all signals off and resetting state machines, 1386 ** scrioctl takes a shortcut and resets everything itself. Ie it hits everything 1387 ** with a big hammer!! 1388 ** 1389 ** FORMAL PARAMETERS: 1390 ** 1391 ** sc - Pointer to the softc structure. 1392 ** cmd - command to the state machine, can be from ioctl, or mid level SM 1393 ** 1394 ** IMPLICIT INPUTS: 1395 ** 1396 ** sc->masterS state of this machine 1397 ** sc->pIoctlT0 pointer to T0 ioctl 1398 ** 1399 ** IMPLICIT OUTPUTS: 1400 ** 1401 ** 1402 ** FUNCTION VALUE: 1403 ** 1404 ** nill 1405 ** 1406 ** SIDE EFFECTS: 1407 ** 1408 ** power and clock applied to card if successful ATR 1409 **-- 1410 */ 1411 static void masterSM(struct scr_softc * sc,int cmd) 1412 { 1413 1414 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1415 1416 switch (sc->masterS) 1417 { 1418 case msIdleOff: 1419 switch (cmd) 1420 { 1421 case mcOn: 1422 if (scrGetDetect()) 1423 { 1424 /* 1425 ** the card is off, and we want it on 1426 */ 1427 1428 /* set initial values */ 1429 sc->status = 0; 1430 sc->convention = CONVENTION_UNKNOWN; 1431 sc->protocolType = 0; 1432 sc->N = N_DEFAULT; 1433 sc->Fi = Fi_DEFAULT; 1434 sc->Di = Di_DEFAULT; 1435 sc->Wi = Wi_DEFAULT; 1436 sc->cardFreq = CARD_FREQ_DEF; 1437 sc->clkCountStartRecv = CLK_COUNT_START; 1438 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1439 sc->clkCountDataSend = CLK_COUNT_DATA; 1440 1441 /* get coldResetSM to turn on power, clock, reset */ 1442 sc->masterS = msColdReset; 1443 coldResetSM(sc,crcStart); 1444 } 1445 else 1446 { 1447 /* card not inserted, so just set status and give up */ 1448 sc->status = ERROR_CARD_REMOVED; 1449 sc->masterDone = true; 1450 } 1451 break; 1452 1453 default: 1454 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1455 break; 1456 } 1457 break; 1458 1459 case msColdReset: 1460 switch (cmd) 1461 { 1462 case mcColdReset: 1463 /* 1464 ** coldResetSM has turned on power, clock , reset 1465 ** tell ATRSM to get the ATR sequence from the card 1466 */ 1467 sc->masterS = msATR; 1468 ATRSM(sc,atrcStart); 1469 break; 1470 1471 default: 1472 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1473 break; 1474 } 1475 break; 1476 1477 case msATR: 1478 switch (cmd) 1479 { 1480 case mcATR: 1481 /* 1482 ** ATRSM has tried to get ATR sequence, so give 1483 ** back results to scrioctl. ATR sequence data 1484 ** was copied directly into ioctl data area, so 1485 ** no need to copy data 1486 */ 1487 if(sc->status == ERROR_OK) 1488 { 1489 sc->masterS = msIdleOn; 1490 } 1491 else 1492 { 1493 sc->masterS = msIdleOff; 1494 } 1495 sc->masterDone = true; 1496 break; 1497 1498 1499 default: 1500 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1501 break; 1502 } 1503 break; 1504 1505 case msIdleOn: 1506 switch (cmd) 1507 { 1508 // nb there is no command to go to the IdleOff state. This 1509 // is a reset of the state machine, so is done in ioctl 1510 1511 case mcT0DataSend: 1512 /* 1513 ** card is on, and we want to T0 Send, so 1514 ** as t0SendSM to do work 1515 */ 1516 sc->status = ERROR_OK; 1517 sc->masterS = msT0Send; 1518 t0SendSM(sc,t0scStart); 1519 break; 1520 1521 case mcT0DataRecv: 1522 /* 1523 ** card is on, and we want to T0 Recv, so 1524 ** as t0RecvSM to do work 1525 */ 1526 sc->status = ERROR_OK; 1527 sc->masterS = msT0Recv; 1528 t0RecvSM(sc,t0rcStart); 1529 break; 1530 1531 default: 1532 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1533 break; 1534 } 1535 1536 break; 1537 1538 case msT0Send: 1539 switch (cmd) 1540 { 1541 case mcT0Send: 1542 /* 1543 ** t0SendSM has tried to send , so lets give back results 1544 */ 1545 sc->masterS = msIdleOn; 1546 sc->masterDone = true; 1547 break; 1548 1549 default: 1550 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1551 break; 1552 } 1553 break; 1554 1555 case msT0Recv: 1556 switch (cmd) 1557 { 1558 case mcT0Recv: 1559 /* 1560 ** t0RecvSM has tried to recv , so lets give back results 1561 ** data was written directly into ioctl data area, so we 1562 ** do not need to copy any data 1563 */ 1564 sc->pIoctlT0->dataLen = sc->dataCount; 1565 sc->masterS = msIdleOn; 1566 sc->masterDone = true; 1567 break; 1568 1569 default: 1570 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1571 break; 1572 } 1573 break; 1574 1575 default: 1576 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1577 break; 1578 1579 } 1580 } 1581 1582 1583 1584 1585 /* 1586 **++ 1587 ** FUNCTIONAL DESCRIPTION: 1588 ** 1589 ** t0SendSM 1590 ** 1591 ** This is the T=0 Send State Machine. It is responsible 1592 ** for performing the send part of the ISO 7816-3 T=0 1593 ** protocol. It is mid level protocol state machine. 1594 ** 1595 ** Once started, this machine is driven entirely via the 1596 ** FIQ/timeout structure . 1597 ** 1598 ** 1599 ** 1600 ** FORMAL PARAMETERS: 1601 ** 1602 ** sc - Pointer to the softc structure. 1603 ** cmd - command to this machine 1604 ** 1605 ** IMPLICIT INPUTS: 1606 ** 1607 ** sc->t0SendS state of this machine 1608 ** sc->pIoctlT0->command command to send to card 1609 ** sc->pIoctlT0->data data to send to card 1610 ** 1611 ** IMPLICIT OUTPUTS: 1612 ** 1613 ** sc->status error status from this machine 1614 ** sc->pIoctlT0->sw1 command status from card 1615 ** sc->pIoctlT0->sw2 command status from card 1616 ** sc->status error status from this machine 1617 ** 1618 ** FUNCTION VALUE: 1619 ** 1620 ** nill 1621 ** 1622 ** SIDE EFFECTS: 1623 ** 1624 ** nill 1625 **-- 1626 */ 1627 static void t0SendSM (struct scr_softc * sc, int cmd) 1628 { 1629 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1630 /* 1631 ** check for major failures that are common to most states 1632 */ 1633 if (cmd == t0scTWorkWaiting || 1634 cmd == gcT0RecvByteErr || 1635 cmd == gcT0SendByteErr 1636 ) 1637 { 1638 switch(cmd) 1639 { 1640 case t0scTWorkWaiting: 1641 ASSERT(sc->t0SendS != t0ssIdle); 1642 1643 /* kill all lower machines */ 1644 t0SendByteSM(sc,t0sbcAbort); 1645 t0RecvByteSM(sc,t0rbcAbort); 1646 1647 /* set status */ 1648 sc->status = ERROR_WORK_WAITING; 1649 break; 1650 1651 case gcT0RecvByteErr: // fall through 1652 case gcT0SendByteErr: 1653 scrUntimeout(t0SendSM, sc, t0scTWorkWaiting); 1654 // done set status, already set in lower machine 1655 break; 1656 1657 default: 1658 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1659 break; 1660 } 1661 1662 /* change states */ 1663 sc->t0SendS = t0ssIdle; 1664 masterSM(sc,mcT0Send); 1665 return; 1666 } 1667 1668 switch (sc->t0SendS) 1669 { 1670 case t0ssIdle: 1671 switch (cmd) 1672 { 1673 case t0scStart: 1674 /* set initial values */ 1675 sc->t0SendS = t0ssSendHeader; 1676 sc->t0ByteParent = t0SendSM; 1677 sc->commandCount = 0; 1678 sc->dataCount = 0; 1679 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1680 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1681 1682 // get a byte 1683 t0SendByteSM(sc,t0sbcStart); 1684 break; 1685 1686 default: 1687 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1688 break; 1689 } 1690 break; 1691 1692 case t0ssSendHeader: 1693 switch (cmd) 1694 { 1695 case gcT0SendByte: 1696 sc->commandCount++; 1697 if (sc->commandCount < CMD_BUF_LEN) 1698 { 1699 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1700 t0SendByteSM(sc,t0sbcStart); 1701 } 1702 else 1703 { 1704 ASSERT(sc->commandCount == CMD_BUF_LEN); 1705 1706 sc->t0SendS = t0ssRecvProcedure; 1707 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1708 t0RecvByteSM(sc,t0rbcStart); 1709 } 1710 break; 1711 1712 default: 1713 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1714 break; 1715 } 1716 break; 1717 1718 case t0ssRecvProcedure: 1719 switch (cmd) 1720 { 1721 case gcT0RecvByte: 1722 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1723 /* see if we should send all remaining bytes */ 1724 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 1725 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 1726 { 1727 ASSERT(sc->dataCount < sc->dataMax); 1728 sc->t0SendS = t0ssSendData; 1729 sc->dataByte = sc->pIoctlT0->data[sc->dataCount]; 1730 t0SendByteSM(sc,t0sbcStart); 1731 sc->dataCount++; 1732 } 1733 1734 /* see if we should send one data byte */ 1735 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 1736 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 1737 { 1738 ASSERT(sc->dataCount < sc->dataMax); 1739 sc->t0SendS = t0ssSendByte; 1740 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1741 t0SendByteSM(sc,t0sbcStart); 1742 sc->dataCount++; 1743 } 1744 1745 /* see if we should extend the work waiting period */ 1746 else if (sc->dataByte == 0x60) 1747 { 1748 t0RecvByteSM(sc,t0rbcStart); 1749 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1750 } 1751 1752 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 1753 /* see if we have a SW1 byte */ 1754 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 1755 && 1756 sc->dataByte != 0x60) 1757 #else /* XXX XXX XXX cgd */ 1758 /* see if we have a SW1 byte */ 1759 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 1760 && 1761 sc->dataByte != 0x60) 1762 #endif /* XXX XXX XXX cgd */ 1763 { 1764 sc->pIoctlT0->sw1 = sc->dataByte; 1765 sc->t0SendS = t0ssRecvSW2; 1766 t0RecvByteSM(sc,t0rbcStart); 1767 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1768 } 1769 1770 /* got bad data byte, log error and get out */ 1771 else 1772 { 1773 sc->status = ERROR_BAD_PROCEDURE_BYTE; 1774 1775 /* change state */ 1776 sc->t0SendS = t0ssIdle; 1777 masterSM(sc,mcT0Send); 1778 } 1779 break; 1780 1781 default: 1782 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1783 break; 1784 } 1785 break; 1786 1787 case t0ssSendByte: 1788 switch (cmd) 1789 { 1790 case gcT0SendByte: 1791 if (sc->dataCount < sc->dataMax) 1792 { 1793 sc->t0SendS = t0ssRecvProcedure; 1794 } 1795 1796 /* wait for sw1 byte */ 1797 else 1798 { 1799 ASSERT(sc->dataCount == sc->dataMax); 1800 sc->t0SendS = t0ssRecvSW1; 1801 } 1802 1803 // ask for another byte 1804 t0RecvByteSM(sc,t0rbcStart); 1805 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1806 break; 1807 1808 default: 1809 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1810 break; 1811 } 1812 break; 1813 1814 case t0ssSendData: 1815 switch (cmd) 1816 { 1817 case gcT0SendByte: 1818 /* send data */ 1819 if (sc->dataCount < sc->dataMax) 1820 { 1821 sc->t0SendS = t0ssSendData; 1822 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1823 t0SendByteSM(sc,t0sbcStart); 1824 sc->dataCount++; 1825 } 1826 1827 /* wait for sw1 byte */ 1828 else 1829 { 1830 ASSERT(sc->dataCount == sc->dataMax); 1831 sc->t0SendS = t0ssRecvSW1; 1832 t0RecvByteSM(sc,t0rbcStart); 1833 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1834 } 1835 break; 1836 1837 default: 1838 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1839 break; 1840 } 1841 break; 1842 1843 case t0ssRecvSW1: 1844 switch (cmd) 1845 { 1846 case gcT0RecvByte: 1847 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1848 sc->pIoctlT0->sw1 = sc->dataByte; 1849 sc->t0SendS = t0ssRecvSW2; 1850 t0RecvByteSM(sc,t0rbcStart); 1851 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1852 break; 1853 default: 1854 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1855 break; 1856 } 1857 break; 1858 1859 case t0ssRecvSW2: 1860 switch (cmd) 1861 { 1862 case gcT0RecvByte: 1863 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1864 sc->pIoctlT0->sw2 = sc->dataByte; 1865 sc->t0SendS = t0ssIdle; 1866 masterSM(sc,mcT0Send); 1867 break; 1868 1869 default: 1870 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1871 break; 1872 } 1873 break; 1874 1875 default: 1876 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1877 break; 1878 } 1879 } 1880 1881 1882 1883 /* 1884 **++ 1885 ** FUNCTIONAL DESCRIPTION: 1886 ** 1887 ** t0RecvSM 1888 ** 1889 ** This is the T=0 Recv State Machine. It is responsible 1890 ** for performing the recv part of the ISO 7816-3 T=0 1891 ** protocol. It is mid level protocol state machine. 1892 ** 1893 ** Once started, this machine is driven entirely via the 1894 ** FIQ/timeout structure . 1895 ** 1896 ** FORMAL PARAMETERS: 1897 ** 1898 ** sc - Pointer to the softc structure. 1899 ** cmd - command to this machine 1900 ** 1901 ** IMPLICIT INPUTS: 1902 ** 1903 ** sc->t0RecvS state of this machine 1904 ** sc->pIoctlT0->command command to send to card 1905 ** 1906 ** IMPLICIT OUTPUTS: 1907 ** 1908 ** sc->pIoctlT0->data data from card 1909 ** sc->pIoctlT0->dataLen size of data from card 1910 ** sc->pIoctlT0->sw1 command status from card 1911 ** sc->pIoctlT0->sw2 command status from card 1912 ** sc->status error status from this machine 1913 ** 1914 ** FUNCTION VALUE: 1915 ** 1916 ** nill 1917 ** 1918 ** SIDE EFFECTS: 1919 ** 1920 ** nill 1921 **-- 1922 */ 1923 static void t0RecvSM (struct scr_softc * sc,int cmd) 1924 { 1925 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1926 1927 /* 1928 ** check for major failures that are common to most states 1929 */ 1930 if (cmd == t0rcTWorkWaiting || 1931 cmd == gcT0RecvByteErr || 1932 cmd == gcT0SendByteErr ) 1933 1934 { 1935 switch(cmd) 1936 { 1937 1938 case t0rcTWorkWaiting: 1939 ASSERT(sc->t0RecvS != t0rsIdle); 1940 1941 /* kill all lower level machines */ 1942 t0SendByteSM(sc,t0sbcAbort); 1943 t0RecvByteSM(sc,t0rbcAbort); 1944 1945 /* set status */ 1946 sc->status = ERROR_WORK_WAITING; 1947 break; 1948 1949 case gcT0RecvByteErr: // fall through 1950 case gcT0SendByteErr: 1951 /* kill all the timers */ 1952 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 1953 break; 1954 1955 default: 1956 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1957 break; 1958 1959 } 1960 1961 1962 1963 /* change state */ 1964 sc->t0RecvS = t0rsIdle; 1965 masterSM(sc,mcT0Recv); 1966 1967 /* all done */ 1968 return; 1969 } 1970 1971 switch (sc->t0RecvS) 1972 { 1973 case t0rsIdle: 1974 switch (cmd) 1975 { 1976 case t0rcStart: 1977 /* set initial values */ 1978 sc->t0RecvS = t0rsSendHeader; 1979 sc->t0ByteParent = t0RecvSM; 1980 sc->commandCount = 0; 1981 sc->dataCount = 0; 1982 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1983 if (sc->dataMax == 0) 1984 { 1985 sc->dataMax = 256; 1986 } 1987 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1988 t0SendByteSM(sc,t0sbcStart); 1989 break; 1990 1991 default: 1992 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1993 break; 1994 } 1995 break; 1996 1997 case t0rsSendHeader: 1998 switch (cmd) 1999 { 2000 case gcT0SendByte: 2001 sc->commandCount++; 2002 if (sc->commandCount < CMD_BUF_LEN) 2003 { 2004 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2005 t0SendByteSM(sc,t0sbcStart); 2006 } 2007 else 2008 { 2009 ASSERT(sc->commandCount == CMD_BUF_LEN); 2010 2011 sc->t0RecvS = t0rsRecvProcedure; 2012 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2013 t0RecvByteSM(sc,t0rbcStart); 2014 } 2015 break; 2016 2017 default: 2018 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2019 break; 2020 } 2021 break; 2022 2023 case t0rsRecvProcedure: 2024 switch (cmd) 2025 { 2026 case gcT0RecvByte: 2027 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2028 2029 /* see if we should recv all remaining bytes */ 2030 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 2031 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 2032 { 2033 ASSERT(sc->dataCount < sc->dataMax); 2034 2035 sc->t0RecvS = t0rsRecvData; 2036 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2037 t0RecvByteSM(sc,t0rbcStart); 2038 } 2039 2040 /* see if we should send one data byte */ 2041 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 2042 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 2043 { 2044 ASSERT(sc->dataCount < sc->dataMax); 2045 sc->t0RecvS = t0rsRecvByte; 2046 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2047 t0RecvByteSM(sc,t0rbcStart); 2048 } 2049 2050 /* see if we should extend the work waiting period */ 2051 else if (sc->dataByte == 0x60) 2052 { 2053 t0RecvByteSM(sc,t0rbcStart); 2054 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2055 } 2056 2057 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 2058 /* see if we have a SW1 byte */ 2059 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 2060 && 2061 sc->dataByte != 0x60) 2062 #else /* XXX XXX XXX cgd */ 2063 /* see if we have a SW1 byte */ 2064 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 2065 && 2066 sc->dataByte != 0x60) 2067 #endif /* XXX XXX XXX cgd */ 2068 { 2069 sc->pIoctlT0->sw1 = sc->dataByte; 2070 sc->t0RecvS = t0rsRecvSW2; 2071 t0RecvByteSM(sc,t0rbcStart); 2072 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2073 } 2074 2075 /* got bad data byte, log error and get out */ 2076 else 2077 { 2078 sc->status = ERROR_BAD_PROCEDURE_BYTE; 2079 2080 /* change state */ 2081 sc->t0RecvS = t0rsIdle; 2082 masterSM(sc,mcT0Recv); 2083 } 2084 break; 2085 2086 default: 2087 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2088 break; 2089 } 2090 break; 2091 2092 case t0rsRecvByte: 2093 switch (cmd) 2094 { 2095 case gcT0RecvByte: 2096 /* clock in byte */ 2097 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2098 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2099 sc->dataCount++; 2100 2101 2102 if (sc->dataCount < sc->dataMax) 2103 { 2104 /* get procedure byte */ 2105 sc->t0RecvS = t0rsRecvProcedure; 2106 } 2107 2108 else 2109 { 2110 ASSERT(sc->dataCount == sc->dataMax); 2111 sc->t0RecvS = t0rsRecvSW1; 2112 } 2113 2114 // ask for another byte 2115 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2116 t0RecvByteSM(sc,t0rbcStart); 2117 break; 2118 2119 default: 2120 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2121 break; 2122 } 2123 break; 2124 2125 case t0rsRecvData: 2126 switch (cmd) 2127 { 2128 case gcT0RecvByte: 2129 /* clock in data */ 2130 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2131 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2132 sc->dataCount++; 2133 2134 /* decide if we have all data */ 2135 if (sc->dataCount >= sc->dataMax) 2136 { 2137 KERN_DEBUG (scrdebug, T0_RECV_SM_DEBUG_INFO,("\t\tt0RecvSM: changing state to t0rsRecvSW1\n")); 2138 ASSERT(sc->dataCount == sc->dataMax); 2139 sc->t0RecvS = t0rsRecvSW1; 2140 } 2141 2142 /* ask for another byte */ 2143 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2144 t0RecvByteSM(sc,t0rbcStart); 2145 break; 2146 2147 default: 2148 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2149 break; 2150 } 2151 break; 2152 2153 case t0rsRecvSW1: 2154 switch (cmd) 2155 { 2156 case gcT0RecvByte: 2157 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2158 sc->pIoctlT0->sw1 = sc->dataByte; 2159 2160 sc->t0RecvS = t0rsRecvSW2; 2161 t0RecvByteSM(sc,t0rbcStart); 2162 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2163 break; 2164 default: 2165 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2166 break; 2167 } 2168 break; 2169 2170 case t0rsRecvSW2: 2171 switch (cmd) 2172 { 2173 case gcT0RecvByte: 2174 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2175 sc->pIoctlT0->sw2 = sc->dataByte; 2176 2177 sc->t0RecvS = t0rsIdle; 2178 masterSM(sc,mcT0Recv); 2179 break; 2180 2181 default: 2182 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2183 break; 2184 } 2185 break; 2186 2187 default: 2188 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2189 break; 2190 } 2191 } 2192 2193 2194 /* 2195 **++ 2196 ** FUNCTIONAL DESCRIPTION: 2197 ** 2198 ** coldResetSM 2199 ** 2200 ** This state machine switches on the power, clock and reset pins 2201 ** in the correct order/timing. 2202 ** It is a low level bit-bashing state machine. 2203 ** 2204 ** 2205 ** FORMAL PARAMETERS: 2206 ** 2207 ** sc - Pointer to the softc structure. 2208 ** cmd - command to this machine 2209 ** 2210 ** IMPLICIT INPUTS: 2211 ** 2212 ** sc->coldResetS state of this machine 2213 ** 2214 ** IMPLICIT OUTPUTS: 2215 ** 2216 ** nill 2217 ** 2218 ** FUNCTION VALUE: 2219 ** 2220 ** nill 2221 ** 2222 ** SIDE EFFECTS: 2223 ** 2224 ** signals to card are on 2225 **-- 2226 */ 2227 static void coldResetSM(struct scr_softc * sc,int cmd) 2228 { 2229 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2230 2231 switch (sc->coldResetS) 2232 { 2233 case crsIdle: 2234 switch (cmd) 2235 { 2236 case crcStart: 2237 scrSetReset(true); 2238 scrSetClock(true); 2239 scrSetDataHighZ(); 2240 scrSetPower(true); 2241 2242 /* start a t2 timer */ 2243 scrTimeout(coldResetSM,sc,crcT2,T_t2); 2244 sc->coldResetS = crsT2Wait; 2245 break; 2246 2247 default: 2248 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2249 break; 2250 } 2251 break; 2252 2253 case crsT2Wait: 2254 switch (cmd) 2255 { 2256 case crcT2: 2257 /* turn off rst */ 2258 scrSetReset(false); 2259 2260 /* tell master state machine that we are all done */ 2261 sc->coldResetS = crsIdle; 2262 masterSM(sc,mcColdReset); 2263 break; 2264 2265 default: 2266 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2267 break; 2268 } 2269 break; 2270 2271 2272 default: 2273 INVALID_STATE_CMD(sc,sc->coldResetS,cmd); 2274 break; 2275 } 2276 } 2277 2278 /* 2279 **++ 2280 ** FUNCTIONAL DESCRIPTION: 2281 ** 2282 ** ATRSM 2283 ** 2284 ** This is the Answer To Reset State Machine. It is responsible 2285 ** for performing the Answer To Reset as specified in ISO 7816-3. 2286 ** It is mid level protocol state machine. 2287 ** 2288 ** Once started, this machine is driven entirely via the 2289 ** FIQ/timeout structure. 2290 ** 2291 ** 2292 ** During the first byte, we have to check if the card is operating 2293 ** at full speed or half speed. The first couple of bits are 2294 ** checked to see if it is 1/2 speed, and if so, the clock is changed 2295 ** and the state adjustes 2296 ** 2297 ** At the end of the first byte we have to determin the logic being 2298 ** used by the card, ie is it active high/low and msb/lsb. 2299 ** 2300 ** 2301 ** FORMAL PARAMETERS: 2302 ** 2303 ** sc - Pointer to the softc structure. 2304 ** cmd - command to this machine 2305 ** 2306 ** IMPLICIT INPUTS: 2307 ** 2308 ** sc->pIoctlAtr->atr data from card 2309 ** sc->pIoctlT0->sw1 command status from card 2310 ** sc->pIoctlT0->sw2 command status from card 2311 ** sc->status error status from this machine 2312 ** 2313 ** IMPLICIT OUTPUTS: 2314 ** 2315 ** sc->pIoctlOn->atrBuf data from ATR sequence 2316 ** sc->pIoctlOn->atrLen size of data from ATR sequence 2317 ** sc->status error status from this machine 2318 ** 2319 ** 2320 ** FUNCTION VALUE: 2321 ** 2322 ** nill 2323 ** 2324 ** SIDE EFFECTS: 2325 ** 2326 ** nill 2327 **-- 2328 */ 2329 static void ATRSM (struct scr_softc * sc,int cmd) 2330 { 2331 int lc; 2332 int tck; 2333 2334 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2335 2336 /* 2337 ** check for major failures that are common to most states 2338 */ 2339 if (cmd == atrcT3 || 2340 cmd == atrcTWorkWaiting || 2341 cmd == gcT0RecvByteErr 2342 ) 2343 { 2344 switch(cmd) 2345 { 2346 case atrcT3: 2347 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2348 sc->status = ERROR_ATR_T3; 2349 t0RecvByteSM(sc,t0rbcAbort); 2350 break; 2351 2352 case atrcTWorkWaiting: 2353 scrUntimeout (ATRSM,sc,atrcT3); 2354 sc->status = ERROR_WORK_WAITING; 2355 t0RecvByteSM(sc,t0rbcAbort); 2356 break; 2357 2358 case gcT0RecvByteErr: 2359 scrUntimeout (ATRSM,sc,atrcT3); 2360 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2361 /* done set status, its already set */ 2362 break; 2363 2364 default: 2365 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2366 break; 2367 } 2368 2369 /* change state */ 2370 sc->ATRS = atrsIdle; 2371 masterSM(sc,mcATR); 2372 return; 2373 } 2374 2375 switch (sc->ATRS) 2376 { 2377 case atrsIdle: 2378 switch (cmd) 2379 { 2380 case atrcStart: 2381 /* lets start looking */ 2382 sc->ATRS = atrsTS; 2383 sc->pIoctlOn->atrLen = 0; 2384 sc->t0ByteParent = ATRSM; 2385 scrTimeout(ATRSM,sc,atrcT3,T_t3 *2); /* by 2 to accommodate 1/2 freq cards */ 2386 t0RecvByteSM(sc,t0rbcStart); 2387 break; 2388 2389 default: 2390 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2391 break; 2392 } 2393 break; 2394 2395 case atrsTS: 2396 switch (cmd) 2397 { 2398 case gcT0RecvByte: 2399 scrUntimeout(ATRSM,sc,atrcT3); 2400 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2401 sc->pIoctlOn->atrLen++; 2402 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2403 { 2404 #ifdef SCR_DEBUG 2405 DEBUGGER; 2406 #endif 2407 sc->status = ERROR_ATR_TCK; 2408 sc->ATRS = atrsIdle; 2409 masterSM(sc,mcATR); 2410 } 2411 else 2412 { 2413 /* move onto recv T0 */ 2414 sc->ATRS = atrsT0; 2415 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2416 t0RecvByteSM(sc,t0rbcStart); 2417 } 2418 break; 2419 2420 default: 2421 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2422 break; 2423 } 2424 break; 2425 2426 case atrsT0: 2427 switch (cmd) 2428 { 2429 case gcT0RecvByte: 2430 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2431 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2432 sc->pIoctlOn->atrLen++; 2433 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2434 { 2435 #ifdef SCR_DEBUG 2436 printf("atrLen >= ATR_BUF_MAX\n"); 2437 DEBUGGER; 2438 #endif 2439 sc->status = ERROR_ATR_TCK; 2440 sc->ATRS = atrsIdle; 2441 masterSM(sc,mcATR); 2442 } 2443 else 2444 { 2445 /* store Y & K */ 2446 sc->atrY = sc->dataByte & 0xf0; 2447 sc->atrK = sc->dataByte & 0x0f; 2448 2449 sc->atrTABCDx = 1; 2450 sc->atrKCount = 1; 2451 2452 /* if there are no TDx following set T0 protocol */ 2453 if (!ISSET(sc->atrY,ATR_Y_TD)) 2454 { 2455 sc->protocolType = PROTOCOL_T0; 2456 } 2457 2458 2459 if (sc->atrY) 2460 { 2461 2462 sc->ATRS = atrsTABCD; 2463 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2464 t0RecvByteSM(sc,t0rbcStart); 2465 } 2466 2467 else if (sc->atrK) 2468 { 2469 sc->ATRS = atrsTK; 2470 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2471 t0RecvByteSM(sc,t0rbcStart); 2472 } 2473 2474 else if (sc->protocolType != PROTOCOL_T0) 2475 { 2476 sc->ATRS = atrsTCK; 2477 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2478 t0RecvByteSM(sc,t0rbcStart); 2479 } 2480 2481 else /* got all of ATR */ 2482 { 2483 sc->ATRS = atrsIdle; 2484 masterSM(sc,mcATR); 2485 } 2486 } 2487 break; 2488 2489 2490 default: 2491 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2492 break; 2493 } 2494 break; 2495 2496 2497 case atrsTABCD: 2498 switch (cmd) 2499 { 2500 case gcT0RecvByte: 2501 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2502 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2503 sc->pIoctlOn->atrLen++; 2504 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2505 { 2506 #ifdef SCR_DEBUG 2507 printf("atrLen >= ATR_BUF_MAX\n"); 2508 DEBUGGER; 2509 #endif 2510 sc->status = ERROR_ATR_TCK; 2511 sc->ATRS = atrsIdle; 2512 masterSM(sc,mcATR); 2513 } 2514 else 2515 { 2516 if (sc->atrY & ATR_Y_TA) 2517 { 2518 sc->atrY &= ~ATR_Y_TA; 2519 if (sc->atrTABCDx == 1) 2520 { 2521 sc->Fi = FI2Fi[((sc->dataByte >> 4) & 0x0f)]; 2522 if (sc->Fi == 0) 2523 { 2524 sc->status = ERROR_ATR_FI_INVALID; 2525 sc->Fi = Fi_DEFAULT; 2526 } 2527 2528 sc->Di = DI2Di[(sc->dataByte & 0x0f)]; 2529 if (sc->Di == 0) 2530 { 2531 sc->status = ERROR_ATR_DI_INVALID; 2532 sc->Di = Di_DEFAULT; 2533 } 2534 2535 } 2536 } 2537 2538 else if (sc->atrY & ATR_Y_TB) 2539 { 2540 sc->atrY &= ~ATR_Y_TB; 2541 } 2542 2543 else if (sc->atrY & ATR_Y_TC) 2544 { 2545 sc->atrY &= ~ATR_Y_TC; 2546 if (sc->atrTABCDx == 1) 2547 { 2548 sc->N = sc->dataByte; 2549 } 2550 2551 if (sc->atrTABCDx == 2) 2552 { 2553 sc->Wi = sc->dataByte; 2554 } 2555 } 2556 2557 else 2558 { 2559 ASSERT(sc->atrY & ATR_Y_TD); 2560 sc->atrY &= ~ATR_Y_TD; 2561 2562 /* copy across the y section of TD */ 2563 sc->atrY = sc->dataByte; 2564 sc->atrY &= 0xf0; 2565 2566 /* step to the next group of TABCD */ 2567 sc->atrTABCDx++; 2568 2569 /* store protocols */ 2570 sc->protocolType = (1 << (sc->dataByte &0x0f)); 2571 } 2572 2573 2574 /* see what we should do next */ 2575 if (sc->atrY) 2576 { 2577 /* just stay in the same state */ 2578 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2579 t0RecvByteSM(sc,t0rbcStart); 2580 } 2581 2582 else if (sc->atrK) 2583 { 2584 sc->ATRS = atrsTK; 2585 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2586 t0RecvByteSM(sc,t0rbcStart); 2587 } 2588 2589 else if (sc->protocolType != PROTOCOL_T0) 2590 { 2591 sc->ATRS = atrsTCK; 2592 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2593 t0RecvByteSM(sc,t0rbcStart); 2594 } 2595 2596 else /* got all of ATR */ 2597 { 2598 sc->ATRS = atrsIdle; 2599 masterSM(sc,mcATR); 2600 } 2601 } 2602 2603 break; 2604 2605 2606 default: 2607 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2608 break; 2609 } 2610 break; 2611 2612 case atrsTK: 2613 switch (cmd) 2614 { 2615 case gcT0RecvByte: 2616 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2617 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2618 sc->pIoctlOn->atrLen++; 2619 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2620 { 2621 #ifdef SCR_DEBUG 2622 printf("atrLen >= ATR_BUF_MAX\n"); 2623 DEBUGGER; 2624 #endif 2625 sc->status = ERROR_ATR_TCK; 2626 sc->ATRS = atrsIdle; 2627 masterSM(sc,mcATR); 2628 } 2629 else 2630 { 2631 2632 if (sc->atrKCount < sc->atrK) 2633 { 2634 sc->atrKCount++; 2635 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2636 t0RecvByteSM(sc,t0rbcStart); 2637 } 2638 2639 2640 else if (sc->protocolType != PROTOCOL_T0) 2641 { 2642 sc->ATRS = atrsTCK; 2643 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2644 t0RecvByteSM(sc,t0rbcStart); 2645 } 2646 2647 else /* got all of ATR */ 2648 { 2649 sc->ATRS = atrsIdle; 2650 masterSM(sc,mcATR); 2651 } 2652 } 2653 break; 2654 2655 default: 2656 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2657 break; 2658 } 2659 break; 2660 2661 case atrsTCK: 2662 switch (cmd) 2663 { 2664 case gcT0RecvByte: 2665 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2666 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2667 sc->pIoctlOn->atrLen++; 2668 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2669 { 2670 #ifdef SCR_DEBUG 2671 printf("atrLen >= ATR_BUF_MAX\n"); 2672 DEBUGGER; 2673 #endif 2674 sc->status = ERROR_ATR_TCK; 2675 sc->ATRS = atrsIdle; 2676 masterSM(sc,mcATR); 2677 } 2678 else 2679 { 2680 tck = 0; 2681 for (lc = 1; lc < sc->pIoctlOn->atrLen-1; lc++) 2682 { 2683 tck ^= sc->pIoctlOn->atrBuf[lc]; 2684 } 2685 2686 if (tck == sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen-1]) 2687 { 2688 sc->ATRS = atrsIdle; 2689 masterSM(sc,mcATR); 2690 } 2691 else 2692 { 2693 sc->status = ERROR_ATR_TCK; 2694 sc->ATRS = atrsIdle; 2695 masterSM(sc,mcATR); 2696 } 2697 } 2698 break; 2699 2700 default: 2701 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2702 break; 2703 } 2704 break; 2705 2706 2707 2708 default: 2709 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2710 break; 2711 } 2712 } 2713 2714 2715 2716 /* 2717 **++ 2718 ** FUNCTIONAL DESCRIPTION: 2719 ** 2720 ** t0RecvByteSM 2721 ** 2722 ** This state machine attempts to read 1 byte from a card. 2723 ** It is a low level bit-bashing state machine. 2724 ** 2725 ** Data from the card is async, so the machine scans at 2726 ** 5 times the data rate looking for a state bit. Once 2727 ** a start bit has been found, it waits for the middle of 2728 ** the bit and starts sampling at the bit rate. 2729 ** 2730 ** Several mid level machines can use this machine, so the value 2731 ** sc->t0ByteParent is used to point to back to the mid level machine 2732 ** 2733 ** 2734 ** FORMAL PARAMETERS: 2735 ** 2736 ** sc - Pointer to the softc structure. 2737 ** cmd - command to this machine 2738 ** 2739 ** IMPLICIT INPUTS: 2740 ** 2741 ** sc->t0RecvByteS state of this machine 2742 ** sc->t0ByteParent mid level machine that started this machine 2743 ** 2744 ** IMPLICIT OUTPUTS: 2745 ** 2746 ** sc->shiftByte byte read from the card 2747 ** sc->status error value if could not read byte 2748 ** 2749 ** FUNCTION VALUE: 2750 ** 2751 ** nill 2752 ** 2753 ** SIDE EFFECTS: 2754 ** 2755 ** nill 2756 **-- 2757 */ 2758 static void t0RecvByteSM(struct scr_softc* sc,int cmd) 2759 { 2760 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2761 2762 if (cmd == t0rbcAbort) 2763 { 2764 /* kill all the timers */ 2765 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartEdge); 2766 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartMid); 2767 scrUntimeout(t0RecvByteSM, sc,t0rbcTClockData); 2768 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStart); 2769 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStop); 2770 2771 scrSetDataHighZ(); 2772 sc->t0RecvByteS = t0rbsIdle; 2773 return; 2774 } 2775 2776 2777 switch (sc->t0RecvByteS) 2778 { 2779 case t0rbsIdle: 2780 switch (cmd) 2781 { 2782 case t0rbcStart: 2783 /* set initial conditions */ 2784 sc->shiftBits = 0; 2785 sc->shiftByte = 0; 2786 sc->shiftParity = 0; 2787 sc->shiftParityCount = 0; 2788 scrClkAdj(sc->clkCountStartRecv); /* recv data clock running at 5 times */ 2789 2790 /* check if start bit is already here */ 2791 //if (scrGetData()) 2792 if (1) 2793 { 2794 /* didn't find it, keep looking */ 2795 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2796 sc->t0RecvByteS = t0rbsFindStartEdge; 2797 } 2798 else 2799 { 2800 /* found start bit, look for mid bit */ 2801 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv); 2802 sc->t0RecvByteS = t0rbsFindStartMid; 2803 } 2804 break; 2805 2806 2807 2808 default: 2809 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2810 break; 2811 } 2812 break; 2813 2814 2815 case t0rbsFindStartEdge: 2816 switch (cmd) 2817 { 2818 case t0rbcTFindStartEdge: 2819 if (scrGetData()) 2820 { 2821 /* didn't find it, keep looking */ 2822 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2823 } 2824 else 2825 { 2826 /* found start bit, look for mid bit */ 2827 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv * 2); 2828 sc->t0RecvByteS = t0rbsFindStartMid; 2829 } 2830 break; 2831 2832 2833 default: 2834 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2835 break; 2836 } 2837 break; 2838 2839 case t0rbsFindStartMid: 2840 switch (cmd) 2841 { 2842 case t0rbcTFindStartMid: 2843 if (scrGetData()) 2844 { 2845 /* found glitch, so just go back to hunting */ 2846 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2847 sc->t0RecvByteS = t0rbsFindStartEdge; 2848 } 2849 else 2850 { 2851 /* found start bit, start clocking in data */ 2852 TOGGLE_TEST_PIN(); 2853 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2854 sc->t0RecvByteS = t0rbsClockData; 2855 } 2856 break; 2857 2858 2859 default: 2860 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2861 break; 2862 } 2863 break; 2864 2865 2866 case t0rbsClockData: 2867 TOGGLE_TEST_PIN(); 2868 switch (cmd) 2869 { 2870 case t0rbcTClockData: 2871 if (sc->shiftBits < 8) 2872 { 2873 if (sc->convention == CONVENTION_INVERSE || 2874 sc->convention == CONVENTION_UNKNOWN) 2875 { 2876 /* logic 1 is low, msb is first */ 2877 sc->shiftByte <<= 1; 2878 sc->shiftByte &= 0xfe; 2879 if (!scrGetData()) 2880 { 2881 sc->shiftByte |= 0x01; 2882 sc->shiftParity++; 2883 } 2884 } 2885 else 2886 { 2887 ASSERT(sc->convention == CONVENTION_DIRECT); 2888 /* logic 1 is high, lsb is first */ 2889 sc->shiftByte = sc->shiftByte >> 1; 2890 sc->shiftByte &= 0x7f; 2891 if (scrGetData()) 2892 { 2893 sc->shiftParity++; 2894 sc->shiftByte |= 0x80; 2895 } 2896 } 2897 sc->shiftBits++; 2898 2899 2900 /* in TS byte, check if we have a card that works at 1/2 freq */ 2901 if (sc->convention == CONVENTION_UNKNOWN && /* in TS byte */ 2902 sc->shiftBits == 3 && /* test at bit 3 in word */ 2903 sc->shiftByte == 4 && /* check for 1/2 freq pattern */ 2904 sc->cardFreq == CARD_FREQ_DEF) /* only do this if at full freq */ 2905 { 2906 /* adjust counts down to 1/2 freq */ 2907 sc->cardFreq = CARD_FREQ_DEF / 2; 2908 sc->clkCountStartRecv = sc->clkCountStartRecv *2; 2909 sc->clkCountDataRecv = sc->clkCountDataRecv *2; 2910 sc->clkCountDataSend = sc->clkCountDataSend *2; 2911 2912 2913 /* adjust this so that we have clocked in only fist bit of TS */ 2914 sc->shiftParity = 0; 2915 sc->shiftByte = 0; 2916 sc->shiftBits = 1; 2917 2918 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,(sc->clkCountDataRecv * 3) /4); 2919 } 2920 else 2921 { 2922 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2923 } 2924 } 2925 2926 /* clock in parity bit */ 2927 else if (sc->shiftBits == 8) 2928 { 2929 if (sc->convention == CONVENTION_INVERSE) 2930 { 2931 if (!scrGetData()) 2932 { 2933 sc->shiftParity++; 2934 } 2935 } 2936 else if (sc->convention == CONVENTION_DIRECT) 2937 { 2938 if (scrGetData()) 2939 { 2940 sc->shiftParity++; 2941 } 2942 } 2943 2944 2945 else 2946 { 2947 /* sc->convention not set so sort it out */ 2948 ASSERT(sc->convention == CONVENTION_UNKNOWN); 2949 if (sc->shiftByte == CONVENIONT_INVERSE_ID && scrGetData()) 2950 { 2951 sc->convention = CONVENTION_INVERSE; 2952 sc->shiftParity = 0; /* force good parity */ 2953 } 2954 2955 else if (sc->shiftByte == CONVENTION_DIRECT_ID && scrGetData()) 2956 { 2957 sc->shiftByte = CONVENTION_DIRECT_FIX; 2958 sc->convention = CONVENTION_DIRECT; 2959 sc->shiftParity = 0; /* force good parity */ 2960 } 2961 2962 else 2963 { 2964 sc->shiftParity = 1; /* force bad parity */ 2965 } 2966 } 2967 2968 2969 if ((sc->shiftParity & 01) == 0) 2970 { 2971 sc->shiftBits++; 2972 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2973 } 2974 else 2975 { 2976 /* got parity error */ 2977 if (sc->shiftParityCount < PARITY_ERROR_MAX) 2978 { 2979 sc->shiftParityCount++; 2980 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStart,sc->clkCountDataRecv); 2981 sc->t0RecvByteS = t0rbsSendError; 2982 } 2983 else 2984 2985 { 2986 /* too many parity errors, just give up on this sc->dataByte */ 2987 sc->status = ERROR_PARITY; 2988 sc->t0RecvByteS = t0rbsIdle; 2989 sc->t0ByteParent(sc,gcT0RecvByteErr); 2990 } 2991 } 2992 } 2993 2994 else 2995 { 2996 sc->dataByte = sc->shiftByte; 2997 sc->t0RecvByteS = t0rbsIdle; 2998 sc->t0ByteParent(sc,gcT0RecvByte); 2999 } 3000 break; 3001 3002 default: 3003 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3004 break; 3005 } 3006 break; 3007 3008 3009 case t0rbsSendError: 3010 TOGGLE_TEST_PIN(); 3011 switch (cmd) 3012 { 3013 case t0rbcTErrorStart: 3014 /* start sending error bit */ 3015 scrSetData(false); 3016 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStop,sc->clkCountDataRecv * 2); 3017 break; 3018 3019 case t0rbcTErrorStop: 3020 /* stop sending parity error & reset information*/ 3021 scrSetData(true); 3022 sc->shiftBits = 0; 3023 sc->shiftByte = 0; 3024 sc->shiftParity = 0; 3025 3026 /* start looking for start bit */ 3027 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,1); 3028 sc->t0RecvByteS = t0rbsFindStartEdge; 3029 break; 3030 3031 default: 3032 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3033 break; 3034 } 3035 break; 3036 3037 3038 default: 3039 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3040 break; 3041 } 3042 } 3043 3044 /* 3045 **++ 3046 ** FUNCTIONAL DESCRIPTION: 3047 ** 3048 ** t0SendByteSM 3049 ** 3050 ** This state machine writes 1 byte to a card. 3051 ** It is a low level bit-bashing state machine. 3052 ** 3053 ** 3054 ** Several mid level machines can use this machine, so the value 3055 ** sc->t0ByteParent is used to point to back to the mid level machine 3056 ** 3057 ** FORMAL PARAMETERS: 3058 ** 3059 ** sc - Pointer to the softc structure. 3060 ** cmd - command to this machine 3061 ** 3062 ** IMPLICIT INPUTS: 3063 ** 3064 ** sc->t0SendByteS state of this machine 3065 ** sc->shiftByte byte to write to the card 3066 ** 3067 ** IMPLICIT OUTPUTS: 3068 ** 3069 ** sc->status error value if could not read byte 3070 ** 3071 ** FUNCTION VALUE: 3072 ** 3073 ** nill 3074 ** 3075 ** SIDE EFFECTS: 3076 ** 3077 ** nill 3078 **-- 3079 */ 3080 //int bigTroubleTest = 0; 3081 static void t0SendByteSM (struct scr_softc * sc,int cmd) 3082 { 3083 //if(bigTroubleTest == 2000) 3084 //{ 3085 // INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3086 // bigTroubleTest = 0; 3087 //} 3088 // 3089 //bigTroubleTest++; 3090 3091 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 3092 3093 if (cmd == t0sbcAbort) 3094 { 3095 /* kill all the timers */ 3096 scrUntimeout(t0SendByteSM, sc, t0sbcTGuardTime); 3097 scrUntimeout(t0SendByteSM, sc, t0sbcTClockData); 3098 scrUntimeout(t0SendByteSM, sc, t0sbcTError); 3099 3100 scrSetDataHighZ(); 3101 return; 3102 } 3103 3104 3105 switch (sc->t0SendByteS) 3106 { 3107 case t0sbsIdle: 3108 switch (cmd) 3109 { 3110 case t0sbcStart: 3111 /* set initial conditions */ 3112 sc->shiftBits = 0; 3113 sc->shiftParity = 0; 3114 sc->shiftParityCount = 0; 3115 sc->shiftByte = sc->dataByte; 3116 3117 scrClkAdj(sc->clkCountDataSend); /* send data clock running at 1 ETU */ 3118 3119 /* check if we have to wait for guard time */ 3120 if (0) /* possible optimization here */ 3121 { 3122 /* can send start bit now */ 3123 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3124 scrSetData(false); 3125 sc->t0SendByteS = t0sbsClockData; 3126 } 3127 else 3128 { 3129 /* need to wait for guard time */ 3130 scrTimeout(t0SendByteSM,sc,t0sbcTGuardTime,sc->clkCountDataSend * (12 + sc->N)); 3131 sc->t0SendByteS = t0sbsWaitGuardTime; 3132 3133 } 3134 break; 3135 3136 default: 3137 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3138 break; 3139 } 3140 break; 3141 3142 3143 case t0sbsWaitGuardTime: 3144 switch (cmd) 3145 { 3146 case t0sbcTGuardTime: 3147 TOGGLE_TEST_PIN(); 3148 /* set start bit */ 3149 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3150 scrSetData(false); 3151 sc->t0SendByteS = t0sbsClockData; 3152 break; 3153 3154 default: 3155 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3156 break; 3157 } 3158 break; 3159 3160 3161 case t0sbsClockData: 3162 switch (cmd) 3163 { 3164 case t0sbcTClockData: 3165 TOGGLE_TEST_PIN(); 3166 /* clock out data bit */ 3167 if (sc->shiftBits < 8) 3168 { 3169 if (sc->convention == CONVENTION_INVERSE) 3170 { 3171 if (sc->shiftByte & 0x80) 3172 { 3173 scrSetData(false); 3174 sc->shiftParity++; 3175 } 3176 else 3177 { 3178 scrSetData(true); 3179 } 3180 sc->shiftByte = sc->shiftByte << 1; 3181 } 3182 else 3183 { 3184 ASSERT(sc->convention == CONVENTION_DIRECT); 3185 if (sc->shiftByte & 0x01) 3186 { 3187 scrSetData(true); 3188 sc->shiftParity++; 3189 } 3190 else 3191 { 3192 scrSetData(false); 3193 } 3194 sc->shiftByte = sc->shiftByte >> 1; 3195 } 3196 sc->shiftBits++; 3197 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3198 } 3199 3200 /* clock out parity bit */ 3201 else if (sc->shiftBits == 8) 3202 { 3203 if ( ((sc->shiftParity & 0x01) && (sc->convention == CONVENTION_INVERSE)) || 3204 (!(sc->shiftParity & 0x01) && (sc->convention == CONVENTION_DIRECT)) ) 3205 { 3206 scrSetData(false); 3207 } 3208 else 3209 { 3210 scrSetData(true); 3211 } 3212 sc->shiftBits++; 3213 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3214 } 3215 3216 /* all data shifted out, move onto next state */ 3217 else 3218 { 3219 ASSERT(sc->shiftBits > 8); 3220 scrSetData(true); 3221 scrTimeout(t0SendByteSM,sc,t0sbcTError,sc->clkCountDataSend); 3222 sc->t0SendByteS = t0sbsWaitError; 3223 } 3224 break; 3225 3226 default: 3227 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3228 break; 3229 } 3230 break; 3231 3232 case t0sbsWaitError: 3233 switch (cmd) 3234 { 3235 case t0sbcTError: 3236 /* no error indicated*/ 3237 if (scrGetData()) 3238 { 3239 sc->t0SendByteS = t0sbsIdle; 3240 sc->t0ByteParent(sc,gcT0SendByte); 3241 } 3242 3243 /* got error */ 3244 else 3245 { 3246 /* got parity error */ 3247 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3248 { 3249 sc->shiftParityCount++; 3250 scrTimeout(t0SendByteSM,sc,t0sbcTResend,sc->clkCountDataSend * 2); 3251 sc->t0SendByteS = t0sbsWaitResend; 3252 } 3253 else 3254 { 3255 /* too many parity errors, just give up on this sc->dataByte */ 3256 sc->status = ERROR_PARITY; 3257 sc->t0SendByteS = t0sbsIdle; 3258 sc->t0ByteParent(sc,gcT0SendByteErr); 3259 } 3260 } 3261 break; 3262 3263 default: 3264 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3265 break; 3266 } 3267 break; 3268 3269 case t0sbsWaitResend: 3270 switch (cmd) 3271 { 3272 case t0sbcTResend: 3273 sc->shiftBits = 0; 3274 sc->shiftParity = 0; 3275 sc->shiftByte = sc->dataByte; 3276 /* set start bit */ 3277 3278 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3279 scrSetData(false); 3280 sc->t0SendByteS = t0sbsClockData; 3281 break; 3282 3283 default: 3284 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3285 break; 3286 } 3287 break; 3288 3289 3290 default: 3291 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3292 break; 3293 } 3294 } 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 /* 3307 **++ 3308 ** FUNCTIONAL DESCRIPTION: 3309 ** 3310 ** cardOff 3311 ** 3312 ** Turn all signals to the card off 3313 ** 3314 ** FORMAL PARAMETERS: 3315 ** 3316 ** sc - Pointer to the softc structure. 3317 ** 3318 ** IMPLICIT INPUTS: 3319 ** 3320 ** nill 3321 ** 3322 ** IMPLICIT OUTPUTS: 3323 ** 3324 ** nill 3325 ** 3326 ** FUNCTION VALUE: 3327 ** 3328 ** nill 3329 ** 3330 ** SIDE EFFECTS: 3331 ** 3332 ** nill 3333 **-- 3334 */ 3335 static void cardOff (struct scr_softc * sc) 3336 { 3337 scrSetReset(true); 3338 scrSetDataHighZ(); 3339 scrSetClock(false); 3340 scrSetPower(false); 3341 } 3342 3343 3344 3345 3346 /* 3347 ** 3348 ** 3349 ** **************** timer routines *************** 3350 ** 3351 */ 3352 3353 /* 3354 **++ 3355 ** FUNCTIONAL DESCRIPTION: 3356 ** 3357 ** scrClkInit 3358 ** 3359 ** Init the callout queues. The callout queues are used 3360 ** by the timeout/untimeout queues 3361 ** 3362 ** FORMAL PARAMETERS: 3363 ** 3364 ** nill 3365 ** 3366 ** IMPLICIT INPUTS: 3367 ** 3368 ** nill 3369 ** 3370 ** IMPLICIT OUTPUTS: 3371 ** 3372 ** nill 3373 ** 3374 ** FUNCTION VALUE: 3375 ** 3376 ** nill 3377 ** 3378 ** SIDE EFFECTS: 3379 ** 3380 ** nill 3381 **-- 3382 */ 3383 static void scrClkInit(void) 3384 { 3385 3386 int lc; 3387 Callout *c; 3388 Callout *new; 3389 3390 scrClkCallTodo.c_next = NULL; 3391 scrClkCallFree = &scrClkCalloutArray[0]; 3392 c = scrClkCallFree; 3393 3394 for (lc = 1; lc < SCR_CLK_CALLOUT_COUNT; lc++) 3395 { 3396 new = &scrClkCalloutArray[lc]; 3397 c->c_next = new; 3398 c = new; 3399 } 3400 3401 c->c_next = NULL; 3402 } 3403 3404 3405 /* 3406 **++ 3407 ** FUNCTIONAL DESCRIPTION: 3408 ** 3409 ** scrClkStart 3410 ** 3411 ** This function starts the clock running. The clock is reall the 3412 ** HAT clock (High Available Timer) that is using a FIQ (fast interrupt 3413 ** request). 3414 ** 3415 ** FORMAL PARAMETERS: 3416 ** 3417 ** sc - Pointer to the softc structure. 3418 ** countPerTick - value for T2 timer that drives FIQ 3419 ** 3420 ** IMPLICIT INPUTS: 3421 ** 3422 ** nill 3423 ** 3424 ** IMPLICIT OUTPUTS: 3425 ** 3426 ** nill 3427 ** 3428 ** FUNCTION VALUE: 3429 ** 3430 ** nill 3431 ** 3432 ** SIDE EFFECTS: 3433 ** 3434 ** nill 3435 **-- 3436 */ 3437 static void scrClkStart(struct scr_softc * sc,int countPerTick) 3438 { 3439 u_int savedInts; 3440 3441 savedInts = disable_interrupts(I32_bit | F32_bit); 3442 3443 3444 3445 ASSERT(scrClkCallTodo.c_next == NULL); 3446 ASSERT(!scrClkEnable); 3447 scrClkEnable = 1; 3448 scrClkCount = countPerTick; 3449 3450 hatClkOn(countPerTick, 3451 hatClkIrq, 3452 0xdeadbeef, 3453 hatStack + HATSTACKSIZE - sizeof(unsigned), 3454 myHatWedge); 3455 3456 restore_interrupts(savedInts); 3457 } 3458 3459 /* 3460 **++ 3461 ** FUNCTIONAL DESCRIPTION: 3462 ** 3463 ** scrClkAdj 3464 ** 3465 ** Adjusts the frequence of the clock 3466 ** 3467 ** FORMAL PARAMETERS: 3468 ** 3469 ** count - new value for T2 timer that drives FIQ 3470 ** 3471 ** IMPLICIT INPUTS: 3472 ** 3473 ** nill 3474 ** 3475 ** IMPLICIT OUTPUTS: 3476 ** 3477 ** nill 3478 ** 3479 ** FUNCTION VALUE: 3480 ** 3481 ** nill 3482 ** 3483 ** SIDE EFFECTS: 3484 ** 3485 ** nill 3486 **-- 3487 */ 3488 static void scrClkAdj (int count) 3489 { 3490 u_int savedInts; 3491 3492 if (count != scrClkCount) 3493 { 3494 savedInts = disable_interrupts(I32_bit | F32_bit); 3495 3496 ASSERT(scrClkEnable); 3497 3498 scrClkCount = count; 3499 hatClkAdjust(count); 3500 3501 restore_interrupts(savedInts); 3502 } 3503 } 3504 3505 /* 3506 **++ 3507 ** FUNCTIONAL DESCRIPTION: 3508 ** 3509 ** scrClkStop 3510 ** 3511 ** Stops the clock 3512 ** 3513 ** FORMAL PARAMETERS: 3514 ** 3515 ** nill 3516 ** 3517 ** 3518 ** IMPLICIT INPUTS: 3519 ** 3520 ** nill 3521 ** 3522 ** IMPLICIT OUTPUTS: 3523 ** 3524 ** nill 3525 ** 3526 ** FUNCTION VALUE: 3527 ** 3528 ** nill 3529 ** 3530 ** SIDE EFFECTS: 3531 ** 3532 ** nill 3533 **-- 3534 */ 3535 static void scrClkStop(void) 3536 { 3537 u_int savedInts; 3538 savedInts = disable_interrupts(I32_bit | F32_bit); 3539 3540 ASSERT(scrClkEnable); 3541 scrClkEnable = 0; 3542 ASSERT(scrClkCallTodo.c_next == NULL); 3543 hatClkOff(); 3544 3545 restore_interrupts(savedInts); 3546 } 3547 3548 3549 3550 /* 3551 **++ 3552 ** FUNCTIONAL DESCRIPTION: 3553 ** 3554 ** hatClkIrq 3555 ** 3556 ** This is what the HAT clock calls. This call drives 3557 ** the timeout queues, which in turn drive the state machines 3558 ** 3559 ** Be very carefully when calling a timeout as the function 3560 ** that is called may in turn do timeout/untimeout calls 3561 ** before returning 3562 ** 3563 ** FORMAL PARAMETERS: 3564 ** 3565 ** int x - not used 3566 ** 3567 ** IMPLICIT INPUTS: 3568 ** 3569 ** nill 3570 ** 3571 ** IMPLICIT OUTPUTS: 3572 ** 3573 ** nill 3574 ** 3575 ** FUNCTION VALUE: 3576 ** 3577 ** nill 3578 ** 3579 ** SIDE EFFECTS: 3580 ** 3581 ** a timeout may be called if it is due 3582 **-- 3583 */ 3584 static void hatClkIrq(int x) 3585 { 3586 register Callout *p1; 3587 register int needsoft =0; 3588 register Callout *c; 3589 register int arg; 3590 register void (*func)(struct scr_softc*,int); 3591 struct scr_softc * sc; 3592 3593 ASSERT(scrClkEnable); 3594 for (p1 = scrClkCallTodo.c_next; p1 != NULL; p1 = p1->c_next) 3595 { 3596 p1->c_time -= scrClkCount; 3597 3598 if (p1->c_time > 0) 3599 { 3600 break; 3601 } 3602 needsoft = 1; 3603 if (p1->c_time == 0) 3604 { 3605 break; 3606 } 3607 } 3608 3609 3610 if (needsoft) 3611 { 3612 while ((c = scrClkCallTodo.c_next) != NULL && c->c_time <= 0) 3613 { 3614 func = c->c_func; 3615 sc = c->c_sc; 3616 arg = c->c_arg; 3617 scrClkCallTodo.c_next = c->c_next; 3618 c->c_next = scrClkCallFree; 3619 scrClkCallFree = c; 3620 (*func)(sc,arg); 3621 } 3622 } 3623 } 3624 3625 /* 3626 **++ 3627 ** FUNCTIONAL DESCRIPTION: 3628 ** 3629 ** myHatWedge 3630 ** 3631 ** Called if the HAT timer becomes clogged/wedged. Not 3632 ** used by this driver, we let upper layers recover 3633 ** from this condition 3634 ** 3635 ** FORMAL PARAMETERS: 3636 ** 3637 ** int nFIQs - not used 3638 ** 3639 ** IMPLICIT INPUTS: 3640 ** 3641 ** nill 3642 ** 3643 ** IMPLICIT OUTPUTS: 3644 ** 3645 ** nill 3646 ** 3647 ** FUNCTION VALUE: 3648 ** 3649 ** nill 3650 ** 3651 ** SIDE EFFECTS: 3652 ** 3653 ** nill 3654 **-- 3655 */ 3656 static void myHatWedge(int nFIQs) 3657 { 3658 #ifdef DEBUG 3659 printf("myHatWedge: nFIQ = %d\n",nFIQs); 3660 #endif 3661 } 3662 3663 3664 3665 /* 3666 **++ 3667 ** FUNCTIONAL DESCRIPTION: 3668 ** 3669 ** scrTimeout 3670 ** 3671 ** Execute a function after a specified length of time. 3672 ** 3673 ** 3674 ** FORMAL PARAMETERS: 3675 ** 3676 ** ftn - function to execute 3677 ** sc - pointer to soft c 3678 ** arg - argument passed to function 3679 ** count - number of T2 counts for timeout 3680 ** 3681 ** IMPLICIT INPUTS: 3682 ** 3683 ** nill 3684 ** 3685 ** IMPLICIT OUTPUTS: 3686 ** 3687 ** nill 3688 ** 3689 ** FUNCTION VALUE: 3690 ** 3691 ** nill 3692 ** 3693 ** SIDE EFFECTS: 3694 ** 3695 ** nill 3696 **-- 3697 */ 3698 3699 static void scrTimeout(ftn, sc, arg, count) 3700 void (*ftn)(struct scr_softc*,int); 3701 struct scr_softc* sc; 3702 int arg; 3703 register int count; 3704 { 3705 3706 register Callout *new, *p, *t; 3707 ASSERT(scrClkEnable); 3708 3709 3710 if (count <= 0) 3711 { 3712 count = 1; 3713 } 3714 3715 3716 /* Fill in the next free fcallout structure. */ 3717 if (scrClkCallFree == NULL) 3718 { 3719 panic("timeout table full"); 3720 } 3721 3722 new = scrClkCallFree; 3723 scrClkCallFree = new->c_next; 3724 new->c_sc = sc; 3725 new->c_arg = arg; 3726 new->c_func = ftn; 3727 3728 /* 3729 * The time for each event is stored as a difference from the time 3730 * of the previous event on the queue. Walk the queue, correcting 3731 * the counts argument for queue entries passed. Correct the counts 3732 * value for the queue entry immediately after the insertion point 3733 * as well. Watch out for negative c_time values; these represent 3734 * overdue events. 3735 */ 3736 for (p = &scrClkCallTodo; (t = p->c_next) != NULL && count > t->c_time; p = t) 3737 { 3738 if (t->c_time > 0) 3739 { 3740 count -= t->c_time; 3741 } 3742 } 3743 3744 3745 new->c_time = count; 3746 if (t != NULL) 3747 { 3748 t->c_time -= count; 3749 } 3750 3751 /* Insert the new entry into the queue. */ 3752 p->c_next = new; 3753 new->c_next = t; 3754 } 3755 3756 /* 3757 **++ 3758 ** FUNCTIONAL DESCRIPTION: 3759 ** 3760 ** scrUntimeout 3761 ** 3762 ** Cancel previous timeout function call. 3763 ** 3764 ** FORMAL PARAMETERS: 3765 ** 3766 ** ftn - function of timeout to cancel 3767 ** sc - sc of timeout to cancel 3768 ** arg - arg of timeout to cancel 3769 ** 3770 ** IMPLICIT INPUTS: 3771 ** 3772 ** nill 3773 ** 3774 ** IMPLICIT OUTPUTS: 3775 ** 3776 ** nill 3777 ** 3778 ** FUNCTION VALUE: 3779 ** 3780 ** nill 3781 ** 3782 ** SIDE EFFECTS: 3783 ** 3784 ** nill 3785 **-- 3786 */ 3787 static void scrUntimeout(ftn, sc, arg) 3788 void (*ftn)(struct scr_softc*,int); 3789 struct scr_softc* sc; 3790 int arg; 3791 { 3792 register Callout *p, *t; 3793 ASSERT(scrClkEnable); 3794 3795 for (p = &scrClkCallTodo; (t = p->c_next) != NULL; p = t) 3796 { 3797 if (t->c_func == ftn && t->c_sc == sc && t->c_arg == arg) 3798 { 3799 /* Increment next entry's count. */ 3800 if (t->c_next && t->c_time > 0) 3801 { 3802 t->c_next->c_time += t->c_time; 3803 } 3804 3805 /* Move entry from fcallout queue to scrClkCallFree queue. */ 3806 p->c_next = t->c_next; 3807 t->c_next = scrClkCallFree; 3808 scrClkCallFree = t; 3809 break; 3810 } 3811 } 3812 } 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 /******************* routines used only during debugging */ 3829 #ifdef SCR_DEBUG 3830 3831 /* 3832 **++ 3833 ** FUNCTIONAL DESCRIPTION: 3834 ** 3835 ** invalidStateCmd 3836 ** 3837 ** Debugging function. Printout information about problem 3838 ** and then kick in the debugger or panic 3839 ** 3840 ** FORMAL PARAMETERS: 3841 ** 3842 ** sc - pointer to soft c 3843 ** state - state of machine 3844 ** cmd - command of machine 3845 ** line - line that problem was detected 3846 ** 3847 ** 3848 ** IMPLICIT INPUTS: 3849 ** 3850 ** nill 3851 ** 3852 ** IMPLICIT OUTPUTS: 3853 ** 3854 ** nill 3855 ** 3856 ** FUNCTION VALUE: 3857 ** 3858 ** nill 3859 ** 3860 ** SIDE EFFECTS: 3861 ** 3862 ** nill 3863 **-- 3864 */ 3865 void invalidStateCmd (struct scr_softc* sc,int state,int cmd,int line) 3866 { 3867 printf("INVALID_STATE_CMD: sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,line); 3868 DEBUGGER; 3869 } 3870 3871 /* 3872 **++ 3873 ** FUNCTIONAL DESCRIPTION: 3874 ** 3875 ** getText 3876 ** 3877 ** Get text representation of state or command 3878 ** 3879 ** FORMAL PARAMETERS: 3880 ** 3881 ** x - state or command 3882 ** 3883 ** IMPLICIT INPUTS: 3884 ** 3885 ** nill 3886 ** 3887 ** IMPLICIT OUTPUTS: 3888 ** 3889 ** nill 3890 ** 3891 ** FUNCTION VALUE: 3892 ** 3893 ** nill 3894 ** 3895 ** SIDE EFFECTS: 3896 ** 3897 ** nill 3898 **-- 3899 */ 3900 char * getText(int x) 3901 { 3902 switch (x) 3903 { 3904 /* commands to Master State Machine (mc = Master Command )*/ 3905 case mcOn: return "mcOn"; 3906 case mcT0DataSend: return "mcT0DataSend"; 3907 case mcT0DataRecv: return "mcT0DataRecv"; 3908 case mcColdReset: return "mcColdReset"; 3909 case mcATR: return "mcATR"; 3910 case mcT0Send: return "mcT0Send"; 3911 case mcT0Recv: return "mcT0Recv"; 3912 3913 /* states in Master state machine (ms = Master State) */ 3914 case msIdleOff: return "msIdleOff"; 3915 case msColdReset: return "msColdReset"; 3916 case msATR: return "msATR"; 3917 case msIdleOn: return "msIdleOn"; 3918 case msT0Send: return "msT0Send"; 3919 case msT0Recv: return "msT0Recv"; 3920 3921 3922 3923 /* commands to T0 send state machine */ 3924 case t0scStart: return "t0scStart"; 3925 case t0scTWorkWaiting: return "t0scTWorkWaiting"; 3926 3927 3928 /* states in T0 send state machine */ 3929 case t0ssIdle: return "t0ssIdle"; 3930 case t0ssSendHeader: return "t0ssSendHeader"; 3931 case t0ssRecvProcedure: return "t0ssRecvProcedu"; 3932 case t0ssSendByte: return "t0ssSendByte"; 3933 case t0ssSendData: return "t0ssSendData"; 3934 case t0ssRecvSW1: return "t0ssRecvSW1"; 3935 case t0ssRecvSW2: return "t0ssRecvSW2"; 3936 3937 3938 /* commands to T0 recv state machine */ 3939 case t0rcStart: return "t0rcStart"; 3940 case t0rcTWorkWaiting: return "t0rcTWorkWaiting"; 3941 3942 /* states in T0 recv state machine */ 3943 case t0rsIdle: return "t0rsIdle"; 3944 case t0rsSendHeader: return "t0rsSendHeader"; 3945 case t0rsRecvProcedure: return "t0rsRecvProcedure"; 3946 case t0rsRecvByte: return "t0rsRecvByte"; 3947 case t0rsRecvData: return "t0rsRecvData"; 3948 case t0rsRecvSW1: return "t0rsRecvSW1"; 3949 case t0rsRecvSW2: return "t0rsRecvSW2"; 3950 3951 3952 3953 3954 3955 /* commands to Answer To Reset (ATR) state machine */ 3956 case atrcStart: return "atrcStart"; 3957 case atrcT3: return "0x0b04"; 3958 case atrcTWorkWaiting: return "atrcTWorkWaiting"; 3959 3960 3961 /* states in in Anser To Reset (ATR) state machine */ 3962 case atrsIdle: return "atrsIdle"; 3963 case atrsTS: return "atrsTS"; 3964 case atrsT0: return "atrsT0"; 3965 case atrsTABCD: return "atrsTABCD"; 3966 case atrsTK: return "atrsTK"; 3967 case atrsTCK: return "atrsTCK"; 3968 3969 3970 3971 /* commands to T0 Recv Byte state machine */ 3972 case t0rbcStart: return "t0rbcStart"; 3973 case t0rbcAbort: return "t0rbcAbort"; 3974 3975 case t0rbcTFindStartEdge:return "t0rbcTFindStartEdge"; 3976 case t0rbcTFindStartMid: return "t0rbcTFindStartMid"; 3977 case t0rbcTClockData: return "t0rbcTClockData"; 3978 case t0rbcTErrorStart: return "t0rbcTErrorStart"; 3979 case t0rbcTErrorStop: return "t0rbcTErrorStop"; 3980 3981 /* states in in TO Recv Byte state machine */ 3982 case t0rbsIdle: return "t0rbsIdle"; 3983 case t0rbsFindStartEdge: return "t0rbcFindStartEdge"; 3984 case t0rbsFindStartMid: return "t0rbcFindStartMid"; 3985 case t0rbsClockData: return "t0rbcClockData"; 3986 case t0rbsSendError: return "t0rbcSendError"; 3987 3988 3989 /* commands to T0 Send Byte state machine */ 3990 case t0sbcStart: return "t0sbcStart"; 3991 case t0sbcAbort: return "t0sbcAbort"; 3992 case t0sbcTGuardTime: return "t0sbcTGuardTime"; 3993 case t0sbcTClockData: return "t0sbcTClockData"; 3994 case t0sbcTError: return "t0sbcTError"; 3995 case t0sbcTResend: return "t0sbcTResend"; 3996 3997 /* states in in T0 Send Byte state machine */ 3998 case t0sbsIdle: return "t0sbsIdle"; 3999 case t0sbsClockData: return "t0sbsClockData"; 4000 case t0sbsWaitError: return "t0sbsWaitError"; 4001 case t0sbsWaitResend: return "t0sbsWaitResend"; 4002 case t0sbsWaitGuardTime: return "t0sbsWaitGuardTime"; 4003 4004 4005 case gcT0RecvByte: return "gcT0RecvByte"; 4006 case gcT0RecvByteErr: return "gcT0RecvByteErr"; 4007 case gcT0SendByte: return "gcT0SendByte"; 4008 case gcT0SendByteErr: return "gcT0SendByteErr"; 4009 4010 4011 case crcStart: return "crcStart"; 4012 case crcT2: return "crcT2"; 4013 4014 4015 default: 4016 printf("unknown case, %x\n",x); 4017 break; 4018 } 4019 return "???"; 4020 } 4021 4022 #endif /* SCR_DEBUG */ 4023 4024 4025 4026