1 /* $NetBSD: vlpci.c,v 1.8 2017/04/18 14:11:42 flxd Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: vlpci.c,v 1.8 2017/04/18 14:11:42 flxd Exp $"); 31 32 #include "opt_pci.h" 33 #include "pci.h" 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/mutex.h> 40 #include <uvm/uvm.h> 41 #include <machine/pio.h> 42 #include <machine/pmap.h> 43 #include <machine/ofw.h> 44 45 #include <dev/isa/isavar.h> 46 47 #include <dev/ofw/openfirm.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 #include <arm/pci_machdep.h> 52 53 #include <shark/ofw/vlpci.h> 54 55 #define VLPCI_ADDON_DEV_NO 6 56 #define VLPCI_IRQ 10 57 58 #define VLPCI_PCI_MEM_BASE 0x02000000 59 #define VLPCI_PCI_MEM_SZ 1048576 60 61 #define VLPCI_VL_MEM_BASE 0x08000000 62 #define VLPCI_VL_MEM_SZ 4194304 63 64 static int vlpci_match(device_t, struct cfdata *, void *); 65 static void vlpci_attach(device_t, device_t, void *); 66 67 static void vlpci_pc_attach_hook(device_t, device_t, 68 struct pcibus_attach_args *); 69 static int vlpci_pc_bus_maxdevs(void *, int); 70 static pcitag_t vlpci_pc_make_tag(void *, int, int, int); 71 static void vlpci_pc_decompose_tag(void *, pcitag_t, int *, int *, int *); 72 static pcireg_t vlpci_pc_conf_read(void *, pcitag_t, int); 73 static void vlpci_pc_conf_write(void *, pcitag_t, int, pcireg_t); 74 75 static int vlpci_pc_intr_map(const struct pci_attach_args *, 76 pci_intr_handle_t *); 77 static const char * vlpci_pc_intr_string(void *, pci_intr_handle_t, char *, 78 size_t); 79 static const struct evcnt * vlpci_pc_intr_evcnt(void *, pci_intr_handle_t); 80 static void * vlpci_pc_intr_establish(void *, pci_intr_handle_t, int, 81 int (*)(void *), void *); 82 static void vlpci_pc_intr_disestablish(void *, void *); 83 84 #ifdef __HAVE_PCI_CONF_HOOK 85 static int vlpci_pc_conf_hook(void *, int, int, int, pcireg_t); 86 #endif 87 static void vlpci_pc_conf_interrupt(void *, int, int, int, int, int *); 88 89 struct vlpci_softc { 90 device_t sc_dev; 91 kmutex_t sc_lock; 92 bus_space_handle_t sc_conf_ioh; 93 bus_space_handle_t sc_reg_ioh; 94 struct arm32_pci_chipset sc_pc; 95 }; 96 97 CFATTACH_DECL_NEW(vlpci, sizeof(struct vlpci_softc), 98 vlpci_match, vlpci_attach, NULL, NULL); 99 100 static const char * const compat_strings[] = { "via,vt82c505", NULL }; 101 102 vaddr_t vlpci_mem_vaddr = 0; 103 paddr_t vlpci_mem_paddr; 104 struct bus_space vlpci_memt; 105 106 static void 107 regwrite_1(struct vlpci_softc * const sc, uint8_t off, uint8_t val) 108 { 109 110 mutex_spin_enter(&sc->sc_lock); 111 bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_IDX_OFF, 112 off); 113 bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_DATA_OFF, 114 val); 115 mutex_spin_exit(&sc->sc_lock); 116 } 117 118 static uint8_t 119 regread_1(struct vlpci_softc * const sc, uint8_t off) 120 { 121 uint8_t reg; 122 123 mutex_spin_enter(&sc->sc_lock); 124 bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_IDX_OFF, 125 off); 126 reg = bus_space_read_1(&isa_io_bs_tag, sc->sc_reg_ioh, 127 VLPCI_INTREG_DATA_OFF); 128 mutex_spin_exit(&sc->sc_lock); 129 return reg; 130 } 131 132 static void 133 vlpci_dump_window(struct vlpci_softc *sc, int num) 134 { 135 int regaddr = VLPCI_PCI_WND_HIADDR_REG(num); 136 uint32_t addr, size; 137 uint8_t attr; 138 139 addr = regread_1(sc, regaddr) << 24; 140 addr |= regread_1(sc, regaddr + 1) << 16; 141 attr = regread_1(sc, regaddr + 2); 142 size = 0x00010000 << __SHIFTOUT(attr, VLPCI_PCI_WND_ATTR_SZ); 143 printf("memory window #%d at %08x size %08x flags %x\n", num, addr, 144 size, attr); 145 } 146 147 static int 148 vlpci_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, 149 bus_space_handle_t *bshp) 150 { 151 152 *bshp = vlpci_mem_vaddr - VLPCI_PCI_MEM_BASE + bpa; 153 printf("%s: %08lx -> %08lx\n", __func__, bpa, *bshp); 154 return(0); 155 } 156 157 static paddr_t 158 vlpci_mmap(void *cookie, bus_addr_t addr, off_t off, int prot, 159 int flags) 160 { 161 paddr_t ret; 162 163 ret = vlpci_mem_paddr + addr + off; 164 165 if (flags & BUS_SPACE_MAP_PREFETCHABLE) 166 return (arm_btop(ret) | ARM32_MMAP_WRITECOMBINE); 167 else 168 return arm_btop(ret); 169 } 170 171 static void 172 vlpci_steer_irq(struct vlpci_softc * const sc) 173 { 174 const unsigned int_ctl[] = { 175 VLPCI_INT_CTL_INTA, VLPCI_INT_CTL_INTB, 176 VLPCI_INT_CTL_INTC, VLPCI_INT_CTL_INTD 177 }; 178 uint8_t val; 179 180 for (size_t i = 0; i < __arraycount(int_ctl); i++) { 181 val = regread_1(sc, VLPCI_INT_CTL_REG(int_ctl[i])); 182 val &= ~VLPCI_INT_CTL_INT2IRQ(int_ctl[i]); 183 val |= VLPCI_INT_CTL_ENA(int_ctl[i]); 184 val |= __SHIFTIN(VLPCI_INT_CTL_IRQ(VLPCI_IRQ), 185 VLPCI_INT_CTL_INT2IRQ(int_ctl[i])); 186 regwrite_1(sc, VLPCI_INT_CTL_REG(int_ctl[i]), val); 187 } 188 } 189 190 static int 191 vlpci_match(device_t parent, struct cfdata *match, void *aux) 192 { 193 struct ofbus_attach_args * const oba = aux; 194 195 if (of_compatible(oba->oba_phandle, compat_strings) < 0) 196 return 0; 197 198 return 2; /* beat generic ofbus */ 199 } 200 201 static void 202 vlpci_attach(device_t parent, device_t self, void *aux) 203 { 204 struct vlpci_softc * const sc = device_private(self); 205 pci_chipset_tag_t const pc = &sc->sc_pc; 206 struct pcibus_attach_args pba; 207 pcitag_t tag; 208 pcireg_t cmd; 209 210 aprint_normal("\n"); 211 212 sc->sc_dev = self; 213 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 214 memset(&pba, 0, sizeof(pba)); 215 216 if (bus_space_map(&isa_io_bs_tag, VLPCI_INTREG_BASE, VLPCI_INTREG_SZ, 217 0, &sc->sc_reg_ioh) != 0) { 218 aprint_error_dev(self, "failed to map internal reg port\n"); 219 return; 220 } 221 if (bus_space_map(&isa_io_bs_tag, VLPCI_CFGREG_BASE, VLPCI_CFGREG_SZ, 222 0, &sc->sc_conf_ioh) != 0) { 223 aprint_error_dev(self, "failed to map configuration port\n"); 224 return; 225 } 226 227 /* Enable VLB/PCI bridge */ 228 regwrite_1(sc, VLPCI_MISC_1_REG, VLPCI_MISC_1_LOCAL_PIN | 229 VLPCI_MISC_1_COMPAT_ISA_BOFF); 230 regwrite_1(sc, VLPCI_MISC_CTL_REG, __SHIFTIN(VLPCI_MISC_CTL_HIADDR_DIS, 231 VLPCI_MISC_CTL_HIADDR) | VLPCI_MISC_CTL_IOCHCK_PIN); 232 regwrite_1(sc, VLPCI_CFG_MISC_CTL_REG, 233 __SHIFTIN(VLPCI_CFG_MISC_CTL_INT_CTL_CONV, 234 VLPCI_CFG_MISC_CTL_INT_CTL) | VLPCI_CFG_MISC_CTL_LREQI_LGNTO_PIN); 235 regwrite_1(sc, VLPCI_IRQ_MODE_REG, 0x00); /* don't do per-INTx conversions */ 236 vlpci_steer_irq(sc); 237 /* 238 * XXX 239 * set memory size to 255MB, so the bridge knows which cycles go to RAM 240 * shark's RAM is in the upper half of the lower 256MB, part of the 241 * lower half is occupied by the graphics chip 242 * ... or that's the theory. OF puts PCI BARS at 0x02000000 which 243 * overlaps with when we do this and pci memory access doesn't work. 244 */ 245 regwrite_1(sc, VLPCI_OBD_MEM_SZ_REG, 1); 246 247 regwrite_1(sc, VLPCI_BUF_CTL_REG, VLPCI_BUF_CTL_PCI_DYN_ACC_DEC); 248 regwrite_1(sc, VLPCI_VL_TIM_REG, VLPCI_VL_TIM_OBD_MEM_1ST_DAT); 249 printf("reg 0x83 %02x\n", regread_1(sc, VLPCI_VL_TIM_REG)); 250 251 #if 1 252 /* program window #0 to 0x08000000 */ 253 regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_1), 254 VLPCI_PCI_WND_HIADDR_MEM(VLPCI_VL_MEM_BASE)); 255 regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_1), 256 VLPCI_PCI_WND_LOADDR_MEM(VLPCI_VL_MEM_BASE)); 257 regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_1), 258 VLPCI_PCI_WND_ATTR_VL | 259 __SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_VL_MEM_SZ), 260 VLPCI_PCI_WND_ATTR_SZ)); 261 #else 262 regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_1), 0x00); 263 regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_1), 0x00); 264 regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_1), 0x00); 265 #endif 266 267 vlpci_mem_paddr = VLPCI_PCI_MEM_BASE; /* get from OF! */ 268 269 /* 270 * we map in 1MB at 0x02000000, so program window #1 accordingly 271 */ 272 regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_2), 273 VLPCI_PCI_WND_HIADDR_MEM(vlpci_mem_paddr)); 274 regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_2), 275 VLPCI_PCI_WND_LOADDR_MEM(vlpci_mem_paddr)); 276 regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_2), 277 VLPCI_PCI_WND_ATTR_PCI | 278 __SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_PCI_MEM_SZ), 279 VLPCI_PCI_WND_ATTR_SZ)); 280 281 /* now map in some of the memory space */ 282 printf("vlpci_mem_vaddr %08lx\n", vlpci_mem_vaddr); 283 memcpy(&vlpci_memt, &isa_io_bs_tag, sizeof(struct bus_space)); 284 vlpci_memt.bs_cookie = (void *)vlpci_mem_vaddr; 285 vlpci_memt.bs_map = vlpci_map; 286 vlpci_memt.bs_mmap = vlpci_mmap; 287 288 pc->pc_conf_v = sc; 289 pc->pc_attach_hook = vlpci_pc_attach_hook; 290 pc->pc_bus_maxdevs = vlpci_pc_bus_maxdevs; 291 pc->pc_make_tag = vlpci_pc_make_tag; 292 pc->pc_decompose_tag = vlpci_pc_decompose_tag; 293 pc->pc_conf_read = vlpci_pc_conf_read; 294 pc->pc_conf_write = vlpci_pc_conf_write; 295 296 pc->pc_intr_v = sc; 297 pc->pc_intr_map = vlpci_pc_intr_map; 298 pc->pc_intr_string = vlpci_pc_intr_string; 299 pc->pc_intr_evcnt = vlpci_pc_intr_evcnt; 300 pc->pc_intr_establish = vlpci_pc_intr_establish; 301 pc->pc_intr_disestablish = vlpci_pc_intr_disestablish; 302 303 #ifdef __HAVE_PCI_CONF_HOOK 304 pc->pc_conf_hook = vlpci_pc_conf_hook; 305 #endif 306 pc->pc_conf_interrupt = vlpci_pc_conf_interrupt; 307 308 /* try to assure IO space is enabled on the default device-function */ 309 tag = vlpci_pc_make_tag(sc, 0, VLPCI_ADDON_DEV_NO, 0); 310 cmd = vlpci_pc_conf_read(sc, tag, PCI_COMMAND_STATUS_REG); 311 vlpci_pc_conf_write(sc, tag, PCI_COMMAND_STATUS_REG, 312 cmd | PCI_COMMAND_IO_ENABLE); 313 314 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 315 pba.pba_iot = &isa_io_bs_tag; 316 pba.pba_memt = &vlpci_memt; 317 pba.pba_dmat = &isa_bus_dma_tag; 318 pba.pba_pc = &sc->sc_pc; 319 pba.pba_bus = 0; 320 321 printf("dma %lx %lx, %lx\n", isa_bus_dma_tag._ranges[0].dr_sysbase, 322 isa_bus_dma_tag._ranges[0].dr_busbase, 323 isa_bus_dma_tag._ranges[0].dr_len); 324 325 vlpci_dump_window(sc, VLPCI_PCI_WND_NO_1); 326 vlpci_dump_window(sc, VLPCI_PCI_WND_NO_2); 327 vlpci_dump_window(sc, VLPCI_PCI_WND_NO_3); 328 329 config_found_ia(self, "pcibus", &pba, pcibusprint); 330 } 331 332 static void 333 vlpci_pc_attach_hook(device_t parent, device_t self, 334 struct pcibus_attach_args *pba) 335 { 336 } 337 338 static int 339 vlpci_pc_bus_maxdevs(void *v, int busno) 340 { 341 342 return busno == 0 ? 32 : 0; 343 } 344 345 static pcitag_t 346 vlpci_pc_make_tag(void *v, int b, int d, int f) 347 { 348 349 return (b << 16) | (d << 11) | (f << 8); 350 } 351 352 static void 353 vlpci_pc_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 354 { 355 356 if (bp) 357 *bp = (tag >> 16) & 0xff; 358 if (dp) 359 *dp = (tag >> 11) & 0x1f; 360 if (fp) 361 *fp = (tag >> 8) & 0x7; 362 } 363 364 static pcireg_t 365 vlpci_pc_conf_read(void *v, pcitag_t tag, int offset) 366 { 367 struct vlpci_softc * const sc = v; 368 pcireg_t ret; 369 370 KASSERT((offset & 3) == 0); 371 372 if (offset >= PCI_CONF_SIZE) 373 return 0xffffffff; 374 375 mutex_spin_enter(&sc->sc_lock); 376 bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh, 377 VLPCI_CFGREG_ADDR_OFF, 0x80000000UL|tag|offset); 378 ret = bus_space_read_4(&isa_io_bs_tag, sc->sc_conf_ioh, 379 VLPCI_CFGREG_DATA_OFF); 380 mutex_spin_exit(&sc->sc_lock); 381 382 #if 0 383 device_printf(sc->sc_dev, "%s tag %x offset %x ret %x\n", 384 __func__, (unsigned int)tag, offset, ret); 385 #endif 386 387 return ret; 388 } 389 390 static void 391 vlpci_pc_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 392 { 393 struct vlpci_softc * const sc = v; 394 395 KASSERT((offset & 3) == 0); 396 397 if (offset >= PCI_CONF_SIZE) 398 return; 399 400 #if 0 401 device_printf(sc->sc_dev, "%s tag %x offset %x val %x\n", 402 __func__, (unsigned int)tag, offset, val); 403 #endif 404 405 mutex_spin_enter(&sc->sc_lock); 406 bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh, 407 VLPCI_CFGREG_ADDR_OFF, 0x80000000UL|tag|offset); 408 bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh, 409 VLPCI_CFGREG_DATA_OFF, val); 410 mutex_spin_exit(&sc->sc_lock); 411 } 412 413 static int 414 vlpci_pc_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 415 { 416 417 switch (pa->pa_intrpin) { 418 default: 419 case 0: 420 return EINVAL; 421 case 1: 422 case 2: 423 case 3: 424 case 4: 425 *ih = VLPCI_IRQ; 426 return 0; 427 } 428 } 429 430 static const char * 431 vlpci_pc_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 432 { 433 434 if (ih == PCI_INTERRUPT_PIN_NONE) 435 return NULL; 436 snprintf(buf, len, "irq %lu", ih); 437 return buf; 438 } 439 440 static const struct evcnt * 441 vlpci_pc_intr_evcnt(void *v, pci_intr_handle_t ih) 442 { 443 444 return NULL; 445 } 446 447 static void * 448 vlpci_pc_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 449 int (*callback)(void *), void *arg) 450 { 451 452 if (pih == 0) 453 return NULL; 454 455 return isa_intr_establish(NULL, pih, IST_LEVEL, ipl, callback, arg); 456 } 457 458 static void 459 vlpci_pc_intr_disestablish(void *v, void *w) 460 { 461 462 return isa_intr_disestablish(NULL, v); 463 } 464 465 #ifdef __HAVE_PCI_CONF_HOOK 466 static int 467 vlpci_pc_conf_hook(void *v, int b, int d, int f, pcireg_t id) 468 { 469 470 return PCI_CONF_DEFAULT /*& ~PCI_CONF_ENABLE_BM*/; 471 } 472 #endif 473 474 static void 475 vlpci_pc_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 476 int *ilinep) 477 { 478 479 *ilinep = 0xff; /* XXX */ 480 } 481