xref: /netbsd-src/sys/arch/sh3/sh3/devreg.c (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa)
1 /*	$NetBSD: devreg.c,v 1.6 2006/03/04 01:13:35 uwe Exp $	*/
2 
3 /*-
4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *        This product includes software developed by the NetBSD
18  *        Foundation, Inc. and its contributors.
19  * 4. Neither the name of The NetBSD Foundation nor the names of its
20  *    contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  * POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: devreg.c,v 1.6 2006/03/04 01:13:35 uwe Exp $");
38 
39 #include <sys/param.h>
40 
41 #include <sh3/exception.h>
42 #include <sh3/cache_sh3.h>
43 #include <sh3/cache_sh4.h>
44 #include <sh3/mmu_sh3.h>
45 #include <sh3/mmu_sh4.h>
46 
47 #include <sh3/ubcreg.h>
48 #include <sh3/rtcreg.h>
49 #include <sh3/tmureg.h>
50 
51 /* MMU */
52 uint32_t __sh_PTEH;
53 uint32_t __sh_TTB;
54 uint32_t __sh_TEA;
55 uint32_t __sh_TRA;
56 uint32_t __sh_EXPEVT;
57 uint32_t __sh_INTEVT;
58 
59 /* UBC */
60 uint32_t __sh_BARA;
61 uint32_t __sh_BAMRA;
62 uint32_t __sh_BASRA;
63 uint32_t __sh_BBRA;
64 uint32_t __sh_BARB;
65 uint32_t __sh_BAMRB;
66 uint32_t __sh_BASRB;
67 uint32_t __sh_BBRB;
68 uint32_t __sh_BDRB;
69 uint32_t __sh_BDMRB;
70 uint32_t __sh_BRCR;
71 
72 /* RTC */
73 uint32_t __sh_R64CNT;
74 uint32_t __sh_RSECCNT;
75 uint32_t __sh_RMINCNT;
76 uint32_t __sh_RHRCNT;
77 uint32_t __sh_RWKCNT;
78 uint32_t __sh_RDAYCNT;
79 uint32_t __sh_RMONCNT;
80 uint32_t __sh_RYRCNT;
81 uint32_t __sh_RSECAR;
82 uint32_t __sh_RMINAR;
83 uint32_t __sh_RHRAR;
84 uint32_t __sh_RWKAR;
85 uint32_t __sh_RDAYAR;
86 uint32_t __sh_RMONAR;
87 uint32_t __sh_RCR1;
88 uint32_t __sh_RCR2;
89 
90 /* TMU */
91 uint32_t __sh_TOCR;
92 uint32_t __sh_TSTR;
93 uint32_t __sh_TCOR0;
94 uint32_t __sh_TCNT0;
95 uint32_t __sh_TCR0;
96 uint32_t __sh_TCOR1;
97 uint32_t __sh_TCNT1;
98 uint32_t __sh_TCR1;
99 uint32_t __sh_TCOR2;
100 uint32_t __sh_TCNT2;
101 uint32_t __sh_TCR2;
102 uint32_t __sh_TCPR2;
103 
104 #define	SH3REG(x)	__sh_ ## x = SH3_ ## x
105 #define	SH4REG(x)	__sh_ ## x = SH4_ ## x
106 
107 #define	SHREG(x)							\
108 do {									\
109 /* Exception */								\
110 SH ## x ## REG(TRA);							\
111 SH ## x ## REG(EXPEVT);							\
112 SH ## x ## REG(INTEVT);							\
113 /* UBC */								\
114 SH ## x ## REG(BARA);							\
115 SH ## x ## REG(BAMRA);							\
116 SH ## x ## REG(BASRA);							\
117 SH ## x ## REG(BBRA);							\
118 SH ## x ## REG(BARB);							\
119 SH ## x ## REG(BAMRB);							\
120 SH ## x ## REG(BASRB);							\
121 SH ## x ## REG(BBRB);							\
122 SH ## x ## REG(BDRB);							\
123 SH ## x ## REG(BDMRB);							\
124 SH ## x ## REG(BRCR);							\
125 /* MMU */								\
126 SH ## x ## REG(PTEH);							\
127 SH ## x ## REG(TEA);							\
128 SH ## x ## REG(TTB);							\
129 /* RTC */								\
130 SH ## x ## REG(R64CNT);							\
131 SH ## x ## REG(RSECCNT);						\
132 SH ## x ## REG(RMINCNT);						\
133 SH ## x ## REG(RHRCNT);							\
134 SH ## x ## REG(RWKCNT);							\
135 SH ## x ## REG(RDAYCNT);						\
136 SH ## x ## REG(RMONCNT);						\
137 SH ## x ## REG(RYRCNT);							\
138 SH ## x ## REG(RSECAR);							\
139 SH ## x ## REG(RMINAR);							\
140 SH ## x ## REG(RHRAR);							\
141 SH ## x ## REG(RWKAR);							\
142 SH ## x ## REG(RDAYAR);							\
143 SH ## x ## REG(RMONAR);							\
144 SH ## x ## REG(RCR1);							\
145 SH ## x ## REG(RCR2);							\
146 /* TMU */								\
147 SH ## x ## REG(TOCR);							\
148 SH ## x ## REG(TSTR);							\
149 SH ## x ## REG(TCOR0);							\
150 SH ## x ## REG(TCNT0);							\
151 SH ## x ## REG(TCR0);							\
152 SH ## x ## REG(TCOR1);							\
153 SH ## x ## REG(TCNT1);							\
154 SH ## x ## REG(TCR1);							\
155 SH ## x ## REG(TCOR2);							\
156 SH ## x ## REG(TCNT2);							\
157 SH ## x ## REG(TCR2);							\
158 SH ## x ## REG(TCPR2);							\
159 } while (/*CONSTCOND*/0)
160 
161 void
162 sh_devreg_init()
163 {
164 
165 	if (CPU_IS_SH3)
166 		SHREG(3);
167 
168 	if (CPU_IS_SH4)
169 		SHREG(4);
170 
171 }
172