1 /* $NetBSD: devreg.c,v 1.3 2002/04/28 17:10:38 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 38 #include <sh3/exception.h> 39 #include <sh3/cache_sh3.h> 40 #include <sh3/cache_sh4.h> 41 #include <sh3/mmu_sh3.h> 42 #include <sh3/mmu_sh4.h> 43 44 #include <sh3/ubcreg.h> 45 #include <sh3/rtcreg.h> 46 #include <sh3/tmureg.h> 47 48 /* MMU */ 49 u_int32_t __sh_PTEH; 50 u_int32_t __sh_TTB; 51 u_int32_t __sh_TEA; 52 u_int32_t __sh_TRA; 53 u_int32_t __sh_EXPEVT; 54 u_int32_t __sh_INTEVT; 55 56 /* UBC */ 57 u_int32_t __sh_BARA; 58 u_int32_t __sh_BAMRA; 59 u_int32_t __sh_BASRA; 60 u_int32_t __sh_BBRA; 61 u_int32_t __sh_BARB; 62 u_int32_t __sh_BAMRB; 63 u_int32_t __sh_BASRB; 64 u_int32_t __sh_BBRB; 65 u_int32_t __sh_BDRB; 66 u_int32_t __sh_BDMRB; 67 u_int32_t __sh_BRCR; 68 69 /* RTC */ 70 u_int32_t __sh_R64CNT; 71 u_int32_t __sh_RSECCNT; 72 u_int32_t __sh_RMINCNT; 73 u_int32_t __sh_RHRCNT; 74 u_int32_t __sh_RWKCNT; 75 u_int32_t __sh_RDAYCNT; 76 u_int32_t __sh_RMONCNT; 77 u_int32_t __sh_RYRCNT; 78 u_int32_t __sh_RSECAR; 79 u_int32_t __sh_RMINAR; 80 u_int32_t __sh_RHRAR; 81 u_int32_t __sh_RWKAR; 82 u_int32_t __sh_RDAYAR; 83 u_int32_t __sh_RMONAR; 84 u_int32_t __sh_RCR1; 85 u_int32_t __sh_RCR2; 86 87 /* TMU */ 88 u_int32_t __sh_TOCR; 89 u_int32_t __sh_TSTR; 90 u_int32_t __sh_TCOR0; 91 u_int32_t __sh_TCNT0; 92 u_int32_t __sh_TCR0; 93 u_int32_t __sh_TCOR1; 94 u_int32_t __sh_TCNT1; 95 u_int32_t __sh_TCR1; 96 u_int32_t __sh_TCOR2; 97 u_int32_t __sh_TCNT2; 98 u_int32_t __sh_TCR2; 99 u_int32_t __sh_TCPR2; 100 101 #define SH3REG(x) __sh_ ## x = SH3_ ## x 102 #define SH4REG(x) __sh_ ## x = SH4_ ## x 103 104 #define SHREG(x) \ 105 do { \ 106 /* Exception */ \ 107 SH ## x ## REG(TRA); \ 108 SH ## x ## REG(EXPEVT); \ 109 SH ## x ## REG(INTEVT); \ 110 /* UBC */ \ 111 SH ## x ## REG(BARA); \ 112 SH ## x ## REG(BAMRA); \ 113 SH ## x ## REG(BASRA); \ 114 SH ## x ## REG(BBRA); \ 115 SH ## x ## REG(BARB); \ 116 SH ## x ## REG(BAMRB); \ 117 SH ## x ## REG(BASRB); \ 118 SH ## x ## REG(BBRB); \ 119 SH ## x ## REG(BDRB); \ 120 SH ## x ## REG(BDMRB); \ 121 SH ## x ## REG(BRCR); \ 122 /* MMU */ \ 123 SH ## x ## REG(PTEH); \ 124 SH ## x ## REG(TEA); \ 125 SH ## x ## REG(TTB); \ 126 /* RTC */ \ 127 SH ## x ## REG(R64CNT); \ 128 SH ## x ## REG(RSECCNT); \ 129 SH ## x ## REG(RMINCNT); \ 130 SH ## x ## REG(RHRCNT); \ 131 SH ## x ## REG(RWKCNT); \ 132 SH ## x ## REG(RDAYCNT); \ 133 SH ## x ## REG(RMONCNT); \ 134 SH ## x ## REG(RYRCNT); \ 135 SH ## x ## REG(RSECAR); \ 136 SH ## x ## REG(RMINAR); \ 137 SH ## x ## REG(RHRAR); \ 138 SH ## x ## REG(RWKAR); \ 139 SH ## x ## REG(RDAYAR); \ 140 SH ## x ## REG(RMONAR); \ 141 SH ## x ## REG(RCR1); \ 142 SH ## x ## REG(RCR2); \ 143 /* TMU */ \ 144 SH ## x ## REG(TOCR); \ 145 SH ## x ## REG(TSTR); \ 146 SH ## x ## REG(TCOR0); \ 147 SH ## x ## REG(TCNT0); \ 148 SH ## x ## REG(TCR0); \ 149 SH ## x ## REG(TCOR1); \ 150 SH ## x ## REG(TCNT1); \ 151 SH ## x ## REG(TCR1); \ 152 SH ## x ## REG(TCOR2); \ 153 SH ## x ## REG(TCNT2); \ 154 SH ## x ## REG(TCR2); \ 155 SH ## x ## REG(TCPR2); \ 156 } while (/*CONSTCOND*/0) 157 158 void 159 sh_devreg_init() 160 { 161 162 if (CPU_IS_SH3) 163 SHREG(3); 164 165 if (CPU_IS_SH4) 166 SHREG(4); 167 168 } 169