1 /* $NetBSD: intr.h,v 1.10 2001/01/14 02:00:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1997 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * SH3 Version 34 * 35 * T.Horiuchi Brains Corp. 5/22/98 36 */ 37 38 #ifndef _SH3_INTR_H_ 39 #define _SH3_INTR_H_ 40 41 /* Interrupt sharing types. */ 42 #define IST_NONE 0 /* none */ 43 #define IST_PULSE 1 /* pulsed */ 44 #define IST_EDGE 2 /* edge-triggered */ 45 #define IST_LEVEL 3 /* level-triggered */ 46 47 #ifndef _LOCORE 48 49 volatile int cpl, ipending, astpending; 50 int imask[NIPL]; 51 52 extern void Xspllower __P((void)); 53 54 static __inline int splraise __P((int)); 55 static __inline void spllower __P((int)); 56 static __inline void softintr __P((int)); 57 58 /* 59 * Add a mask to cpl, and return the old value of cpl. 60 */ 61 static __inline int 62 splraise(ncpl) 63 register int ncpl; 64 { 65 int ocpl ; 66 67 ocpl = cpl; 68 69 cpl = ocpl | ncpl; 70 return (ocpl); 71 } 72 73 /* 74 * Restore a value to cpl (unmasking interrupts). If any unmasked 75 * interrupts are pending, call Xspllower() to process them. 76 */ 77 static __inline void 78 spllower(ncpl) 79 register int ncpl; 80 { 81 82 cpl = ncpl; 83 if (ipending & ~ncpl) 84 Xspllower(); 85 } 86 87 /* 88 * Hardware interrupt masks 89 */ 90 #define splbio() splraise(imask[IPL_BIO]) 91 #define splnet() splraise(imask[IPL_NET]) 92 #define spltty() splraise(imask[IPL_TTY]) 93 #define splaudio() splraise(imask[IPL_AUDIO]) 94 #define splclock() splraise(imask[IPL_CLOCK]) 95 #define splstatclock() splclock() 96 #define splserial() splraise(imask[IPL_SERIAL]) 97 98 /* 99 * Software interrupt masks 100 * 101 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 102 * clock to softclock before it calls softclock(). 103 */ 104 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 105 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 106 #define splsoftnet() splraise(imask[IPL_SOFTNET]) 107 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 108 109 /* 110 * Miscellaneous 111 */ 112 #define splimp() splraise(imask[IPL_IMP]) 113 #define splvm() splraise(imask[IPL_IMP]) 114 #define splhigh() splraise(imask[IPL_HIGH]) 115 #define splsched() splhigh() 116 #define spllock() splhigh() 117 #define spl0() spllower(0) 118 #define splx(x) spllower(x) 119 120 /* 121 * Software interrupt registration 122 * 123 * We hand-code this to ensure that it's atomic. 124 */ 125 static __inline void 126 softintr(mask) 127 register int mask; 128 { 129 extern void enable_interrupt(void); /* XXX */ 130 extern void disable_interrupt(void); 131 132 disable_interrupt(); 133 ipending |= (1 << mask); 134 enable_interrupt(); 135 } 136 137 #define setsoftast() (astpending = 1) 138 #define setsoftclock() softintr(SIR_CLOCK) 139 #define setsoftnet() softintr(SIR_NET) 140 #define setsoftserial() softintr(SIR_SERIAL) 141 142 #endif /* !_LOCORE */ 143 144 #define INTEVT_SOFT 0xf00 /* This value is stored to INTEVT reg, 145 when software interrupt occured */ 146 #define INTEVT_TMU0 0x400 147 #define INTEVT_TMU1 0x420 148 #define INTEVT_TMU2 0x440 149 150 #define INTEVT_SCI0_ERI 0x4e0 151 #define INTEVT_SCI0_RXI 0x500 152 #define INTEVT_SCI0_TXI 0x520 153 #define INTEVT_SCI0_TEI 0x540 154 155 #define INTEVT_WDT 0x560 156 157 #define IS_INTEVT_SCI0(x) ((x == INTEVT_SCI0_ERI) || (x == INTEVT_SCI0_RXI) \ 158 || (x == INTEVT_SCI0_TXI) || (x == INTEVT_SCI0_TEI)) 159 160 #define INTEVT_PRI 0x4a0 /* Periodic interrupt generated by RTC */ 161 162 #if defined(SH4) 163 #define INTEVT_SCIF 0x700 164 #endif 165 166 #endif /* !_SH3_INTR_H_ */ 167