1 /* $NetBSD: cache_sh4.h,v 1.7 2005/06/30 15:14:46 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * SH4: SH7750 SH7750S SH7750R SH7751 SH7751R 41 */ 42 43 #ifndef _SH3_CACHE_SH4_H_ 44 #define _SH3_CACHE_SH4_H_ 45 #include <sh3/devreg.h> 46 #ifdef _KERNEL 47 48 #define SH4_ICACHE_SIZE 8192 49 #define SH4_DCACHE_SIZE 16384 50 #define SH4_CACHE_LINESZ 32 51 52 #define SH4_CCR 0xff00001c 53 #define SH4_CCR_EMODE 0x80000000 54 #define SH4_CCR_IIX 0x00008000 55 #define SH4_CCR_ICI 0x00000800 56 #define SH4_CCR_ICE 0x00000100 57 #define SH4_CCR_OIX 0x00000080 58 #define SH4_CCR_ORA 0x00000020 59 #define SH4_CCR_OCI 0x00000008 60 #define SH4_CCR_CB 0x00000004 61 #define SH4_CCR_WT 0x00000002 62 #define SH4_CCR_OCE 0x00000001 63 64 #define SH4_QACR0 0xff000038 65 #define SH4_QACR1 0xff00003c 66 #define SH4_QACR_AREA_SHIFT 2 67 #define SH4_QACR_AREA_MASK 0x0000001c 68 69 /* I-cache address/data array */ 70 #define SH4_CCIA 0xf0000000 71 /* address specification */ 72 #define CCIA_A 0x00000008 /* associate bit */ 73 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 74 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 75 /* data specification */ 76 #define CCIA_V 0x00000001 77 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 78 79 #define SH4_CCID 0xf1000000 80 /* address specification */ 81 #define CCID_L_SHIFT 2 82 #define CCID_L_MASK 0x1c /* line-size is 32B */ 83 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 84 85 /* D-cache address/data array */ 86 #define SH4_CCDA 0xf4000000 87 /* address specification */ 88 #define CCDA_A 0x00000008 /* associate bit */ 89 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 90 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 256-entries */ 91 /* data specification */ 92 #define CCDA_V 0x00000001 93 #define CCDA_U 0x00000002 94 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 95 96 #define SH4_CCDD 0xf5000000 97 98 /* Store Queue */ 99 #define SH4_SQ 0xe0000000 100 101 /* 102 * cache flush macro for locore level code. 103 */ 104 #define SH4_CACHE_FLUSH() \ 105 do { \ 106 u_int32_t __e, __a; \ 107 \ 108 /* D-cache */ \ 109 for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 110 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 111 (*(__volatile__ u_int32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 112 } \ 113 /* I-cache */ \ 114 for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 115 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 116 (*(__volatile__ u_int32_t *)__a) &= ~(CCIA_V); \ 117 } \ 118 } while(/*CONSTCOND*/0) 119 120 #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH() 121 #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH() 122 #define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH() 123 #define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH() 124 #define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH() 125 126 #ifndef _LOCORE 127 extern void sh4_cache_config(void); 128 #endif 129 #endif /* _KERNEL */ 130 #endif /* !_SH3_CACHE_SH4_H_ */ 131