1 /* $NetBSD: scif.c,v 1.42 2005/12/11 12:18:58 christos Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. Neither the name of the University nor the names of its contributors 78 * may be used to endorse or promote products derived from this software 79 * without specific prior written permission. 80 * 81 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 82 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 84 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 87 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 88 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 89 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 90 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 91 * SUCH DAMAGE. 92 * 93 * @(#)com.c 7.5 (Berkeley) 5/16/91 94 */ 95 96 /* 97 * SH internal serial driver 98 * 99 * This code is derived from both z8530tty.c and com.c 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: scif.c,v 1.42 2005/12/11 12:18:58 christos Exp $"); 104 105 #include "opt_kgdb.h" 106 #include "opt_scif.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/syslog.h> 115 #include <sys/kernel.h> 116 #include <sys/device.h> 117 #include <sys/malloc.h> 118 #include <sys/kgdb.h> 119 120 #include <dev/cons.h> 121 122 #include <sh3/clock.h> 123 #include <sh3/exception.h> 124 #include <sh3/scifreg.h> 125 #include <machine/intr.h> 126 127 #include <sh3/dev/scifvar.h> 128 129 #include "locators.h" 130 131 static void scifstart(struct tty *); 132 static int scifparam(struct tty *, struct termios *); 133 static int kgdb_attached; 134 135 void scifcnprobe(struct consdev *); 136 void scifcninit(struct consdev *); 137 void scifcnputc(dev_t, int); 138 int scifcngetc(dev_t); 139 void scifcnpoolc(dev_t, int); 140 void scif_intr_init(void); 141 int scifintr(void *); 142 143 struct scif_softc { 144 struct device sc_dev; /* boilerplate */ 145 struct tty *sc_tty; 146 void *sc_si; 147 148 struct callout sc_diag_ch; 149 150 #if 0 151 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 152 bus_space_handle_t sc_ioh; /* ISA io handle */ 153 154 int sc_drq; 155 156 int sc_frequency; 157 #endif 158 159 u_int sc_overflows, 160 sc_floods, 161 sc_errors; /* number of retries so far */ 162 u_char sc_status[7]; /* copy of registers */ 163 164 int sc_hwflags; 165 int sc_swflags; 166 u_int sc_fifolen; 167 168 u_int sc_r_hiwat, 169 sc_r_lowat; 170 u_char *volatile sc_rbget, 171 *volatile sc_rbput; 172 volatile u_int sc_rbavail; 173 u_char *sc_rbuf, 174 *sc_ebuf; 175 176 u_char *sc_tba; /* transmit buffer address */ 177 u_int sc_tbc, /* transmit byte count */ 178 sc_heldtbc; 179 180 volatile u_char sc_rx_flags, 181 #define RX_TTY_BLOCKED 0x01 182 #define RX_TTY_OVERFLOWED 0x02 183 #define RX_IBUF_BLOCKED 0x04 184 #define RX_IBUF_OVERFLOWED 0x08 185 #define RX_ANY_BLOCK 0x0f 186 sc_tx_busy, /* working on an output chunk */ 187 sc_tx_done, /* done with one output chunk */ 188 sc_tx_stopped, /* H/W level stop (lost CTS) */ 189 sc_st_check, /* got a status interrupt */ 190 sc_rx_ready; 191 192 volatile u_char sc_heldchange; 193 }; 194 195 /* controller driver configuration */ 196 static int scif_match(struct device *, struct cfdata *, void *); 197 static void scif_attach(struct device *, struct device *, void *); 198 199 void scif_break(struct scif_softc *, int); 200 void scif_iflush(struct scif_softc *); 201 202 #define integrate static inline 203 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 204 void scifsoft(void *); 205 #else 206 #ifndef __NO_SOFT_SERIAL_INTERRUPT 207 void scifsoft(void); 208 #else 209 void scifsoft(void *); 210 #endif 211 #endif 212 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 213 integrate void scif_txsoft(struct scif_softc *, struct tty *); 214 integrate void scif_stsoft(struct scif_softc *, struct tty *); 215 integrate void scif_schedrx(struct scif_softc *); 216 void scifdiag(void *); 217 218 219 #define SCIFUNIT_MASK 0x7ffff 220 #define SCIFDIALOUT_MASK 0x80000 221 222 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 223 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 224 225 /* Macros to clear/set/test flags. */ 226 #define SET(t, f) (t) |= (f) 227 #define CLR(t, f) (t) &= ~(f) 228 #define ISSET(t, f) ((t) & (f)) 229 230 /* Hardware flag masks */ 231 #define SCIF_HW_NOIEN 0x01 232 #define SCIF_HW_FIFO 0x02 233 #define SCIF_HW_FLOW 0x08 234 #define SCIF_HW_DEV_OK 0x20 235 #define SCIF_HW_CONSOLE 0x40 236 #define SCIF_HW_KGDB 0x80 237 238 /* Buffer size for character buffer */ 239 #define SCIF_RING_SIZE 2048 240 241 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 242 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 243 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 244 245 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 246 int scifconscflag = CONMODE; 247 int scifisconsole = 0; 248 249 #ifdef SCIFCN_SPEED 250 unsigned int scifcn_speed = SCIFCN_SPEED; 251 #else 252 unsigned int scifcn_speed = 9600; 253 #endif 254 255 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 256 257 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 258 #ifdef __NO_SOFT_SERIAL_INTERRUPT 259 volatile int scif_softintr_scheduled; 260 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 261 #endif 262 #endif 263 264 u_int scif_rbuf_size = SCIF_RING_SIZE; 265 266 CFATTACH_DECL(scif, sizeof(struct scif_softc), 267 scif_match, scif_attach, NULL, NULL); 268 269 extern struct cfdriver scif_cd; 270 271 static int scif_attached; 272 273 dev_type_open(scifopen); 274 dev_type_close(scifclose); 275 dev_type_read(scifread); 276 dev_type_write(scifwrite); 277 dev_type_ioctl(scifioctl); 278 dev_type_stop(scifstop); 279 dev_type_tty(sciftty); 280 dev_type_poll(scifpoll); 281 282 const struct cdevsw scif_cdevsw = { 283 scifopen, scifclose, scifread, scifwrite, scifioctl, 284 scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY 285 }; 286 287 void InitializeScif (unsigned int); 288 289 /* 290 * following functions are debugging prupose only 291 */ 292 #define CR 0x0D 293 #define USART_ON (unsigned int)~0x08 294 295 void scif_putc(unsigned char); 296 unsigned char scif_getc(void); 297 int ScifErrCheck(void); 298 299 300 /* XXX: uwe 301 * Prepare for bus_spacification. The difference in access widths is 302 * still handled by the magic definitions in scifreg.h 303 */ 304 #define scif_smr_read() SHREG_SCSMR2 305 #define scif_smr_write(v) (SHREG_SCSMR2 = (v)) 306 307 #define scif_brr_read() SHREG_SCBRR2 308 #define scif_brr_write(v) (SHREG_SCBRR2 = (v)) 309 310 #define scif_scr_read() SHREG_SCSCR2 311 #define scif_scr_write(v) (SHREG_SCSCR2 = (v)) 312 313 #define scif_ftdr_write(v) (SHREG_SCFTDR2 = (v)) 314 315 #define scif_ssr_read() SHREG_SCSSR2 316 #define scif_ssr_write(v) (SHREG_SCSSR2 = (v)) 317 318 #define scif_frdr_read() SHREG_SCFRDR2 319 320 #define scif_fcr_read() SHREG_SCFCR2 321 #define scif_fcr_write(v) (SHREG_SCFCR2 = (v)) 322 323 #define scif_fdr_read() SHREG_SCFDR2 324 325 #ifdef SH4 /* additional registers in sh4 */ 326 327 #define scif_sptr_read() SHREG_SCSPTR2 328 #define scif_sptr_write(v) (SHREG_SCSPTR2 = (v)) 329 330 #define scif_lsr_read() SHREG_SCLSR2 331 #define scif_lsr_write(v) (SHREG_SCLSR2 = (v)) 332 333 #endif /* SH4 */ 334 335 336 /* 337 * InitializeScif 338 * : unsigned int bps; 339 * : SCIF(Serial Communication Interface) 340 */ 341 342 void 343 InitializeScif(unsigned int bps) 344 { 345 346 /* Initialize SCR */ 347 scif_scr_write(0x00); 348 349 #if 0 350 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE); 351 #else 352 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST); 353 #endif 354 /* Serial Mode Register */ 355 scif_smr_write(0x00); /* 8bit,NonParity,Even,1Stop */ 356 357 /* Bit Rate Register */ 358 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1); 359 360 /* 361 * wait 2m Sec, because Send/Recv must begin 1 bit period after 362 * BRR is set. 363 */ 364 delay(2000); 365 366 #if 0 367 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE); 368 #else 369 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1); 370 #endif 371 372 /* Send permission, Receive permission ON */ 373 scif_scr_write(SCSCR2_TE | SCSCR2_RE); 374 375 /* Serial Status Register */ 376 scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */ 377 } 378 379 380 /* 381 * scif_putc 382 * : unsigned char c; 383 */ 384 385 void 386 scif_putc(unsigned char c) 387 { 388 389 /* wait for ready */ 390 while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 391 continue; 392 393 /* write send data to send register */ 394 scif_ftdr_write(c); 395 396 /* clear ready flag */ 397 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND)); 398 } 399 400 /* 401 * : ScifErrCheck 402 * 0x80 = error 403 * 0x08 = frame error 404 * 0x04 = parity error 405 */ 406 int 407 ScifErrCheck(void) 408 { 409 410 return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 411 } 412 413 /* 414 * scif_getc 415 */ 416 unsigned char 417 scif_getc(void) 418 { 419 unsigned char c, err_c; 420 #ifdef SH4 421 unsigned short err_c2; 422 #endif 423 424 for (;;) { 425 /* wait for ready */ 426 while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0) 427 continue; 428 429 c = scif_frdr_read(); 430 err_c = scif_ssr_read(); 431 scif_ssr_write(scif_ssr_read() 432 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR)); 433 #ifdef SH4 434 if (CPU_IS_SH4) { 435 err_c2 = scif_lsr_read(); 436 scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER); 437 } 438 #endif 439 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 440 | SCSSR2_PER)) == 0) { 441 #ifdef SH4 442 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 443 #endif 444 return(c); 445 } 446 } 447 448 } 449 450 static int 451 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 452 { 453 454 if (strcmp(cfp->cf_name, "scif") || scif_attached) 455 return 0; 456 457 return 1; 458 } 459 460 static void 461 scif_attach(struct device *parent, struct device *self, void *aux) 462 { 463 struct scif_softc *sc = (struct scif_softc *)self; 464 struct tty *tp; 465 466 scif_attached = 1; 467 468 sc->sc_hwflags = 0; /* XXX */ 469 sc->sc_swflags = 0; /* XXX */ 470 sc->sc_fifolen = 16; 471 472 if (scifisconsole || kgdb_attached) { 473 /* InitializeScif(scifcn_speed); */ 474 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 475 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 476 if (kgdb_attached) { 477 SET(sc->sc_hwflags, SCIF_HW_KGDB); 478 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 479 } else { 480 printf("\n%s: console\n", sc->sc_dev.dv_xname); 481 } 482 } else { 483 InitializeScif(9600); 484 printf("\n"); 485 } 486 487 callout_init(&sc->sc_diag_ch); 488 #ifdef SH4 489 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 490 scifintr, sc); 491 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 492 scifintr, sc); 493 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 494 scifintr, sc); 495 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 496 scifintr, sc); 497 #else 498 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 499 scifintr, sc); 500 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 501 scifintr, sc); 502 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 503 scifintr, sc); 504 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 505 scifintr, sc); 506 #endif 507 508 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 509 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 510 #endif 511 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 512 513 tp = ttymalloc(); 514 tp->t_oproc = scifstart; 515 tp->t_param = scifparam; 516 tp->t_hwiflow = NULL; 517 518 sc->sc_tty = tp; 519 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 520 if (sc->sc_rbuf == NULL) { 521 printf("%s: unable to allocate ring buffer\n", 522 sc->sc_dev.dv_xname); 523 return; 524 } 525 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 526 527 tty_attach(tp); 528 } 529 530 /* 531 * Start or restart transmission. 532 */ 533 static void 534 scifstart(struct tty *tp) 535 { 536 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 537 int s; 538 539 s = spltty(); 540 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 541 goto out; 542 if (sc->sc_tx_stopped) 543 goto out; 544 545 if (tp->t_outq.c_cc <= tp->t_lowat) { 546 if (ISSET(tp->t_state, TS_ASLEEP)) { 547 CLR(tp->t_state, TS_ASLEEP); 548 wakeup(&tp->t_outq); 549 } 550 selwakeup(&tp->t_wsel); 551 if (tp->t_outq.c_cc == 0) 552 goto out; 553 } 554 555 /* Grab the first contiguous region of buffer space. */ 556 { 557 u_char *tba; 558 int tbc; 559 560 tba = tp->t_outq.c_cf; 561 tbc = ndqb(&tp->t_outq, 0); 562 563 (void)splserial(); 564 565 sc->sc_tba = tba; 566 sc->sc_tbc = tbc; 567 } 568 569 SET(tp->t_state, TS_BUSY); 570 sc->sc_tx_busy = 1; 571 572 /* Enable transmit completion interrupts if necessary. */ 573 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 574 575 /* Output the first chunk of the contiguous buffer. */ 576 { 577 int n; 578 int maxchars; 579 int i; 580 581 n = sc->sc_tbc; 582 maxchars = sc->sc_fifolen 583 - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 584 if (n > maxchars) 585 n = maxchars; 586 587 for (i = 0; i < n; i++) { 588 scif_putc(*(sc->sc_tba)); 589 sc->sc_tba++; 590 } 591 sc->sc_tbc -= n; 592 } 593 out: 594 splx(s); 595 return; 596 } 597 598 /* 599 * Set SCIF tty parameters from termios. 600 * XXX - Should just copy the whole termios after 601 * making sure all the changes could be done. 602 */ 603 static int 604 scifparam(struct tty *tp, struct termios *t) 605 { 606 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 607 int ospeed = t->c_ospeed; 608 int s; 609 610 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 611 return (EIO); 612 613 /* Check requested parameters. */ 614 if (ospeed < 0) 615 return (EINVAL); 616 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 617 return (EINVAL); 618 619 /* 620 * For the console, always force CLOCAL and !HUPCL, so that the port 621 * is always active. 622 */ 623 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 624 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 625 SET(t->c_cflag, CLOCAL); 626 CLR(t->c_cflag, HUPCL); 627 } 628 629 /* 630 * If there were no changes, don't do anything. This avoids dropping 631 * input and improves performance when all we did was frob things like 632 * VMIN and VTIME. 633 */ 634 if (tp->t_ospeed == t->c_ospeed && 635 tp->t_cflag == t->c_cflag) 636 return (0); 637 638 #if 0 639 /* XXX (msaitoh) */ 640 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 641 #endif 642 643 s = splserial(); 644 645 /* 646 * Set the flow control pins depending on the current flow control 647 * mode. 648 */ 649 if (ISSET(t->c_cflag, CRTSCTS)) { 650 scif_fcr_write(scif_fcr_read() | SCFCR2_MCE); 651 } else { 652 scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE); 653 } 654 655 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1); 656 657 /* 658 * Set the FIFO threshold based on the receive speed. 659 * 660 * * If it's a low speed, it's probably a mouse or some other 661 * interactive device, so set the threshold low. 662 * * If it's a high speed, trim the trigger level down to prevent 663 * overflows. 664 * * Otherwise set it a bit higher. 665 */ 666 #if 0 667 /* XXX (msaitoh) */ 668 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 669 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 670 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 671 sc->sc_fifo = FIFO_ENABLE | 672 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 673 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 674 else 675 sc->sc_fifo = 0; 676 #endif 677 678 /* And copy to tty. */ 679 tp->t_ispeed = 0; 680 tp->t_ospeed = t->c_ospeed; 681 tp->t_cflag = t->c_cflag; 682 683 if (!sc->sc_heldchange) { 684 if (sc->sc_tx_busy) { 685 sc->sc_heldtbc = sc->sc_tbc; 686 sc->sc_tbc = 0; 687 sc->sc_heldchange = 1; 688 } 689 #if 0 690 /* XXX (msaitoh) */ 691 else 692 scif_loadchannelregs(sc); 693 #endif 694 } 695 696 if (!ISSET(t->c_cflag, CHWFLOW)) { 697 /* Disable the high water mark. */ 698 sc->sc_r_hiwat = 0; 699 sc->sc_r_lowat = 0; 700 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 701 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 702 scif_schedrx(sc); 703 } 704 } else { 705 sc->sc_r_hiwat = scif_rbuf_hiwat; 706 sc->sc_r_lowat = scif_rbuf_lowat; 707 } 708 709 splx(s); 710 711 #ifdef SCIF_DEBUG 712 if (scif_debug) 713 scifstatus(sc, "scifparam "); 714 #endif 715 716 if (!ISSET(t->c_cflag, CHWFLOW)) { 717 if (sc->sc_tx_stopped) { 718 sc->sc_tx_stopped = 0; 719 scifstart(tp); 720 } 721 } 722 723 return (0); 724 } 725 726 void 727 scif_iflush(struct scif_softc *sc) 728 { 729 int i; 730 unsigned char c; 731 732 i = scif_fdr_read() & SCFDR2_RECVCNT; 733 734 while (i > 0) { 735 c = scif_frdr_read(); 736 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR)); 737 i--; 738 } 739 } 740 741 int 742 scifopen(dev_t dev, int flag, int mode, struct lwp *l) 743 { 744 int unit = SCIFUNIT(dev); 745 struct scif_softc *sc; 746 struct tty *tp; 747 int s, s2; 748 int error; 749 750 if (unit >= scif_cd.cd_ndevs) 751 return (ENXIO); 752 sc = scif_cd.cd_devs[unit]; 753 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 754 sc->sc_rbuf == NULL) 755 return (ENXIO); 756 757 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 758 return (ENXIO); 759 760 #ifdef KGDB 761 /* 762 * If this is the kgdb port, no other use is permitted. 763 */ 764 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 765 return (EBUSY); 766 #endif /* KGDB */ 767 768 tp = sc->sc_tty; 769 770 if (ISSET(tp->t_state, TS_ISOPEN) && 771 ISSET(tp->t_state, TS_XCLUDE) && 772 suser(l->l_proc->p_ucred, &l->l_proc->p_acflag) != 0) 773 return (EBUSY); 774 775 s = spltty(); 776 777 /* 778 * Do the following iff this is a first open. 779 */ 780 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 781 struct termios t; 782 783 tp->t_dev = dev; 784 785 s2 = splserial(); 786 787 /* Turn on interrupts. */ 788 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 789 790 splx(s2); 791 792 /* 793 * Initialize the termios status to the defaults. Add in the 794 * sticky bits from TIOCSFLAGS. 795 */ 796 t.c_ispeed = 0; 797 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 798 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 799 t.c_cflag = scifconscflag; 800 } else { 801 t.c_ospeed = TTYDEF_SPEED; 802 t.c_cflag = TTYDEF_CFLAG; 803 } 804 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 805 SET(t.c_cflag, CLOCAL); 806 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 807 SET(t.c_cflag, CRTSCTS); 808 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 809 SET(t.c_cflag, MDMBUF); 810 /* Make sure scifparam() will do something. */ 811 tp->t_ospeed = 0; 812 (void) scifparam(tp, &t); 813 tp->t_iflag = TTYDEF_IFLAG; 814 tp->t_oflag = TTYDEF_OFLAG; 815 tp->t_lflag = TTYDEF_LFLAG; 816 ttychars(tp); 817 ttsetwater(tp); 818 819 s2 = splserial(); 820 821 /* Clear the input ring, and unblock. */ 822 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 823 sc->sc_rbavail = scif_rbuf_size; 824 scif_iflush(sc); 825 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 826 #if 0 827 /* XXX (msaitoh) */ 828 scif_hwiflow(sc); 829 #endif 830 831 #ifdef SCIF_DEBUG 832 if (scif_debug) 833 scifstatus(sc, "scifopen "); 834 #endif 835 836 splx(s2); 837 } 838 839 splx(s); 840 841 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 842 if (error) 843 goto bad; 844 845 error = (*tp->t_linesw->l_open)(dev, tp); 846 if (error) 847 goto bad; 848 849 return (0); 850 851 bad: 852 853 return (error); 854 } 855 856 int 857 scifclose(dev_t dev, int flag, int mode, struct lwp *l) 858 { 859 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 860 struct tty *tp = sc->sc_tty; 861 862 /* XXX This is for cons.c. */ 863 if (!ISSET(tp->t_state, TS_ISOPEN)) 864 return (0); 865 866 (*tp->t_linesw->l_close)(tp, flag); 867 ttyclose(tp); 868 869 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 870 return (0); 871 872 return (0); 873 } 874 875 int 876 scifread(dev_t dev, struct uio *uio, int flag) 877 { 878 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 879 struct tty *tp = sc->sc_tty; 880 881 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 882 } 883 884 int 885 scifwrite(dev_t dev, struct uio *uio, int flag) 886 { 887 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 888 struct tty *tp = sc->sc_tty; 889 890 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 891 } 892 893 int 894 scifpoll(dev_t dev, int events, struct lwp *l) 895 { 896 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 897 struct tty *tp = sc->sc_tty; 898 899 return ((*tp->t_linesw->l_poll)(tp, events, l)); 900 } 901 902 struct tty * 903 sciftty(dev_t dev) 904 { 905 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 906 struct tty *tp = sc->sc_tty; 907 908 return (tp); 909 } 910 911 int 912 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 913 { 914 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 915 struct tty *tp = sc->sc_tty; 916 int error; 917 int s; 918 919 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 920 return (EIO); 921 922 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 923 if (error != EPASSTHROUGH) 924 return (error); 925 926 error = ttioctl(tp, cmd, data, flag, l); 927 if (error != EPASSTHROUGH) 928 return (error); 929 930 error = 0; 931 932 s = splserial(); 933 934 switch (cmd) { 935 case TIOCSBRK: 936 scif_break(sc, 1); 937 break; 938 939 case TIOCCBRK: 940 scif_break(sc, 0); 941 break; 942 943 case TIOCGFLAGS: 944 *(int *)data = sc->sc_swflags; 945 break; 946 947 case TIOCSFLAGS: 948 error = suser(l->l_proc->p_ucred, &l->l_proc->p_acflag); 949 if (error) 950 break; 951 sc->sc_swflags = *(int *)data; 952 break; 953 954 default: 955 error = EPASSTHROUGH; 956 break; 957 } 958 959 splx(s); 960 961 return (error); 962 } 963 964 integrate void 965 scif_schedrx(struct scif_softc *sc) 966 { 967 968 sc->sc_rx_ready = 1; 969 970 /* Wake up the poller. */ 971 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 972 softintr_schedule(sc->sc_si); 973 #else 974 #ifndef __NO_SOFT_SERIAL_INTERRUPT 975 setsoftserial(); 976 #else 977 if (!scif_softintr_scheduled) { 978 scif_softintr_scheduled = 1; 979 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 980 } 981 #endif 982 #endif 983 } 984 985 void 986 scif_break(struct scif_softc *sc, int onoff) 987 { 988 989 if (onoff) 990 scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE); 991 else 992 scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE); 993 994 #if 0 /* XXX */ 995 if (!sc->sc_heldchange) { 996 if (sc->sc_tx_busy) { 997 sc->sc_heldtbc = sc->sc_tbc; 998 sc->sc_tbc = 0; 999 sc->sc_heldchange = 1; 1000 } else 1001 scif_loadchannelregs(sc); 1002 } 1003 #endif 1004 } 1005 1006 /* 1007 * Stop output, e.g., for ^S or output flush. 1008 */ 1009 void 1010 scifstop(struct tty *tp, int flag) 1011 { 1012 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1013 int s; 1014 1015 s = splserial(); 1016 if (ISSET(tp->t_state, TS_BUSY)) { 1017 /* Stop transmitting at the next chunk. */ 1018 sc->sc_tbc = 0; 1019 sc->sc_heldtbc = 0; 1020 if (!ISSET(tp->t_state, TS_TTSTOP)) 1021 SET(tp->t_state, TS_FLUSH); 1022 } 1023 splx(s); 1024 } 1025 1026 void 1027 scif_intr_init() 1028 { 1029 /* XXX */ 1030 } 1031 1032 void 1033 scifdiag(void *arg) 1034 { 1035 struct scif_softc *sc = arg; 1036 int overflows, floods; 1037 int s; 1038 1039 s = splserial(); 1040 overflows = sc->sc_overflows; 1041 sc->sc_overflows = 0; 1042 floods = sc->sc_floods; 1043 sc->sc_floods = 0; 1044 sc->sc_errors = 0; 1045 splx(s); 1046 1047 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1048 sc->sc_dev.dv_xname, 1049 overflows, overflows == 1 ? "" : "s", 1050 floods, floods == 1 ? "" : "s"); 1051 } 1052 1053 integrate void 1054 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1055 { 1056 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1057 u_char *get, *end; 1058 u_int cc, scc; 1059 u_char ssr2; 1060 int code; 1061 int s; 1062 1063 end = sc->sc_ebuf; 1064 get = sc->sc_rbget; 1065 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1066 1067 if (cc == scif_rbuf_size) { 1068 sc->sc_floods++; 1069 if (sc->sc_errors++ == 0) 1070 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1071 } 1072 1073 while (cc) { 1074 code = get[0]; 1075 ssr2 = get[1]; 1076 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1077 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1078 SET(code, TTY_FE); 1079 if (ISSET(ssr2, SCSSR2_PER)) 1080 SET(code, TTY_PE); 1081 } 1082 if ((*rint)(code, tp) == -1) { 1083 /* 1084 * The line discipline's buffer is out of space. 1085 */ 1086 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1087 /* 1088 * We're either not using flow control, or the 1089 * line discipline didn't tell us to block for 1090 * some reason. Either way, we have no way to 1091 * know when there's more space available, so 1092 * just drop the rest of the data. 1093 */ 1094 get += cc << 1; 1095 if (get >= end) 1096 get -= scif_rbuf_size << 1; 1097 cc = 0; 1098 } else { 1099 /* 1100 * Don't schedule any more receive processing 1101 * until the line discipline tells us there's 1102 * space available (through scifhwiflow()). 1103 * Leave the rest of the data in the input 1104 * buffer. 1105 */ 1106 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1107 } 1108 break; 1109 } 1110 get += 2; 1111 if (get >= end) 1112 get = sc->sc_rbuf; 1113 cc--; 1114 } 1115 1116 if (cc != scc) { 1117 sc->sc_rbget = get; 1118 s = splserial(); 1119 cc = sc->sc_rbavail += scc - cc; 1120 /* Buffers should be ok again, release possible block. */ 1121 if (cc >= sc->sc_r_lowat) { 1122 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1123 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1124 scif_scr_write(scif_scr_read() | SCSCR2_RIE); 1125 } 1126 #if 0 1127 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1128 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1129 scif_hwiflow(sc); 1130 } 1131 #endif 1132 } 1133 splx(s); 1134 } 1135 } 1136 1137 integrate void 1138 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1139 { 1140 1141 CLR(tp->t_state, TS_BUSY); 1142 if (ISSET(tp->t_state, TS_FLUSH)) 1143 CLR(tp->t_state, TS_FLUSH); 1144 else 1145 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1146 (*tp->t_linesw->l_start)(tp); 1147 } 1148 1149 integrate void 1150 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1151 { 1152 #if 0 1153 /* XXX (msaitoh) */ 1154 u_char msr, delta; 1155 int s; 1156 1157 s = splserial(); 1158 msr = sc->sc_msr; 1159 delta = sc->sc_msr_delta; 1160 sc->sc_msr_delta = 0; 1161 splx(s); 1162 1163 if (ISSET(delta, sc->sc_msr_dcd)) { 1164 /* 1165 * Inform the tty layer that carrier detect changed. 1166 */ 1167 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1168 } 1169 1170 if (ISSET(delta, sc->sc_msr_cts)) { 1171 /* Block or unblock output according to flow control. */ 1172 if (ISSET(msr, sc->sc_msr_cts)) { 1173 sc->sc_tx_stopped = 0; 1174 (*tp->t_linesw->l_start)(tp); 1175 } else { 1176 sc->sc_tx_stopped = 1; 1177 } 1178 } 1179 1180 #ifdef SCIF_DEBUG 1181 if (scif_debug) 1182 scifstatus(sc, "scif_stsoft"); 1183 #endif 1184 #endif 1185 } 1186 1187 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1188 void 1189 scifsoft(void *arg) 1190 { 1191 struct scif_softc *sc = arg; 1192 struct tty *tp; 1193 1194 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1195 return; 1196 1197 { 1198 #else 1199 void 1200 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1201 scifsoft() 1202 #else 1203 scifsoft(void *arg) 1204 #endif 1205 { 1206 struct scif_softc *sc; 1207 struct tty *tp; 1208 int unit; 1209 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1210 int s; 1211 1212 s = splsoftserial(); 1213 scif_softintr_scheduled = 0; 1214 #endif 1215 1216 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1217 sc = scif_cd.cd_devs[unit]; 1218 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1219 continue; 1220 1221 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1222 continue; 1223 1224 tp = sc->sc_tty; 1225 if (tp == NULL) 1226 continue; 1227 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1228 continue; 1229 #endif 1230 tp = sc->sc_tty; 1231 1232 if (sc->sc_rx_ready) { 1233 sc->sc_rx_ready = 0; 1234 scif_rxsoft(sc, tp); 1235 } 1236 1237 #if 0 1238 if (sc->sc_st_check) { 1239 sc->sc_st_check = 0; 1240 scif_stsoft(sc, tp); 1241 } 1242 #endif 1243 1244 if (sc->sc_tx_done) { 1245 sc->sc_tx_done = 0; 1246 scif_txsoft(sc, tp); 1247 } 1248 } 1249 1250 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1251 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1252 splx(s); 1253 #endif 1254 #endif 1255 } 1256 1257 int 1258 scifintr(void *arg) 1259 { 1260 struct scif_softc *sc = arg; 1261 u_char *put, *end; 1262 u_int cc; 1263 u_short ssr2; 1264 int count; 1265 1266 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1267 return (0); 1268 1269 end = sc->sc_ebuf; 1270 put = sc->sc_rbput; 1271 cc = sc->sc_rbavail; 1272 1273 do { 1274 ssr2 = scif_ssr_read(); 1275 if (ISSET(ssr2, SCSSR2_BRK)) { 1276 scif_ssr_write(scif_ssr_read() 1277 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR)); 1278 #ifdef DDB 1279 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1280 console_debugger(); 1281 } 1282 #endif /* DDB */ 1283 #ifdef KGDB 1284 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1285 kgdb_connect(1); 1286 } 1287 #endif /* KGDB */ 1288 } 1289 count = scif_fdr_read() & SCFDR2_RECVCNT; 1290 if (count != 0) { 1291 for (;;) { 1292 u_char c = scif_frdr_read(); 1293 u_char err = (u_char)(scif_ssr_read() & 0x00ff); 1294 1295 scif_ssr_write(scif_ssr_read() 1296 & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR)); 1297 #ifdef SH4 1298 if (CPU_IS_SH4) 1299 scif_lsr_write(scif_lsr_read() 1300 & ~SCLSR2_ORER); 1301 #endif 1302 if ((cc > 0) && (count > 0)) { 1303 put[0] = c; 1304 put[1] = err; 1305 put += 2; 1306 if (put >= end) 1307 put = sc->sc_rbuf; 1308 cc--; 1309 count--; 1310 } else 1311 break; 1312 } 1313 1314 /* 1315 * Current string of incoming characters ended because 1316 * no more data was available or we ran out of space. 1317 * Schedule a receive event if any data was received. 1318 * If we're out of space, turn off receive interrupts. 1319 */ 1320 sc->sc_rbput = put; 1321 sc->sc_rbavail = cc; 1322 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1323 sc->sc_rx_ready = 1; 1324 1325 /* 1326 * See if we are in danger of overflowing a buffer. If 1327 * so, use hardware flow control to ease the pressure. 1328 */ 1329 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1330 cc < sc->sc_r_hiwat) { 1331 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1332 #if 0 1333 scif_hwiflow(sc); 1334 #endif 1335 } 1336 1337 /* 1338 * If we're out of space, disable receive interrupts 1339 * until the queue has drained a bit. 1340 */ 1341 if (!cc) { 1342 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1343 scif_scr_write(scif_scr_read() & ~SCSCR2_RIE); 1344 } 1345 } else { 1346 if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) { 1347 scif_scr_write(scif_scr_read() 1348 & ~(SCSCR2_TIE | SCSCR2_RIE)); 1349 delay(10); 1350 scif_scr_write(scif_scr_read() 1351 | SCSCR2_TIE | SCSCR2_RIE); 1352 continue; 1353 } 1354 } 1355 } while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)); 1356 1357 #if 0 1358 msr = bus_space_read_1(iot, ioh, scif_msr); 1359 delta = msr ^ sc->sc_msr; 1360 sc->sc_msr = msr; 1361 if (ISSET(delta, sc->sc_msr_mask)) { 1362 SET(sc->sc_msr_delta, delta); 1363 1364 /* 1365 * Pulse-per-second clock signal on edge of DCD? 1366 */ 1367 if (ISSET(delta, sc->sc_ppsmask)) { 1368 struct timeval tv; 1369 if (ISSET(msr, sc->sc_ppsmask) == 1370 sc->sc_ppsassert) { 1371 /* XXX nanotime() */ 1372 microtime(&tv); 1373 TIMEVAL_TO_TIMESPEC(&tv, 1374 &sc->ppsinfo.assert_timestamp); 1375 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1376 timespecadd(&sc->ppsinfo.assert_timestamp, 1377 &sc->ppsparam.assert_offset, 1378 &sc->ppsinfo.assert_timestamp); 1379 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1380 } 1381 1382 #ifdef PPS_SYNC 1383 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1384 hardpps(&tv, tv.tv_usec); 1385 #endif 1386 sc->ppsinfo.assert_sequence++; 1387 sc->ppsinfo.current_mode = 1388 sc->ppsparam.mode; 1389 1390 } else if (ISSET(msr, sc->sc_ppsmask) == 1391 sc->sc_ppsclear) { 1392 /* XXX nanotime() */ 1393 microtime(&tv); 1394 TIMEVAL_TO_TIMESPEC(&tv, 1395 &sc->ppsinfo.clear_timestamp); 1396 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1397 timespecadd(&sc->ppsinfo.clear_timestamp, 1398 &sc->ppsparam.clear_offset, 1399 &sc->ppsinfo.clear_timestamp); 1400 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1401 } 1402 1403 #ifdef PPS_SYNC 1404 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1405 hardpps(&tv, tv.tv_usec); 1406 #endif 1407 sc->ppsinfo.clear_sequence++; 1408 sc->ppsinfo.current_mode = 1409 sc->ppsparam.mode; 1410 } 1411 } 1412 1413 /* 1414 * Stop output immediately if we lose the output 1415 * flow control signal or carrier detect. 1416 */ 1417 if (ISSET(~msr, sc->sc_msr_mask)) { 1418 sc->sc_tbc = 0; 1419 sc->sc_heldtbc = 0; 1420 #ifdef SCIF_DEBUG 1421 if (scif_debug) 1422 scifstatus(sc, "scifintr "); 1423 #endif 1424 } 1425 1426 sc->sc_st_check = 1; 1427 } 1428 #endif 1429 1430 /* 1431 * Done handling any receive interrupts. See if data can be 1432 * transmitted as well. Schedule tx done event if no data left 1433 * and tty was marked busy. 1434 */ 1435 if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1436 /* 1437 * If we've delayed a parameter change, do it now, and restart 1438 * output. 1439 */ 1440 if (sc->sc_heldchange) { 1441 sc->sc_heldchange = 0; 1442 sc->sc_tbc = sc->sc_heldtbc; 1443 sc->sc_heldtbc = 0; 1444 } 1445 1446 /* Output the next chunk of the contiguous buffer, if any. */ 1447 if (sc->sc_tbc > 0) { 1448 int n; 1449 int maxchars; 1450 int i; 1451 1452 n = sc->sc_tbc; 1453 maxchars = sc->sc_fifolen - 1454 ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 1455 if (n > maxchars) 1456 n = maxchars; 1457 1458 for (i = 0; i < n; i++) { 1459 scif_putc(*(sc->sc_tba)); 1460 sc->sc_tba++; 1461 } 1462 sc->sc_tbc -= n; 1463 } else { 1464 /* Disable transmit completion interrupts if necessary. */ 1465 #if 0 1466 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1467 #endif 1468 scif_scr_write(scif_scr_read() & ~SCSCR2_TIE); 1469 1470 if (sc->sc_tx_busy) { 1471 sc->sc_tx_busy = 0; 1472 sc->sc_tx_done = 1; 1473 } 1474 } 1475 } 1476 1477 /* Wake up the poller. */ 1478 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1479 softintr_schedule(sc->sc_si); 1480 #else 1481 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1482 setsoftserial(); 1483 #else 1484 if (!scif_softintr_scheduled) { 1485 scif_softintr_scheduled = 1; 1486 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1487 } 1488 #endif 1489 #endif 1490 1491 #if NRND > 0 && defined(RND_SCIF) 1492 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1493 #endif 1494 1495 return (1); 1496 } 1497 1498 void 1499 scifcnprobe(struct consdev *cp) 1500 { 1501 int maj; 1502 1503 /* locate the major number */ 1504 maj = cdevsw_lookup_major(&scif_cdevsw); 1505 1506 /* Initialize required fields. */ 1507 cp->cn_dev = makedev(maj, 0); 1508 #ifdef SCIFCONSOLE 1509 cp->cn_pri = CN_REMOTE; 1510 #else 1511 cp->cn_pri = CN_NORMAL; 1512 #endif 1513 } 1514 1515 void 1516 scifcninit(struct consdev *cp) 1517 { 1518 1519 InitializeScif(scifcn_speed); 1520 scifisconsole = 1; 1521 } 1522 1523 int 1524 scifcngetc(dev_t dev) 1525 { 1526 int c; 1527 int s; 1528 1529 s = splserial(); 1530 c = scif_getc(); 1531 splx(s); 1532 1533 return (c); 1534 } 1535 1536 void 1537 scifcnputc(dev_t dev, int c) 1538 { 1539 int s; 1540 1541 s = splserial(); 1542 scif_putc((u_char)c); 1543 splx(s); 1544 } 1545 1546 #ifdef KGDB 1547 int 1548 scif_kgdb_init() 1549 { 1550 1551 if (strcmp(kgdb_devname, "scif") != 0) 1552 return (1); 1553 1554 if (scifisconsole) 1555 return (1); /* can't share with console */ 1556 1557 InitializeScif(kgdb_rate); 1558 1559 kgdb_attach((int (*)(void *))scifcngetc, 1560 (void (*)(void *, int))scifcnputc, NULL); 1561 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1562 kgdb_attached = 1; 1563 1564 return (0); 1565 } 1566 #endif /* KGDB */ 1567