1 /* $NetBSD: scif.c,v 1.9 2000/03/27 16:24:08 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by the University of 80 * California, Berkeley and its contributors. 81 * 4. Neither the name of the University nor the names of its contributors 82 * may be used to endorse or promote products derived from this software 83 * without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 86 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 91 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 * 97 * @(#)com.c 7.5 (Berkeley) 5/16/91 98 */ 99 100 /* 101 * SH internal serial driver 102 * 103 * This code is derived from both z8530tty.c and com.c 104 */ 105 106 #include "opt_pclock.h" 107 #include "opt_scif.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/tty.h> 112 #include <sys/proc.h> 113 #include <sys/conf.h> 114 #include <sys/file.h> 115 #include <sys/syslog.h> 116 #include <sys/kernel.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 120 #include <dev/cons.h> 121 122 #include <machine/cpu.h> 123 #include <sh3/scifreg.h> 124 #include <sh3/tmureg.h> 125 126 #include <machine/shbvar.h> 127 128 static void scifstart __P((struct tty *)); 129 static int scifparam __P((struct tty *, struct termios *)); 130 131 void scifcnprobe __P((struct consdev *)); 132 void scifcninit __P((struct consdev *)); 133 void scifcnputc __P((dev_t, int)); 134 int scifcngetc __P((dev_t)); 135 void scifcnpoolc __P((dev_t, int)); 136 void scif_intr_init __P((void)); 137 int scifintr __P((void *)); 138 139 struct scif_softc { 140 struct device sc_dev; /* boilerplate */ 141 struct tty *sc_tty; 142 void *sc_ih; 143 144 struct callout sc_diag_ch; 145 146 #if 0 147 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 148 bus_space_handle_t sc_ioh; /* ISA io handle */ 149 150 int sc_drq; 151 152 int sc_frequency; 153 #endif 154 155 u_int sc_overflows, 156 sc_floods, 157 sc_errors; /* number of retries so far */ 158 u_char sc_status[7]; /* copy of registers */ 159 160 int sc_hwflags; 161 int sc_swflags; 162 u_int sc_fifolen; 163 164 u_int sc_r_hiwat, 165 sc_r_lowat; 166 u_char *volatile sc_rbget, 167 *volatile sc_rbput; 168 volatile u_int sc_rbavail; 169 u_char *sc_rbuf, 170 *sc_ebuf; 171 172 u_char *sc_tba; /* transmit buffer address */ 173 u_int sc_tbc, /* transmit byte count */ 174 sc_heldtbc; 175 176 volatile u_char sc_rx_flags, 177 #define RX_TTY_BLOCKED 0x01 178 #define RX_TTY_OVERFLOWED 0x02 179 #define RX_IBUF_BLOCKED 0x04 180 #define RX_IBUF_OVERFLOWED 0x08 181 #define RX_ANY_BLOCK 0x0f 182 sc_tx_busy, /* working on an output chunk */ 183 sc_tx_done, /* done with one output chunk */ 184 sc_tx_stopped, /* H/W level stop (lost CTS) */ 185 sc_st_check, /* got a status interrupt */ 186 sc_rx_ready; 187 188 volatile u_char sc_heldchange; 189 }; 190 191 /* controller driver configuration */ 192 static int scif_match __P((struct device *, struct cfdata *, void *)); 193 static void scif_attach __P((struct device *, struct device *, void *)); 194 195 void scif_break __P((struct scif_softc *, int)); 196 void scif_iflush __P((struct scif_softc *)); 197 198 #define integrate static inline 199 #ifdef __GENERIC_SOFT_INTERRUPTS 200 void scifsoft __P((void *)); 201 #else 202 #ifndef __NO_SOFT_SERIAL_INTERRUPT 203 void scifsoft __P((void)); 204 #else 205 void scifsoft __P((void *)); 206 #endif 207 #endif 208 integrate void scif_rxsoft __P((struct scif_softc *, struct tty *)); 209 integrate void scif_txsoft __P((struct scif_softc *, struct tty *)); 210 integrate void scif_stsoft __P((struct scif_softc *, struct tty *)); 211 integrate void scif_schedrx __P((struct scif_softc *)); 212 void scifdiag __P((void *)); 213 214 215 #define SCIFUNIT_MASK 0x7ffff 216 #define SCIFDIALOUT_MASK 0x80000 217 218 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 219 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 220 221 /* Macros to clear/set/test flags. */ 222 #define SET(t, f) (t) |= (f) 223 #define CLR(t, f) (t) &= ~(f) 224 #define ISSET(t, f) ((t) & (f)) 225 226 /* Hardware flag masks */ 227 #define SCIF_HW_NOIEN 0x01 228 #define SCIF_HW_FIFO 0x02 229 #define SCIF_HW_FLOW 0x08 230 #define SCIF_HW_DEV_OK 0x20 231 #define SCIF_HW_CONSOLE 0x40 232 #define SCIF_HW_KGDB 0x80 233 234 /* Buffer size for character buffer */ 235 #define SCIF_RING_SIZE 2048 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 239 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 240 241 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 242 int scifconscflag = CONMODE; 243 int scifisconsole = 0; 244 245 #ifdef SCIFCN_SPEED 246 unsigned int scifcn_speed = SCIFCN_SPEED; 247 #else 248 unsigned int scifcn_speed = 9600; 249 #endif 250 251 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 252 253 #ifndef __GENERIC_SOFT_INTERRUPTS 254 #ifdef __NO_SOFT_SERIAL_INTERRUPT 255 volatile int scif_softintr_scheduled; 256 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 257 #endif 258 #endif 259 260 u_int scif_rbuf_size = SCIF_RING_SIZE; 261 262 struct cfattach scif_ca = { 263 sizeof(struct scif_softc), scif_match, scif_attach 264 }; 265 266 extern struct cfdriver scif_cd; 267 268 cdev_decl(scif); 269 270 void InitializeScif __P((unsigned int)); 271 272 /* 273 * following functions are debugging prupose only 274 */ 275 #define CR 0x0D 276 #define USART_ON (unsigned int)~0x08 277 278 static void WaitFor __P((int)); 279 void PutcScif __P((unsigned char)); 280 void PutStrScif __P((unsigned char *)); 281 int ScifErrCheck __P((void)); 282 unsigned char GetcScif __P((void)); 283 int GetStrScif __P((unsigned char *, int)); 284 285 /* 286 * WaitFor 287 * : int mSec; 288 */ 289 static void 290 WaitFor(mSec) 291 int mSec; 292 { 293 294 /* Disable Under Flow interrupt, rising edge, 1/4 */ 295 SHREG_TCR2 = 0x0000; 296 297 /* Set counter value (count down with 4 KHz) */ 298 SHREG_TCNT2 = mSec * 4; 299 300 /* start Channel2 */ 301 SHREG_TSTR |= TSTR_STR2; 302 303 /* wait for under flag ON of channel2 */ 304 while ((SHREG_TCR2 & TCR_UNF) == 0) 305 ; 306 307 /* stop channel2 */ 308 SHREG_TSTR &= ~TSTR_STR2; 309 } 310 311 /* 312 * InitializeScif 313 * : unsigned int bps; 314 * : SCIF(Serial Communication Interface) 315 */ 316 317 void 318 InitializeScif(bps) 319 unsigned int bps; 320 { 321 322 /* Initialize SCR */ 323 SHREG_SCSCR2 = 0x00; 324 325 #if 0 326 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE; 327 #else 328 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; 329 #endif 330 /* Serial Mode Register */ 331 SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ 332 333 /* Bit Rate Register */ 334 SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) - 1; 335 336 /* 337 * wait 1mSec, because Send/Recv must begin 1 bit period after 338 * BRR is set. 339 */ 340 WaitFor(1); 341 342 #if 0 343 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE; 344 #else 345 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1; 346 #endif 347 348 /* Send permission, Recieve permission ON */ 349 SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; 350 351 /* Serial Status Register */ 352 SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ 353 } 354 355 356 /* 357 * PutcScif 358 * : unsigned char c; 359 */ 360 361 void 362 PutcScif(c) 363 unsigned char c; 364 { 365 366 /* wait for ready */ 367 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 368 ; 369 370 /* write send data to send register */ 371 SHREG_SCFTDR2 = c; 372 373 /* clear ready flag */ 374 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 375 376 if (c == '\n') { 377 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 378 ; 379 380 SHREG_SCFTDR2 = '\r'; 381 382 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 383 } 384 } 385 386 /* 387 * PutStrScif 388 * : unsigned char *s; 389 */ 390 void 391 PutStrScif(s) 392 unsigned char *s; 393 { 394 395 while (*s) 396 PutcScif(*s++); 397 } 398 399 /* 400 * : ScifErrCheck 401 * 0x80 = error 402 * 0x08 = frame error 403 * 0x04 = parity error 404 */ 405 int 406 ScifErrCheck(void) 407 { 408 409 return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 410 } 411 412 /* 413 * GetcScif 414 */ 415 #if 0 416 /* Old code */ 417 unsigned char 418 GetcScif(void) 419 { 420 unsigned char c, err_c; 421 422 while (((err_c = SHREG_SCSSR2) 423 & (SCSSR2_RDF | SCSSR2_ER | SCSSR2_FER | SCSSR2_PER | SCSSR2_DR)) == 0) 424 ; 425 if ((err_c & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)) != 0) 426 return(err_c |= 0x80); 427 428 c = SHREG_SCFRDR2; 429 430 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 431 432 return(c); 433 } 434 #else 435 unsigned char 436 GetcScif(void) 437 { 438 unsigned char c, err_c; 439 440 /* wait for ready */ 441 while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0) 442 ; 443 err_c = SHREG_SCSSR2; 444 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) != 0) 445 return(err_c |= 0x80); 446 447 c = SHREG_SCFRDR2; 448 449 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR); 450 451 return(c); 452 } 453 #endif 454 455 /* 456 * GetStrScif 457 * : unsigned char *s; 458 * : int size; 459 */ 460 int 461 GetStrScif(s, size) 462 unsigned char *s; 463 int size; 464 { 465 466 for (; size ; size--) { 467 *s = GetcScif(); 468 if (*s & 0x80) 469 return -1; 470 if (*s == CR) { 471 *s = 0; 472 break; 473 } 474 s++; 475 } 476 if (size == 0) 477 *s = 0; 478 return 0; 479 } 480 481 #if 0 482 #define SCIF_MAX_UNITS 2 483 #else 484 #define SCIF_MAX_UNITS 1 485 #endif 486 487 488 static int 489 scif_match(parent, cfp, aux) 490 struct device *parent; 491 struct cfdata *cfp; 492 void *aux; 493 { 494 struct shb_attach_args *sa = aux; 495 496 if (strcmp(cfp->cf_driver->cd_name, "scif") 497 || cfp->cf_unit >= SCIF_MAX_UNITS) 498 return 0; 499 500 sa->ia_iosize = 0x10; 501 return 1; 502 } 503 504 static void 505 scif_attach(parent, self, aux) 506 struct device *parent, *self; 507 void *aux; 508 { 509 struct scif_softc *sc = (struct scif_softc *)self; 510 struct tty *tp; 511 int irq; 512 struct shb_attach_args *ia = aux; 513 514 sc->sc_hwflags = 0; /* XXX */ 515 sc->sc_swflags = 0; /* XXX */ 516 sc->sc_fifolen = 16; 517 518 irq = ia->ia_irq; 519 520 if (scifisconsole) { 521 /* InitializeScif(scifcn_speed); */ 522 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 523 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 524 printf("\n%s: console\n", sc->sc_dev.dv_xname); 525 } else { 526 InitializeScif(9600); 527 printf("\n"); 528 } 529 530 callout_init(&sc->sc_diag_ch); 531 532 #if 0 533 if (irq != IRQUNK) { 534 sc->sc_ih = shb_intr_establish(irq, 535 IST_EDGE, IPL_SERIAL, scifintr, sc); 536 } 537 #else 538 if (irq != IRQUNK) { 539 sc->sc_ih = shb_intr_establish(SCIF_IRQ, 540 IST_EDGE, IPL_SERIAL, scifintr, sc); 541 } 542 #endif 543 544 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 545 546 tp = ttymalloc(); 547 tp->t_oproc = scifstart; 548 tp->t_param = scifparam; 549 tp->t_hwiflow = NULL; 550 551 sc->sc_tty = tp; 552 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 553 if (sc->sc_rbuf == NULL) { 554 printf("%s: unable to allocate ring buffer\n", 555 sc->sc_dev.dv_xname); 556 return; 557 } 558 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 559 560 tty_attach(tp); 561 } 562 563 /* 564 * Start or restart transmission. 565 */ 566 static void 567 scifstart(tp) 568 struct tty *tp; 569 { 570 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 571 int s; 572 573 s = spltty(); 574 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 575 goto out; 576 if (sc->sc_tx_stopped) 577 goto out; 578 579 if (tp->t_outq.c_cc <= tp->t_lowat) { 580 if (ISSET(tp->t_state, TS_ASLEEP)) { 581 CLR(tp->t_state, TS_ASLEEP); 582 wakeup(&tp->t_outq); 583 } 584 selwakeup(&tp->t_wsel); 585 if (tp->t_outq.c_cc == 0) 586 goto out; 587 } 588 589 /* Grab the first contiguous region of buffer space. */ 590 { 591 u_char *tba; 592 int tbc; 593 594 tba = tp->t_outq.c_cf; 595 tbc = ndqb(&tp->t_outq, 0); 596 597 (void)splserial(); 598 599 sc->sc_tba = tba; 600 sc->sc_tbc = tbc; 601 } 602 603 SET(tp->t_state, TS_BUSY); 604 sc->sc_tx_busy = 1; 605 606 /* Enable transmit completion interrupts if necessary. */ 607 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 608 609 /* Output the first chunk of the contiguous buffer. */ 610 { 611 int n; 612 int max; 613 int i; 614 615 n = sc->sc_tbc; 616 max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 617 if (n > max) 618 n = max; 619 620 for (i = 0; i < n; i++) { 621 PutcScif(*(sc->sc_tba)); 622 sc->sc_tba++; 623 } 624 sc->sc_tbc -= n; 625 } 626 out: 627 splx(s); 628 return; 629 } 630 631 /* 632 * Set SCIF tty parameters from termios. 633 * XXX - Should just copy the whole termios after 634 * making sure all the changes could be done. 635 */ 636 static int 637 scifparam(tp, t) 638 struct tty *tp; 639 struct termios *t; 640 { 641 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 642 int ospeed = t->c_ospeed; 643 int s; 644 645 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 646 return (EIO); 647 648 /* Check requested parameters. */ 649 if (ospeed < 0) 650 return (EINVAL); 651 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 652 return (EINVAL); 653 654 /* 655 * For the console, always force CLOCAL and !HUPCL, so that the port 656 * is always active. 657 */ 658 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 659 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 660 SET(t->c_cflag, CLOCAL); 661 CLR(t->c_cflag, HUPCL); 662 } 663 664 /* 665 * If there were no changes, don't do anything. This avoids dropping 666 * input and improves performance when all we did was frob things like 667 * VMIN and VTIME. 668 */ 669 if (tp->t_ospeed == t->c_ospeed && 670 tp->t_cflag == t->c_cflag) 671 return (0); 672 673 #if 0 674 /* XXX (msaitoh) */ 675 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 676 #endif 677 678 s = splserial(); 679 680 /* 681 * Set the flow control pins depending on the current flow control 682 * mode. 683 */ 684 if (ISSET(t->c_cflag, CRTSCTS)) { 685 SHREG_SCFCR2 |= SCFCR2_MCE; 686 } else { 687 SHREG_SCFCR2 &= ~SCFCR2_MCE; 688 } 689 690 SHREG_SCBRR2 = divrnd(PCLOCK, 32 * ospeed) -1; 691 692 /* 693 * Set the FIFO threshold based on the receive speed. 694 * 695 * * If it's a low speed, it's probably a mouse or some other 696 * interactive device, so set the threshold low. 697 * * If it's a high speed, trim the trigger level down to prevent 698 * overflows. 699 * * Otherwise set it a bit higher. 700 */ 701 #if 0 702 /* XXX (msaitoh) */ 703 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 704 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 705 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 706 sc->sc_fifo = FIFO_ENABLE | 707 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 708 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 709 else 710 sc->sc_fifo = 0; 711 #endif 712 713 /* And copy to tty. */ 714 tp->t_ispeed = 0; 715 tp->t_ospeed = t->c_ospeed; 716 tp->t_cflag = t->c_cflag; 717 718 if (!sc->sc_heldchange) { 719 if (sc->sc_tx_busy) { 720 sc->sc_heldtbc = sc->sc_tbc; 721 sc->sc_tbc = 0; 722 sc->sc_heldchange = 1; 723 } 724 #if 0 725 /* XXX (msaitoh) */ 726 else 727 scif_loadchannelregs(sc); 728 #endif 729 } 730 731 if (!ISSET(t->c_cflag, CHWFLOW)) { 732 /* Disable the high water mark. */ 733 sc->sc_r_hiwat = 0; 734 sc->sc_r_lowat = 0; 735 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 736 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 737 scif_schedrx(sc); 738 } 739 } else { 740 sc->sc_r_hiwat = scif_rbuf_hiwat; 741 sc->sc_r_lowat = scif_rbuf_lowat; 742 } 743 744 splx(s); 745 746 #ifdef SCIF_DEBUG 747 if (scif_debug) 748 scifstatus(sc, "scifparam "); 749 #endif 750 751 if (!ISSET(t->c_cflag, CHWFLOW)) { 752 if (sc->sc_tx_stopped) { 753 sc->sc_tx_stopped = 0; 754 scifstart(tp); 755 } 756 } 757 758 return (0); 759 } 760 761 void 762 scif_iflush(sc) 763 struct scif_softc *sc; 764 { 765 int i; 766 unsigned char c; 767 768 i = SHREG_SCFDR2 & SCFDR2_RECVCNT; 769 770 while (i > 0) { 771 c = SHREG_SCFRDR2; 772 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 773 i--; 774 } 775 } 776 777 int scif_getc __P((void)); 778 void scif_putc __P((int)); 779 780 int 781 scif_getc() 782 { 783 784 return (GetcScif()); 785 } 786 787 void 788 scif_putc(int c) 789 { 790 791 PutcScif(c); 792 } 793 794 int 795 scifopen(dev, flag, mode, p) 796 dev_t dev; 797 int flag, mode; 798 struct proc *p; 799 { 800 int unit = SCIFUNIT(dev); 801 struct scif_softc *sc; 802 struct tty *tp; 803 int s, s2; 804 int error; 805 806 if (unit >= scif_cd.cd_ndevs) 807 return (ENXIO); 808 sc = scif_cd.cd_devs[unit]; 809 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 810 sc->sc_rbuf == NULL) 811 return (ENXIO); 812 813 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 814 return (ENXIO); 815 816 #ifdef KGDB 817 /* 818 * If this is the kgdb port, no other use is permitted. 819 */ 820 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 821 return (EBUSY); 822 #endif 823 824 tp = sc->sc_tty; 825 826 if (ISSET(tp->t_state, TS_ISOPEN) && 827 ISSET(tp->t_state, TS_XCLUDE) && 828 p->p_ucred->cr_uid != 0) 829 return (EBUSY); 830 831 s = spltty(); 832 833 /* 834 * Do the following iff this is a first open. 835 */ 836 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 837 struct termios t; 838 839 tp->t_dev = dev; 840 841 s2 = splserial(); 842 843 /* Turn on interrupts. */ 844 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 845 846 splx(s2); 847 848 /* 849 * Initialize the termios status to the defaults. Add in the 850 * sticky bits from TIOCSFLAGS. 851 */ 852 t.c_ispeed = 0; 853 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 854 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 855 t.c_cflag = scifconscflag; 856 } else { 857 t.c_ospeed = TTYDEF_SPEED; 858 t.c_cflag = TTYDEF_CFLAG; 859 } 860 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 861 SET(t.c_cflag, CLOCAL); 862 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 863 SET(t.c_cflag, CRTSCTS); 864 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 865 SET(t.c_cflag, MDMBUF); 866 /* Make sure scifparam() will do something. */ 867 tp->t_ospeed = 0; 868 (void) scifparam(tp, &t); 869 tp->t_iflag = TTYDEF_IFLAG; 870 tp->t_oflag = TTYDEF_OFLAG; 871 tp->t_lflag = TTYDEF_LFLAG; 872 ttychars(tp); 873 ttsetwater(tp); 874 875 s2 = splserial(); 876 877 /* Clear the input ring, and unblock. */ 878 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 879 sc->sc_rbavail = scif_rbuf_size; 880 scif_iflush(sc); 881 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 882 #if 0 883 /* XXX (msaitoh) */ 884 scif_hwiflow(sc); 885 #endif 886 887 #ifdef SCIF_DEBUG 888 if (scif_debug) 889 scifstatus(sc, "scifopen "); 890 #endif 891 892 splx(s2); 893 } 894 895 splx(s); 896 897 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 898 if (error) 899 goto bad; 900 901 error = (*linesw[tp->t_line].l_open)(dev, tp); 902 if (error) 903 goto bad; 904 905 return (0); 906 907 bad: 908 909 return (error); 910 } 911 912 int 913 scifclose(dev, flag, mode, p) 914 dev_t dev; 915 int flag, mode; 916 struct proc *p; 917 { 918 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 919 struct tty *tp = sc->sc_tty; 920 921 /* XXX This is for cons.c. */ 922 if (!ISSET(tp->t_state, TS_ISOPEN)) 923 return (0); 924 925 (*linesw[tp->t_line].l_close)(tp, flag); 926 ttyclose(tp); 927 928 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 929 return (0); 930 931 return (0); 932 } 933 934 int 935 scifread(dev, uio, flag) 936 dev_t dev; 937 struct uio *uio; 938 int flag; 939 { 940 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 941 struct tty *tp = sc->sc_tty; 942 943 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 944 } 945 946 int 947 scifwrite(dev, uio, flag) 948 dev_t dev; 949 struct uio *uio; 950 int flag; 951 { 952 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 953 struct tty *tp = sc->sc_tty; 954 955 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 956 } 957 958 struct tty * 959 sciftty(dev) 960 dev_t dev; 961 { 962 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 963 struct tty *tp = sc->sc_tty; 964 965 return (tp); 966 } 967 968 int 969 scifioctl(dev, cmd, data, flag, p) 970 dev_t dev; 971 u_long cmd; 972 caddr_t data; 973 int flag; 974 struct proc *p; 975 { 976 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 977 struct tty *tp = sc->sc_tty; 978 int error; 979 int s; 980 981 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 982 return (EIO); 983 984 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 985 if (error >= 0) 986 return (error); 987 988 error = ttioctl(tp, cmd, data, flag, p); 989 if (error >= 0) 990 return (error); 991 992 error = 0; 993 994 s = splserial(); 995 996 switch (cmd) { 997 case TIOCSBRK: 998 scif_break(sc, 1); 999 break; 1000 1001 case TIOCCBRK: 1002 scif_break(sc, 0); 1003 break; 1004 1005 case TIOCGFLAGS: 1006 *(int *)data = sc->sc_swflags; 1007 break; 1008 1009 case TIOCSFLAGS: 1010 error = suser(p->p_ucred, &p->p_acflag); 1011 if (error) 1012 break; 1013 sc->sc_swflags = *(int *)data; 1014 break; 1015 1016 default: 1017 error = ENOTTY; 1018 break; 1019 } 1020 1021 splx(s); 1022 1023 return (error); 1024 } 1025 1026 integrate void 1027 scif_schedrx(sc) 1028 struct scif_softc *sc; 1029 { 1030 1031 sc->sc_rx_ready = 1; 1032 1033 /* Wake up the poller. */ 1034 #ifdef __GENERIC_SOFT_INTERRUPTS 1035 softintr_schedule(sc->sc_si); 1036 #else 1037 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1038 setsoftserial(); 1039 #else 1040 if (!scif_softintr_scheduled) { 1041 scif_softintr_scheduled = 1; 1042 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1043 } 1044 #endif 1045 #endif 1046 } 1047 1048 void 1049 scif_break(sc, onoff) 1050 struct scif_softc *sc; 1051 int onoff; 1052 { 1053 1054 if (onoff) 1055 SHREG_SCSSR2 &= ~SCSSR2_TDFE; 1056 else 1057 SHREG_SCSSR2 |= SCSSR2_TDFE; 1058 1059 #if 0 /* XXX */ 1060 if (!sc->sc_heldchange) { 1061 if (sc->sc_tx_busy) { 1062 sc->sc_heldtbc = sc->sc_tbc; 1063 sc->sc_tbc = 0; 1064 sc->sc_heldchange = 1; 1065 } else 1066 scif_loadchannelregs(sc); 1067 } 1068 #endif 1069 } 1070 1071 /* 1072 * Stop output, e.g., for ^S or output flush. 1073 */ 1074 void 1075 scifstop(tp, flag) 1076 struct tty *tp; 1077 int flag; 1078 { 1079 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1080 int s; 1081 1082 s = splserial(); 1083 if (ISSET(tp->t_state, TS_BUSY)) { 1084 /* Stop transmitting at the next chunk. */ 1085 sc->sc_tbc = 0; 1086 sc->sc_heldtbc = 0; 1087 if (!ISSET(tp->t_state, TS_TTSTOP)) 1088 SET(tp->t_state, TS_FLUSH); 1089 } 1090 splx(s); 1091 } 1092 1093 void 1094 scif_intr_init() 1095 { 1096 /* XXX */ 1097 } 1098 1099 void 1100 scifdiag(arg) 1101 void *arg; 1102 { 1103 struct scif_softc *sc = arg; 1104 int overflows, floods; 1105 int s; 1106 1107 s = splserial(); 1108 overflows = sc->sc_overflows; 1109 sc->sc_overflows = 0; 1110 floods = sc->sc_floods; 1111 sc->sc_floods = 0; 1112 sc->sc_errors = 0; 1113 splx(s); 1114 1115 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1116 sc->sc_dev.dv_xname, 1117 overflows, overflows == 1 ? "" : "s", 1118 floods, floods == 1 ? "" : "s"); 1119 } 1120 1121 integrate void 1122 scif_rxsoft(sc, tp) 1123 struct scif_softc *sc; 1124 struct tty *tp; 1125 { 1126 int (*rint) __P((int c, struct tty *tp)) = linesw[tp->t_line].l_rint; 1127 u_char *get, *end; 1128 u_int cc, scc; 1129 u_char ssr2; 1130 int code; 1131 int s; 1132 1133 end = sc->sc_ebuf; 1134 get = sc->sc_rbget; 1135 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1136 1137 if (cc == scif_rbuf_size) { 1138 sc->sc_floods++; 1139 if (sc->sc_errors++ == 0) 1140 callout(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1141 } 1142 1143 while (cc) { 1144 code = get[0]; 1145 ssr2 = get[1]; 1146 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1147 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1148 SET(code, TTY_FE); 1149 if (ISSET(ssr2, SCSSR2_PER)) 1150 SET(code, TTY_PE); 1151 } 1152 if ((*rint)(code, tp) == -1) { 1153 /* 1154 * The line discipline's buffer is out of space. 1155 */ 1156 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1157 /* 1158 * We're either not using flow control, or the 1159 * line discipline didn't tell us to block for 1160 * some reason. Either way, we have no way to 1161 * know when there's more space available, so 1162 * just drop the rest of the data. 1163 */ 1164 get += cc << 1; 1165 if (get >= end) 1166 get -= scif_rbuf_size << 1; 1167 cc = 0; 1168 } else { 1169 /* 1170 * Don't schedule any more receive processing 1171 * until the line discipline tells us there's 1172 * space available (through scifhwiflow()). 1173 * Leave the rest of the data in the input 1174 * buffer. 1175 */ 1176 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1177 } 1178 break; 1179 } 1180 get += 2; 1181 if (get >= end) 1182 get = sc->sc_rbuf; 1183 cc--; 1184 } 1185 1186 if (cc != scc) { 1187 sc->sc_rbget = get; 1188 s = splserial(); 1189 cc = sc->sc_rbavail += scc - cc; 1190 /* Buffers should be ok again, release possible block. */ 1191 if (cc >= sc->sc_r_lowat) { 1192 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1193 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1194 SHREG_SCSCR2 |= SCSCR2_RIE; 1195 } 1196 #if 0 1197 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1198 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1199 scif_hwiflow(sc); 1200 } 1201 #endif 1202 } 1203 splx(s); 1204 } 1205 } 1206 1207 integrate void 1208 scif_txsoft(sc, tp) 1209 struct scif_softc *sc; 1210 struct tty *tp; 1211 { 1212 1213 CLR(tp->t_state, TS_BUSY); 1214 if (ISSET(tp->t_state, TS_FLUSH)) 1215 CLR(tp->t_state, TS_FLUSH); 1216 else 1217 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1218 (*linesw[tp->t_line].l_start)(tp); 1219 } 1220 1221 integrate void 1222 scif_stsoft(sc, tp) 1223 struct scif_softc *sc; 1224 struct tty *tp; 1225 { 1226 #if 0 1227 /* XXX (msaitoh) */ 1228 u_char msr, delta; 1229 int s; 1230 1231 s = splserial(); 1232 msr = sc->sc_msr; 1233 delta = sc->sc_msr_delta; 1234 sc->sc_msr_delta = 0; 1235 splx(s); 1236 1237 if (ISSET(delta, sc->sc_msr_dcd)) { 1238 /* 1239 * Inform the tty layer that carrier detect changed. 1240 */ 1241 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)); 1242 } 1243 1244 if (ISSET(delta, sc->sc_msr_cts)) { 1245 /* Block or unblock output according to flow control. */ 1246 if (ISSET(msr, sc->sc_msr_cts)) { 1247 sc->sc_tx_stopped = 0; 1248 (*linesw[tp->t_line].l_start)(tp); 1249 } else { 1250 sc->sc_tx_stopped = 1; 1251 } 1252 } 1253 1254 #ifdef SCIF_DEBUG 1255 if (scif_debug) 1256 scifstatus(sc, "scif_stsoft"); 1257 #endif 1258 #endif 1259 } 1260 1261 #ifdef __GENERIC_SOFT_INTERRUPTS 1262 void 1263 scifsoft(arg) 1264 void *arg; 1265 { 1266 struct scif_softc *sc = arg; 1267 struct tty *tp; 1268 1269 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1270 return; 1271 1272 { 1273 #else 1274 void 1275 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1276 scifsoft() 1277 #else 1278 scifsoft(arg) 1279 void *arg; 1280 #endif 1281 { 1282 struct scif_softc *sc; 1283 struct tty *tp; 1284 int unit; 1285 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1286 int s; 1287 1288 s = splsoftserial(); 1289 scif_softintr_scheduled = 0; 1290 #endif 1291 1292 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1293 sc = scif_cd.cd_devs[unit]; 1294 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1295 continue; 1296 1297 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1298 continue; 1299 1300 tp = sc->sc_tty; 1301 if (tp == NULL) 1302 continue; 1303 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1304 continue; 1305 #endif 1306 tp = sc->sc_tty; 1307 1308 if (sc->sc_rx_ready) { 1309 sc->sc_rx_ready = 0; 1310 scif_rxsoft(sc, tp); 1311 } 1312 1313 #if 0 1314 if (sc->sc_st_check) { 1315 sc->sc_st_check = 0; 1316 scif_stsoft(sc, tp); 1317 } 1318 #endif 1319 1320 if (sc->sc_tx_done) { 1321 sc->sc_tx_done = 0; 1322 scif_txsoft(sc, tp); 1323 } 1324 } 1325 1326 #ifndef __GENERIC_SOFT_INTERRUPTS 1327 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1328 splx(s); 1329 #endif 1330 #endif 1331 } 1332 1333 int 1334 scifintr(arg) 1335 void *arg; 1336 { 1337 struct scif_softc *sc = arg; 1338 u_char *put, *end; 1339 u_int cc; 1340 u_short ssr2; 1341 int count; 1342 1343 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1344 return (0); 1345 1346 end = sc->sc_ebuf; 1347 put = sc->sc_rbput; 1348 cc = sc->sc_rbavail; 1349 1350 ssr2 = SHREG_SCSSR2; 1351 if (ISSET(ssr2, SCSSR2_BRK)) { 1352 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR); 1353 #if defined(DDB) || defined(KGDB) 1354 #ifdef DDB 1355 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1356 console_debugger(); 1357 } 1358 #endif 1359 #ifdef KGDB 1360 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1361 kgdb_connect(1); 1362 } 1363 #endif 1364 #endif /* DDB || KGDB */ 1365 } 1366 count = SHREG_SCFDR2 & SCFDR2_RECVCNT; 1367 if (count != 0) { 1368 while ((cc > 0) && (count > 0)) { 1369 put[0] = SHREG_SCFRDR2; 1370 put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff); 1371 1372 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 1373 1374 put += 2; 1375 if (put >= end) 1376 put = sc->sc_rbuf; 1377 cc--; 1378 count--; 1379 } 1380 1381 /* 1382 * Current string of incoming characters ended because 1383 * no more data was available or we ran out of space. 1384 * Schedule a receive event if any data was received. 1385 * If we're out of space, turn off receive interrupts. 1386 */ 1387 sc->sc_rbput = put; 1388 sc->sc_rbavail = cc; 1389 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1390 sc->sc_rx_ready = 1; 1391 1392 /* 1393 * See if we are in danger of overflowing a buffer. If 1394 * so, use hardware flow control to ease the pressure. 1395 */ 1396 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1397 cc < sc->sc_r_hiwat) { 1398 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1399 #if 0 1400 scif_hwiflow(sc); 1401 #endif 1402 } 1403 1404 /* 1405 * If we're out of space, disable receive interrupts 1406 * until the queue has drained a bit. 1407 */ 1408 if (!cc) { 1409 SHREG_SCSCR2 &= ~SCSCR2_RIE; 1410 } 1411 } else { 1412 if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) { 1413 SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE); 1414 } 1415 } 1416 1417 #if 0 1418 msr = bus_space_read_1(iot, ioh, scif_msr); 1419 delta = msr ^ sc->sc_msr; 1420 sc->sc_msr = msr; 1421 if (ISSET(delta, sc->sc_msr_mask)) { 1422 SET(sc->sc_msr_delta, delta); 1423 1424 /* 1425 * Pulse-per-second clock signal on edge of DCD? 1426 */ 1427 if (ISSET(delta, sc->sc_ppsmask)) { 1428 struct timeval tv; 1429 if (ISSET(msr, sc->sc_ppsmask) == 1430 sc->sc_ppsassert) { 1431 /* XXX nanotime() */ 1432 microtime(&tv); 1433 TIMEVAL_TO_TIMESPEC(&tv, 1434 &sc->ppsinfo.assert_timestamp); 1435 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1436 timespecadd(&sc->ppsinfo.assert_timestamp, 1437 &sc->ppsparam.assert_offset, 1438 &sc->ppsinfo.assert_timestamp); 1439 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1440 } 1441 1442 #ifdef PPS_SYNC 1443 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1444 hardpps(&tv, tv.tv_usec); 1445 #endif 1446 sc->ppsinfo.assert_sequence++; 1447 sc->ppsinfo.current_mode = 1448 sc->ppsparam.mode; 1449 1450 } else if (ISSET(msr, sc->sc_ppsmask) == 1451 sc->sc_ppsclear) { 1452 /* XXX nanotime() */ 1453 microtime(&tv); 1454 TIMEVAL_TO_TIMESPEC(&tv, 1455 &sc->ppsinfo.clear_timestamp); 1456 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1457 timespecadd(&sc->ppsinfo.clear_timestamp, 1458 &sc->ppsparam.clear_offset, 1459 &sc->ppsinfo.clear_timestamp); 1460 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1461 } 1462 1463 #ifdef PPS_SYNC 1464 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1465 hardpps(&tv, tv.tv_usec); 1466 #endif 1467 sc->ppsinfo.clear_sequence++; 1468 sc->ppsinfo.current_mode = 1469 sc->ppsparam.mode; 1470 } 1471 } 1472 1473 /* 1474 * Stop output immediately if we lose the output 1475 * flow control signal or carrier detect. 1476 */ 1477 if (ISSET(~msr, sc->sc_msr_mask)) { 1478 sc->sc_tbc = 0; 1479 sc->sc_heldtbc = 0; 1480 #ifdef SCIF_DEBUG 1481 if (scif_debug) 1482 scifstatus(sc, "scifintr "); 1483 #endif 1484 } 1485 1486 sc->sc_st_check = 1; 1487 } 1488 #endif 1489 1490 /* 1491 * Done handling any receive interrupts. See if data can be 1492 * transmitted as well. Schedule tx done event if no data left 1493 * and tty was marked busy. 1494 */ 1495 if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1496 /* 1497 * If we've delayed a parameter change, do it now, and restart 1498 * output. 1499 */ 1500 if (sc->sc_heldchange) { 1501 sc->sc_heldchange = 0; 1502 sc->sc_tbc = sc->sc_heldtbc; 1503 sc->sc_heldtbc = 0; 1504 } 1505 1506 /* Output the next chunk of the contiguous buffer, if any. */ 1507 if (sc->sc_tbc > 0) { 1508 int n; 1509 int max; 1510 int i; 1511 1512 n = sc->sc_tbc; 1513 max = sc->sc_fifolen - 1514 ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 1515 if (n > max) 1516 n = max; 1517 1518 for (i = 0; i < n; i++) { 1519 PutcScif(*(sc->sc_tba)); 1520 sc->sc_tba++; 1521 } 1522 sc->sc_tbc -= n; 1523 } else { 1524 /* Disable transmit completion interrupts if necessary. */ 1525 #if 0 1526 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1527 #endif 1528 SHREG_SCSCR2 &= ~SCSCR2_TIE; 1529 1530 if (sc->sc_tx_busy) { 1531 sc->sc_tx_busy = 0; 1532 sc->sc_tx_done = 1; 1533 } 1534 } 1535 } 1536 1537 /* Wake up the poller. */ 1538 #ifdef __GENERIC_SOFT_INTERRUPTS 1539 softintr_schedule(sc->sc_si); 1540 #else 1541 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1542 setsoftserial(); 1543 #else 1544 if (!scif_softintr_scheduled) { 1545 scif_softintr_scheduled = 1; 1546 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1547 } 1548 #endif 1549 #endif 1550 1551 #if NRND > 0 && defined(RND_SCIF) 1552 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1553 #endif 1554 1555 return (1); 1556 } 1557 1558 void 1559 scifcnprobe(cp) 1560 struct consdev *cp; 1561 { 1562 int maj; 1563 1564 /* locate the major number */ 1565 for (maj = 0; maj < nchrdev; maj++) 1566 if (cdevsw[maj].d_open == scifopen) 1567 break; 1568 1569 /* Initialize required fields. */ 1570 cp->cn_dev = makedev(maj, 0); 1571 #ifdef SCIFCONSOLE 1572 cp->cn_pri = CN_REMOTE; 1573 #else 1574 cp->cn_pri = CN_NORMAL; 1575 #endif 1576 } 1577 1578 #define scif_gets GetStrScif 1579 #define scif_puts PutStrScif 1580 1581 void 1582 scifcninit(cp) 1583 struct consdev *cp; 1584 { 1585 1586 InitializeScif(scifcn_speed); 1587 scifisconsole = 1; 1588 } 1589 1590 #define scif_getc GetcScif 1591 #define scif_putc PutcScif 1592 1593 int 1594 scifcngetc(dev) 1595 dev_t dev; 1596 { 1597 int c; 1598 int s; 1599 1600 s = splserial(); 1601 c = scif_getc(); 1602 splx(s); 1603 1604 return (c); 1605 } 1606 1607 void 1608 scifcnputc(dev, c) 1609 dev_t dev; 1610 int c; 1611 { 1612 int s; 1613 1614 s = splserial(); 1615 scif_putc(c); 1616 splx(s); 1617 } 1618