xref: /netbsd-src/sys/arch/sgimips/stand/common/iris_scsivar.h (revision d02e022db788ed4933c5904d9d6ce3af08f11fee)
1*d02e022dStsutsui /*	$NetBSD: iris_scsivar.h,v 1.1 2019/01/12 16:44:47 tsutsui Exp $	*/
2*d02e022dStsutsui 
3*d02e022dStsutsui /*
4*d02e022dStsutsui  * Copyright (c) 2018 Naruaki Etomi
5*d02e022dStsutsui  * All rights reserved.
6*d02e022dStsutsui  *
7*d02e022dStsutsui  * Redistribution and use in source and binary forms, with or without
8*d02e022dStsutsui  * modification, are permitted provided that the following conditions
9*d02e022dStsutsui  * are met:
10*d02e022dStsutsui  * 1. Redistributions of source code must retain the above copyright
11*d02e022dStsutsui  *    notice, this list of conditions and the following disclaimer.
12*d02e022dStsutsui  * 2. Redistributions in binary form must reproduce the above copyright
13*d02e022dStsutsui  *    notice, this list of conditions and the following disclaimer in the
14*d02e022dStsutsui  *    documentation and/or other materials provided with the distribution.
15*d02e022dStsutsui  *
16*d02e022dStsutsui  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17*d02e022dStsutsui  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18*d02e022dStsutsui  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19*d02e022dStsutsui  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20*d02e022dStsutsui  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21*d02e022dStsutsui  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22*d02e022dStsutsui  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23*d02e022dStsutsui  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24*d02e022dStsutsui  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25*d02e022dStsutsui  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26*d02e022dStsutsui  */
27*d02e022dStsutsui 
28*d02e022dStsutsui /*
29*d02e022dStsutsui  * Silicon Graphics "IRIS" series MIPS processors machine bootloader.
30*d02e022dStsutsui  * WD33C93 SCSI interface parameter description.
31*d02e022dStsutsui  */
32*d02e022dStsutsui 
33*d02e022dStsutsui #ifndef _SCSIVAR_H_
34*d02e022dStsutsui #define _SCSIVAR_H_
35*d02e022dStsutsui 
36*d02e022dStsutsui #define SBIC_MAX_MSGLEN	8
37*d02e022dStsutsui #define SBIC_ABORT_TIMEOUT	2000	/* time to wait for abort */
38*d02e022dStsutsui 
39*d02e022dStsutsui /*
40*d02e022dStsutsui  * SCSI delays
41*d02e022dStsutsui  * In u-seconds, primarily for state changes on the SPC.
42*d02e022dStsutsui  */
43*d02e022dStsutsui #define SBIC_CMD_WAIT	50000	/* wait per step of 'immediate' cmds */
44*d02e022dStsutsui #define SBIC_DATA_WAIT	50000	/* wait per data in/out step */
45*d02e022dStsutsui #define SBIC_INIT_WAIT	50000	/* wait per step (both) during init */
46*d02e022dStsutsui 
47*d02e022dStsutsui #define NSCSI			1
48*d02e022dStsutsui #define SCSI_LUN		0
49*d02e022dStsutsui #define SCSI_CLKFREQ		20
50*d02e022dStsutsui 
51*d02e022dStsutsui struct	wd33c93_softc {
52*d02e022dStsutsui 	volatile uint8_t *sc_asr_regh;	/* address register */
53*d02e022dStsutsui 	volatile uint8_t *sc_data_regh;	/* data register */
54*d02e022dStsutsui 	uint8_t sc_target;		/* Currently active target */
55*d02e022dStsutsui 	uint8_t sc_syncperiods;		/* Sync transfer periods (4ns units) */
56*d02e022dStsutsui 	u_short	sc_state;
57*d02e022dStsutsui 	u_short	sc_status;
58*d02e022dStsutsui 	int	sc_flags;
59*d02e022dStsutsui 	uint8_t	sc_imsg[SBIC_MAX_MSGLEN];
60*d02e022dStsutsui 	uint8_t	sc_omsg[SBIC_MAX_MSGLEN];
61*d02e022dStsutsui 	volatile int xs_status;		/* status flags */
62*d02e022dStsutsui };
63*d02e022dStsutsui 
64*d02e022dStsutsui struct wd33c93_softc wd33c93_softc[NSCSI];
65*d02e022dStsutsui 
66*d02e022dStsutsui extern uint8_t scsi_ctlr, scsi_id, scsi_part;
67*d02e022dStsutsui 
68*d02e022dStsutsui /* values for sc_flags */
69*d02e022dStsutsui #define SBICF_SELECTED	0x01	/* bus is in selected state. */
70*d02e022dStsutsui #define SBICF_NODMA	0x02	/* Polled transfer */
71*d02e022dStsutsui #define SBICF_INDMA	0x04	/* DMA I/O in progress */
72*d02e022dStsutsui #define SBICF_SYNCNEGO	0x08	/* Sync negotiation in progress */
73*d02e022dStsutsui #define SBICF_ABORTING	0x10	/* Aborting */
74*d02e022dStsutsui 
75*d02e022dStsutsui /* values for sc_state */
76*d02e022dStsutsui #define SBIC_UNINITIALIZED	0	/* Driver not initialized */
77*d02e022dStsutsui #define SBIC_IDLE		1	/* waiting for something to do */
78*d02e022dStsutsui #define SBIC_SELECTING		2	/* SCSI command is arbiting */
79*d02e022dStsutsui #define SBIC_RESELECTED		3	/* Has been reselected */
80*d02e022dStsutsui #define SBIC_IDENTIFIED		4	/* Has gotten IFY but not TAG */
81*d02e022dStsutsui #define SBIC_CONNECTED		5	/* Actively using the SCSI bus */
82*d02e022dStsutsui #define SBIC_DISCONNECT		6	/* MSG_DISCONNECT received */
83*d02e022dStsutsui #define SBIC_CMDCOMPLETE 	7	/* MSG_CMDCOMPLETE received */
84*d02e022dStsutsui #define SBIC_ERROR		8	/* Error has occurred */
85*d02e022dStsutsui #define SBIC_SELTIMEOUT		9	/* Select Timeout */
86*d02e022dStsutsui #define SBIC_CLEANING		10	/* Scrubbing ACB's */
87*d02e022dStsutsui #define SBIC_BUSRESET		11	/* SCSI RST has been issued */
88*d02e022dStsutsui 
89*d02e022dStsutsui /* values for sc_msgout */
90*d02e022dStsutsui #define SEND_DEV_RESET		0x0001
91*d02e022dStsutsui #define SEND_PARITY_ERROR	0x0002
92*d02e022dStsutsui #define SEND_INIT_DET_ERR	0x0004
93*d02e022dStsutsui #define SEND_REJECT		0x0008
94*d02e022dStsutsui #define SEND_IDENTIFY		0x0010
95*d02e022dStsutsui #define SEND_ABORT		0x0020
96*d02e022dStsutsui #define SEND_WDTR		0x0040
97*d02e022dStsutsui #define SEND_SDTR		0x0080
98*d02e022dStsutsui #define SEND_TAG		0x0100
99*d02e022dStsutsui 
100*d02e022dStsutsui #define STS_CHECKCOND		0x02	/* Check Condition (ie., read sense) */
101*d02e022dStsutsui 
102*d02e022dStsutsui /*
103*d02e022dStsutsui  * States returned by our state machine
104*d02e022dStsutsui  */
105*d02e022dStsutsui #define SBIC_STATE_ERROR	-1
106*d02e022dStsutsui #define SBIC_STATE_DONE		0
107*d02e022dStsutsui #define SBIC_STATE_RUNNING	1
108*d02e022dStsutsui #define SBIC_STATE_DISCONNECT	2
109*d02e022dStsutsui 
110*d02e022dStsutsui #define DEBUG_ACBS	0x01
111*d02e022dStsutsui #define DEBUG_INTS	0x02
112*d02e022dStsutsui #define DEBUG_CMDS	0x04
113*d02e022dStsutsui #define DEBUG_MISC	0x08
114*d02e022dStsutsui #define DEBUG_TRAC	0x10
115*d02e022dStsutsui #define DEBUG_RSEL	0x20
116*d02e022dStsutsui #define DEBUG_PHASE	0x40
117*d02e022dStsutsui #define DEBUG_DMA	0x80
118*d02e022dStsutsui #define DEBUG_CCMDS	0x100
119*d02e022dStsutsui #define DEBUG_MSGS	0x200
120*d02e022dStsutsui #define DEBUG_TAGS	0x400
121*d02e022dStsutsui #define DEBUG_SYNC	0x800
122*d02e022dStsutsui 
123*d02e022dStsutsui #endif /* _SCSIVAR_H_ */
124