1*d02e022dStsutsui /* $NetBSD: iris_machdep.h,v 1.1 2019/01/12 16:44:47 tsutsui Exp $ */ 2*d02e022dStsutsui 3*d02e022dStsutsui /* 4*d02e022dStsutsui * Copyright (c) 2018 Naruaki Etomi 5*d02e022dStsutsui * All rights reserved. 6*d02e022dStsutsui * 7*d02e022dStsutsui * Redistribution and use in source and binary forms, with or without 8*d02e022dStsutsui * modification, are permitted provided that the following conditions 9*d02e022dStsutsui * are met: 10*d02e022dStsutsui * 1. Redistributions of source code must retain the above copyright 11*d02e022dStsutsui * notice, this list of conditions and the following disclaimer. 12*d02e022dStsutsui * 2. Redistributions in binary form must reproduce the above copyright 13*d02e022dStsutsui * notice, this list of conditions and the following disclaimer in the 14*d02e022dStsutsui * documentation and/or other materials provided with the distribution. 15*d02e022dStsutsui * 16*d02e022dStsutsui * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*d02e022dStsutsui * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*d02e022dStsutsui * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*d02e022dStsutsui * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*d02e022dStsutsui * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21*d02e022dStsutsui * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22*d02e022dStsutsui * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23*d02e022dStsutsui * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24*d02e022dStsutsui * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25*d02e022dStsutsui * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26*d02e022dStsutsui */ 27*d02e022dStsutsui 28*d02e022dStsutsui /* 29*d02e022dStsutsui * Silicon Graphics "IRIS" series MIPS processors machine bootloader. 30*d02e022dStsutsui */ 31*d02e022dStsutsui 32*d02e022dStsutsui #include <sys/param.h> 33*d02e022dStsutsui #include <lib/libsa/stand.h> 34*d02e022dStsutsui #include "iris_scsivar.h" 35*d02e022dStsutsui 36*d02e022dStsutsui /* iris_boot.c */ 37*d02e022dStsutsui void again(void); 38*d02e022dStsutsui void reboot(void); 39*d02e022dStsutsui 40*d02e022dStsutsui /* iris_parse.c */ 41*d02e022dStsutsui void parse(char **, char *); 42*d02e022dStsutsui 43*d02e022dStsutsui /* iris_autoconf.c */ 44*d02e022dStsutsui void find_devs(void); 45*d02e022dStsutsui 46*d02e022dStsutsui /* iris_start.S */ 47*d02e022dStsutsui void romrestart(void); 48*d02e022dStsutsui 49*d02e022dStsutsui /* iris_cons.c */ 50*d02e022dStsutsui char *cninit(int *, int *); 51*d02e022dStsutsui int cngetc(void); 52*d02e022dStsutsui void cnputc(int); 53*d02e022dStsutsui int cnscan(void); 54*d02e022dStsutsui 55*d02e022dStsutsui /* iris_scsi.c */ 56*d02e022dStsutsui void wd33c93_init(void *, void*); 57*d02e022dStsutsui int wd33c93_go(struct wd33c93_softc *, uint8_t *, size_t, uint8_t *, size_t *); 58*d02e022dStsutsui 59*d02e022dStsutsui /* iris_scsictl.c */ 60*d02e022dStsutsui int scsi_test_unit_rdy(void); 61*d02e022dStsutsui int scsi_read_capacity(uint8_t *, size_t); 62*d02e022dStsutsui int scsi_read(uint8_t *, size_t, daddr_t, size_t); 63*d02e022dStsutsui int scsi_write(uint8_t *, size_t, daddr_t, size_t); 64*d02e022dStsutsui 65*d02e022dStsutsui #define INDIGO_R3K_MODE 66*d02e022dStsutsui 67*d02e022dStsutsui #ifdef INDIGO_R3K_MODE 68*d02e022dStsutsui #define ZS_ADDR 0x1fb80d10 69*d02e022dStsutsui #define SCSIA_ADDR 0x1FB80122 70*d02e022dStsutsui #define SCSID_ADDR 0x1FB80126 71*d02e022dStsutsui 72*d02e022dStsutsui /* Target is Personal IRIS R3000 36MHz. */ 73*d02e022dStsutsui #define CPUSPEED 36 74*d02e022dStsutsui #endif 75*d02e022dStsutsui 76*d02e022dStsutsui #ifdef INDIGO_R4K_MODE 77*d02e022dStsutsui #define ZS_ADDR 0x1fb80d10 78*d02e022dStsutsui #define SCSIA_ADDR 0x1FB80122 79*d02e022dStsutsui #define SCSID_ADDR 0x1FB80126 80*d02e022dStsutsui 81*d02e022dStsutsui /* Target is IRIS Indigo R4000 100MHz. */ 82*d02e022dStsutsui #define CPUSPEED 100 83*d02e022dStsutsui #endif 84*d02e022dStsutsui 85*d02e022dStsutsui #ifdef INDY_MODE 86*d02e022dStsutsui #define ZS_ADDR 0x1fbd9830 87*d02e022dStsutsui #define SCSIA_ADDR 0x1FBC0003 88*d02e022dStsutsui #define SCSID_ADDR 0x1FBC0007 89*d02e022dStsutsui 90*d02e022dStsutsui /* Target is Indy 180MHz. */ 91*d02e022dStsutsui #define CPUSPEED 180 92*d02e022dStsutsui #endif 93*d02e022dStsutsui 94*d02e022dStsutsui #define DELAY(n) \ 95*d02e022dStsutsui do { \ 96*d02e022dStsutsui register int __N = (CPUSPEED) / 2 * n; \ 97*d02e022dStsutsui do { \ 98*d02e022dStsutsui __asm("addiu %0,%1,-1" : "=r" (__N) : "0" (__N)); \ 99*d02e022dStsutsui } while (__N > 0); \ 100*d02e022dStsutsui } while (/* CONSTCOND */ 0) 101