1 /* $NetBSD: mace.c,v 1.13 2007/10/17 19:57:05 garbled Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Christopher Sekiya 5 * Copyright (c) 2002,2003 Rafal K. Boni 6 * Copyright (c) 2000 Soren S. Jorvang 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * O2 MACE 39 * 40 * The MACE is weird -- although it is a 32-bit device, writes only seem to 41 * work properly if they are 64-bit-at-once writes (at least, out in ISA 42 * space and probably MEC space -- the PCI stuff seems to be okay with _4). 43 * Therefore, the _8* routines are used even though the top 32 bits are 44 * thrown away. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.13 2007/10/17 19:57:05 garbled Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/ioctl.h> 59 #include <sys/errno.h> 60 #include <sys/syslog.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #define _SGIMIPS_BUS_DMA_PRIVATE 65 #include <machine/bus.h> 66 #include <machine/cpu.h> 67 #include <machine/locore.h> 68 #include <machine/autoconf.h> 69 #include <machine/machtype.h> 70 71 #include <sgimips/mace/macevar.h> 72 #include <sgimips/mace/macereg.h> 73 #include <sgimips/dev/crimevar.h> 74 #include <sgimips/dev/crimereg.h> 75 76 #include "locators.h" 77 78 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ 79 80 struct { 81 unsigned int irq; 82 unsigned int intrmask; 83 int (*func)(void *); 84 void *arg; 85 struct evcnt evcnt; 86 char evname[32]; 87 } maceintrtab[MACE_NINTR]; 88 89 struct mace_softc { 90 struct device sc_dev; 91 92 bus_space_tag_t iot; 93 bus_space_handle_t ioh; 94 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ 95 int nsegs; 96 bus_dma_segment_t seg; 97 bus_dmamap_t map; 98 99 void *isa_ringbuffer; 100 }; 101 102 static int mace_match(struct device *, struct cfdata *, void *); 103 static void mace_attach(struct device *, struct device *, void *); 104 static int mace_print(void *, const char *); 105 static int mace_search(struct device *, struct cfdata *, 106 const int *, void *); 107 108 CFATTACH_DECL(mace, sizeof(struct mace_softc), 109 mace_match, mace_attach, NULL, NULL); 110 111 #if defined(BLINK) 112 static callout_t mace_blink_ch; 113 static void mace_blink(void *); 114 #endif 115 116 static int 117 mace_match(struct device *parent, struct cfdata *match, void *aux) 118 { 119 120 /* 121 * The MACE is in the O2. 122 */ 123 if (mach_type == MACH_SGI_IP32) 124 return (1); 125 126 return (0); 127 } 128 129 static void 130 mace_attach(struct device *parent, struct device *self, void *aux) 131 { 132 struct mace_softc *sc = (struct mace_softc *)self; 133 struct mainbus_attach_args *ma = aux; 134 u_int32_t scratch; 135 136 #ifdef BLINK 137 callout_init(&mace_blink_ch, 0); 138 #endif 139 140 sc->iot = SGIMIPS_BUS_SPACE_MACE; 141 sc->dmat = &sgimips_default_bus_dma_tag; 142 143 if (bus_space_map(sc->iot, ma->ma_addr, 0, 144 BUS_SPACE_MAP_LINEAR, &sc->ioh)) 145 panic("mace_attach: could not allocate memory\n"); 146 147 #if 0 148 /* 149 * There's something deeply wrong with the alloc() routine -- it 150 * returns a pointer to memory that is used by the kernel i/o 151 * buffers. Disable for now. 152 */ 153 154 if ((bus_dmamem_alloc(sc->dmat, 32768, PAGE_SIZE, 32768, 155 &sc->seg, 1, &sc->nsegs, BUS_DMA_NOWAIT)) != 0) { 156 printf(": unable to allocate DMA memory\n"); 157 return; 158 } 159 160 if ((bus_dmamem_map(sc->dmat, &sc->seg, sc->nsegs, 32768, 161 (void **)&sc->isa_ringbuffer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) 162 != 0) { 163 printf(": unable to map control data\n"); 164 return; 165 } 166 167 if ((bus_dmamap_create(sc->dmat, 32768, 1, 32768, 0, 168 BUS_DMA_NOWAIT, &sc->map)) != 0) { 169 printf(": unable to create DMA map for control data\n"); 170 return; 171 } 172 173 if ((scratch = bus_dmamap_load(sc->dmat, sc->map, sc->isa_ringbuffer, 174 32768, NULL, BUS_DMA_NOWAIT)) != 0) { 175 printf(": unable to load DMA map for control data %i\n", 176 scratch); 177 } 178 179 memset(sc->isa_ringbuffer, 0, 32768); 180 181 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_RINGBASE, 182 MIPS_KSEG1_TO_PHYS(sc->isa_ringbuffer) & 0xffff8000); 183 184 aprint_normal(" isa ringbuffer 0x%x size 32k", 185 MIPS_KSEG1_TO_PHYS((unsigned long)sc->isa_ringbuffer)); 186 #endif 187 188 aprint_normal("\n"); 189 190 aprint_debug("%s: isa sts %llx\n", self->dv_xname, 191 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); 192 aprint_debug("%s: isa msk %llx\n", self->dv_xname, 193 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); 194 195 /* 196 * Turn on most ISA interrupts. These are actually masked and 197 * registered via the CRIME, as the MACE ISA interrupt mask is 198 * really whacky and nigh on impossible to map to a sane autoconfig 199 * scheme. We do, however, turn off the count/compare timer and RTC 200 * interrupts as they are unused and conflict with the PS/2 201 * keyboard and mouse interrupts. 202 */ 203 204 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffff0aff); 205 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); 206 207 /* set up LED for solid green or blink, if that's your fancy */ 208 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 209 scratch |= MACE_ISA_LED_RED; 210 scratch &= ~(MACE_ISA_LED_GREEN); 211 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); 212 213 #if defined(BLINK) 214 mace_blink(sc); 215 #endif 216 217 /* Initialize the maceintr elements to sane values */ 218 for (scratch = 0; scratch < MACE_NINTR; scratch++) { 219 maceintrtab[scratch].func = NULL; 220 maceintrtab[scratch].irq = 0; 221 } 222 223 config_search_ia(mace_search, self, "mace", NULL); 224 } 225 226 227 static int 228 mace_print(void *aux, const char *pnp) 229 { 230 struct mace_attach_args *maa = aux; 231 232 if (pnp != 0) 233 return QUIET; 234 235 if (maa->maa_offset != MACECF_OFFSET_DEFAULT) 236 aprint_normal(" offset 0x%lx", maa->maa_offset); 237 if (maa->maa_intr != MACECF_INTR_DEFAULT) 238 aprint_normal(" intr %d", maa->maa_intr); 239 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) 240 aprint_normal(" intrmask 0x%x", maa->maa_intrmask); 241 242 return UNCONF; 243 } 244 245 static int 246 mace_search(struct device *parent, struct cfdata *cf, 247 const int *ldesc, void *aux) 248 { 249 struct mace_softc *sc = (struct mace_softc *)parent; 250 struct mace_attach_args maa; 251 int tryagain; 252 253 do { 254 maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; 255 maa.maa_intr = cf->cf_loc[MACECF_INTR]; 256 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; 257 maa.maa_st = SGIMIPS_BUS_SPACE_MACE; 258 maa.maa_sh = sc->ioh; /* XXX */ 259 maa.maa_dmat = &sgimips_default_bus_dma_tag; 260 maa.isa_ringbuffer = sc->isa_ringbuffer; 261 262 tryagain = 0; 263 if (config_match(parent, cf, &maa) > 0) { 264 config_attach(parent, cf, &maa, mace_print); 265 tryagain = (cf->cf_fstate == FSTATE_STAR); 266 } 267 268 } while (tryagain); 269 270 return 0; 271 } 272 273 void * 274 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg) 275 { 276 int i; 277 278 if (intr < 0 || intr >= 16) 279 panic("invalid interrupt number"); 280 281 for (i = 0; i < MACE_NINTR; i++) 282 if (maceintrtab[i].func == NULL) { 283 maceintrtab[i].func = func; 284 maceintrtab[i].arg = arg; 285 maceintrtab[i].irq = (1 << intr); 286 maceintrtab[i].intrmask = level; 287 snprintf(maceintrtab[i].evname, 288 sizeof(maceintrtab[i].evname), 289 "intr %d level 0x%x", intr, level); 290 evcnt_attach_dynamic(&maceintrtab[i].evcnt, 291 EVCNT_TYPE_INTR, NULL, 292 "mace", maceintrtab[i].evname); 293 break; 294 } 295 296 crime_intr_mask(intr); 297 aprint_debug("mace: established interrupt %d (level %x)\n", 298 intr, level); 299 return (void *)&maceintrtab[i]; 300 } 301 302 void 303 mace_intr_disestablish(void *cookie) 304 { 305 int intr = -1, level = 0, irq = 0, i; 306 307 for (i = 0; i < MACE_NINTR; i++) 308 if (&maceintrtab[i] == cookie) { 309 evcnt_detach(&maceintrtab[i].evcnt); 310 for (intr = 0; 311 maceintrtab[i].irq == (1 << intr); intr ++); 312 level = maceintrtab[i].intrmask; 313 irq = maceintrtab[i].irq; 314 315 maceintrtab[i].irq = 0; 316 maceintrtab[i].intrmask = 0; 317 maceintrtab[i].func = NULL; 318 maceintrtab[i].arg = NULL; 319 bzero(&maceintrtab[i].evcnt, sizeof (struct evcnt)); 320 bzero(&maceintrtab[i].evname, 321 sizeof (maceintrtab[i].evname)); 322 break; 323 } 324 if (intr == -1) 325 panic("mace: lost maceintrtab"); 326 327 /* do not do a unmask, when irq is being shared. */ 328 for (i = 0; i < MACE_NINTR; i++) 329 if (&maceintrtab[i].func != NULL && maceintrtab[i].irq == irq) 330 break; 331 if (i == MACE_NINTR) 332 crime_intr_unmask(intr); 333 aprint_debug("mace: disestablished interrupt %d (level %x)\n", 334 intr, level); 335 } 336 337 void 338 mace_intr(int irqs) 339 { 340 u_int64_t isa_irq, isa_mask; 341 int i; 342 343 /* irq 4 is the ISA cascade interrupt. Must handle with care. */ 344 if (irqs & (1 << 4)) { 345 isa_mask = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 346 + MACE_ISA_INT_MASK)); 347 isa_irq = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 348 + MACE_ISA_INT_STATUS)); 349 for (i = 0; i < MACE_NINTR; i++) { 350 if ((maceintrtab[i].irq == (1 << 4)) && 351 (isa_irq & maceintrtab[i].intrmask)) { 352 (maceintrtab[i].func)(maceintrtab[i].arg); 353 maceintrtab[i].evcnt.ev_count++; 354 } 355 } 356 #if 0 357 mips3_sd((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 358 + MACE_ISA_INT_STATUS), isa_mask); 359 #endif 360 irqs &= ~(1 << 4); 361 } 362 363 for (i = 0; i < MACE_NINTR; i++) 364 if ((irqs & maceintrtab[i].irq)) { 365 (maceintrtab[i].func)(maceintrtab[i].arg); 366 maceintrtab[i].evcnt.ev_count++; 367 } 368 } 369 370 #if defined(BLINK) 371 static void 372 mace_blink(void *self) 373 { 374 struct mace_softc *sc = (struct mace_softc *) self; 375 register int s; 376 int value; 377 378 s = splhigh(); 379 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 380 value ^= MACE_ISA_LED_GREEN; 381 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); 382 splx(s); 383 /* 384 * Blink rate is: 385 * full cycle every second if completely idle (loadav = 0) 386 * full cycle every 2 seconds if loadav = 1 387 * full cycle every 3 seconds if loadav = 2 388 * etc. 389 */ 390 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 391 callout_reset(&mace_blink_ch, s, mace_blink, sc); 392 393 } 394 #endif 395