xref: /netbsd-src/sys/arch/sgimips/mace/if_mec.c (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /* $NetBSD: if_mec.c,v 1.57 2018/06/26 06:47:59 msaitoh Exp $ */
2 
3 /*-
4  * Copyright (c) 2004, 2008 Izumi Tsutsui.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 /*
28  * Copyright (c) 2003 Christopher SEKIYA
29  * All rights reserved.
30  *
31  * Redistribution and use in source and binary forms, with or without
32  * modification, are permitted provided that the following conditions
33  * are met:
34  * 1. Redistributions of source code must retain the above copyright
35  *    notice, this list of conditions and the following disclaimer.
36  * 2. Redistributions in binary form must reproduce the above copyright
37  *    notice, this list of conditions and the following disclaimer in the
38  *    documentation and/or other materials provided with the distribution.
39  * 3. All advertising materials mentioning features or use of this software
40  *    must display the following acknowledgement:
41  *          This product includes software developed for the
42  *          NetBSD Project.  See http://www.NetBSD.org/ for
43  *          information about NetBSD.
44  * 4. The name of the author may not be used to endorse or promote products
45  *    derived from this software without specific prior written permission.
46  *
47  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57  */
58 
59 /*
60  * MACE MAC-110 Ethernet driver
61  */
62 
63 #include <sys/cdefs.h>
64 __KERNEL_RCSID(0, "$NetBSD: if_mec.c,v 1.57 2018/06/26 06:47:59 msaitoh Exp $");
65 
66 #include "opt_ddb.h"
67 
68 #include <sys/param.h>
69 #include <sys/systm.h>
70 #include <sys/device.h>
71 #include <sys/callout.h>
72 #include <sys/mbuf.h>
73 #include <sys/malloc.h>
74 #include <sys/kernel.h>
75 #include <sys/socket.h>
76 #include <sys/ioctl.h>
77 #include <sys/errno.h>
78 
79 #include <sys/rndsource.h>
80 
81 #include <net/if.h>
82 #include <net/if_dl.h>
83 #include <net/if_media.h>
84 #include <net/if_ether.h>
85 
86 #include <netinet/in.h>
87 #include <netinet/in_systm.h>
88 #include <netinet/ip.h>
89 #include <netinet/tcp.h>
90 #include <netinet/udp.h>
91 
92 #include <net/bpf.h>
93 
94 #include <sys/bus.h>
95 #include <machine/intr.h>
96 #include <machine/machtype.h>
97 
98 #include <dev/mii/mii.h>
99 #include <dev/mii/miivar.h>
100 
101 #include <sgimips/mace/macevar.h>
102 #include <sgimips/mace/if_mecreg.h>
103 
104 #include <dev/arcbios/arcbios.h>
105 #include <dev/arcbios/arcbiosvar.h>
106 
107 /* #define MEC_DEBUG */
108 
109 #ifdef MEC_DEBUG
110 #define MEC_DEBUG_RESET		0x01
111 #define MEC_DEBUG_START		0x02
112 #define MEC_DEBUG_STOP		0x04
113 #define MEC_DEBUG_INTR		0x08
114 #define MEC_DEBUG_RXINTR	0x10
115 #define MEC_DEBUG_TXINTR	0x20
116 #define MEC_DEBUG_TXSEGS	0x40
117 uint32_t mec_debug = 0;
118 #define DPRINTF(x, y)	if (mec_debug & (x)) printf y
119 #else
120 #define DPRINTF(x, y)	/* nothing */
121 #endif
122 
123 /* #define MEC_EVENT_COUNTERS */
124 
125 #ifdef MEC_EVENT_COUNTERS
126 #define MEC_EVCNT_INCR(ev)	(ev)->ev_count++
127 #else
128 #define MEC_EVCNT_INCR(ev)	do {} while (/* CONSTCOND */ 0)
129 #endif
130 
131 /*
132  * Transmit descriptor list size
133  */
134 #define MEC_NTXDESC		64
135 #define MEC_NTXDESC_MASK	(MEC_NTXDESC - 1)
136 #define MEC_NEXTTX(x)		(((x) + 1) & MEC_NTXDESC_MASK)
137 #define MEC_NTXDESC_RSVD	4
138 #define MEC_NTXDESC_INTR	8
139 
140 /*
141  * software state for TX
142  */
143 struct mec_txsoft {
144 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
145 	bus_dmamap_t txs_dmamap;	/* our DMA map */
146 	uint32_t txs_flags;
147 #define MEC_TXS_BUFLEN_MASK	0x0000007f	/* data len in txd_buf */
148 #define MEC_TXS_TXDPTR		0x00000080	/* concat txd_ptr is used */
149 };
150 
151 /*
152  * Transmit buffer descriptor
153  */
154 #define MEC_TXDESCSIZE		128
155 #define MEC_NTXPTR		3
156 #define MEC_TXD_BUFOFFSET	sizeof(uint64_t)
157 #define MEC_TXD_BUFOFFSET1	\
158 	(sizeof(uint64_t) + sizeof(uint64_t) * MEC_NTXPTR)
159 #define MEC_TXD_BUFSIZE		(MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET)
160 #define MEC_TXD_BUFSIZE1	(MEC_TXDESCSIZE - MEC_TXD_BUFOFFSET1)
161 #define MEC_TXD_BUFSTART(len)	(MEC_TXD_BUFSIZE - (len))
162 #define MEC_TXD_ALIGN		8
163 #define MEC_TXD_ALIGNMASK	(MEC_TXD_ALIGN - 1)
164 #define MEC_TXD_ROUNDUP(addr)	\
165 	(((addr) + MEC_TXD_ALIGNMASK) & ~(uint64_t)MEC_TXD_ALIGNMASK)
166 #define MEC_NTXSEG		16
167 
168 struct mec_txdesc {
169 	volatile uint64_t txd_cmd;
170 #define MEC_TXCMD_DATALEN	0x000000000000ffff	/* data length */
171 #define MEC_TXCMD_BUFSTART	0x00000000007f0000	/* start byte offset */
172 #define  TXCMD_BUFSTART(x)	((x) << 16)
173 #define MEC_TXCMD_TERMDMA	0x0000000000800000	/* stop DMA on abort */
174 #define MEC_TXCMD_TXINT		0x0000000001000000	/* INT after TX done */
175 #define MEC_TXCMD_PTR1		0x0000000002000000	/* valid 1st txd_ptr */
176 #define MEC_TXCMD_PTR2		0x0000000004000000	/* valid 2nd txd_ptr */
177 #define MEC_TXCMD_PTR3		0x0000000008000000	/* valid 3rd txd_ptr */
178 #define MEC_TXCMD_UNUSED	0xfffffffff0000000ULL	/* should be zero */
179 
180 #define txd_stat	txd_cmd
181 #define MEC_TXSTAT_LEN		0x000000000000ffff	/* TX length */
182 #define MEC_TXSTAT_COLCNT	0x00000000000f0000	/* collision count */
183 #define MEC_TXSTAT_COLCNT_SHIFT	16
184 #define MEC_TXSTAT_LATE_COL	0x0000000000100000	/* late collision */
185 #define MEC_TXSTAT_CRCERROR	0x0000000000200000	/* */
186 #define MEC_TXSTAT_DEFERRED	0x0000000000400000	/* */
187 #define MEC_TXSTAT_SUCCESS	0x0000000000800000	/* TX complete */
188 #define MEC_TXSTAT_TOOBIG	0x0000000001000000	/* */
189 #define MEC_TXSTAT_UNDERRUN	0x0000000002000000	/* */
190 #define MEC_TXSTAT_COLLISIONS	0x0000000004000000	/* */
191 #define MEC_TXSTAT_EXDEFERRAL	0x0000000008000000	/* */
192 #define MEC_TXSTAT_COLLIDED	0x0000000010000000	/* */
193 #define MEC_TXSTAT_UNUSED	0x7fffffffe0000000ULL	/* should be zero */
194 #define MEC_TXSTAT_SENT		0x8000000000000000ULL	/* packet sent */
195 
196 	union {
197 		uint64_t txptr[MEC_NTXPTR];
198 #define MEC_TXPTR_UNUSED2	0x0000000000000007	/* should be zero */
199 #define MEC_TXPTR_DMAADDR	0x00000000fffffff8	/* TX DMA address */
200 #define MEC_TXPTR_LEN		0x0000ffff00000000ULL	/* buffer length */
201 #define  TXPTR_LEN(x)		((uint64_t)(x) << 32)
202 #define MEC_TXPTR_UNUSED1	0xffff000000000000ULL	/* should be zero */
203 
204 		uint8_t txbuf[MEC_TXD_BUFSIZE];
205 	} txd_data;
206 #define txd_ptr		txd_data.txptr
207 #define txd_buf		txd_data.txbuf
208 };
209 
210 /*
211  * Receive buffer size
212  */
213 #define MEC_NRXDESC		16
214 #define MEC_NRXDESC_MASK	(MEC_NRXDESC - 1)
215 #define MEC_NEXTRX(x)		(((x) + 1) & MEC_NRXDESC_MASK)
216 
217 /*
218  * Receive buffer description
219  */
220 #define MEC_RXDESCSIZE		4096	/* umm, should be 4kbyte aligned */
221 #define MEC_RXD_NRXPAD		3
222 #define MEC_RXD_DMAOFFSET	(1 + MEC_RXD_NRXPAD)
223 #define MEC_RXD_BUFOFFSET	(MEC_RXD_DMAOFFSET * sizeof(uint64_t))
224 #define MEC_RXD_BUFSIZE		(MEC_RXDESCSIZE - MEC_RXD_BUFOFFSET)
225 
226 struct mec_rxdesc {
227 	volatile uint64_t rxd_stat;
228 #define MEC_RXSTAT_LEN		0x000000000000ffff	/* data length */
229 #define MEC_RXSTAT_VIOLATION	0x0000000000010000	/* code violation (?) */
230 #define MEC_RXSTAT_UNUSED2	0x0000000000020000	/* unknown (?) */
231 #define MEC_RXSTAT_CRCERROR	0x0000000000040000	/* CRC error */
232 #define MEC_RXSTAT_MULTICAST	0x0000000000080000	/* multicast packet */
233 #define MEC_RXSTAT_BROADCAST	0x0000000000100000	/* broadcast packet */
234 #define MEC_RXSTAT_INVALID	0x0000000000200000	/* invalid preamble */
235 #define MEC_RXSTAT_LONGEVENT	0x0000000000400000	/* long packet */
236 #define MEC_RXSTAT_BADPACKET	0x0000000000800000	/* bad packet */
237 #define MEC_RXSTAT_CAREVENT	0x0000000001000000	/* carrier event */
238 #define MEC_RXSTAT_MATCHMCAST	0x0000000002000000	/* match multicast */
239 #define MEC_RXSTAT_MATCHMAC	0x0000000004000000	/* match MAC */
240 #define MEC_RXSTAT_SEQNUM	0x00000000f8000000	/* sequence number */
241 #define MEC_RXSTAT_CKSUM	0x0000ffff00000000ULL	/* IP checksum */
242 #define  RXSTAT_CKSUM(x)	(((uint64_t)(x) & MEC_RXSTAT_CKSUM) >> 32)
243 #define MEC_RXSTAT_UNUSED1	0x7fff000000000000ULL	/* should be zero */
244 #define MEC_RXSTAT_RECEIVED	0x8000000000000000ULL	/* set to 1 on RX */
245 	uint64_t rxd_pad1[MEC_RXD_NRXPAD];
246 	uint8_t  rxd_buf[MEC_RXD_BUFSIZE];
247 };
248 
249 /*
250  * control structures for DMA ops
251  */
252 struct mec_control_data {
253 	/*
254 	 * TX descriptors and buffers
255 	 */
256 	struct mec_txdesc mcd_txdesc[MEC_NTXDESC];
257 
258 	/*
259 	 * RX descriptors and buffers
260 	 */
261 	struct mec_rxdesc mcd_rxdesc[MEC_NRXDESC];
262 };
263 
264 /*
265  * It _seems_ there are some restrictions on descriptor address:
266  *
267  * - Base address of txdescs should be 8kbyte aligned
268  * - Each txdesc should be 128byte aligned
269  * - Each rxdesc should be 4kbyte aligned
270  *
271  * So we should specify 8k align to allocalte txdescs.
272  * In this case, sizeof(struct mec_txdesc) * MEC_NTXDESC is 8192
273  * so rxdescs are also allocated at 4kbyte aligned.
274  */
275 #define MEC_CONTROL_DATA_ALIGN	(8 * 1024)
276 
277 #define MEC_CDOFF(x)	offsetof(struct mec_control_data, x)
278 #define MEC_CDTXOFF(x)	MEC_CDOFF(mcd_txdesc[(x)])
279 #define MEC_CDRXOFF(x)	MEC_CDOFF(mcd_rxdesc[(x)])
280 
281 /*
282  * software state per device
283  */
284 struct mec_softc {
285 	device_t sc_dev;		/* generic device structures */
286 
287 	bus_space_tag_t sc_st;		/* bus_space tag */
288 	bus_space_handle_t sc_sh;	/* bus_space handle */
289 	bus_dma_tag_t sc_dmat;		/* bus_dma tag */
290 
291 	struct ethercom sc_ethercom;	/* Ethernet common part */
292 
293 	struct mii_data sc_mii;		/* MII/media information */
294 	int sc_phyaddr;			/* MII address */
295 	struct callout sc_tick_ch;	/* tick callout */
296 
297 	uint8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */
298 
299 	bus_dmamap_t sc_cddmamap;	/* bus_dma map for control data */
300 #define sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
301 
302 	/* pointer to allocated control data */
303 	struct mec_control_data *sc_control_data;
304 #define sc_txdesc	sc_control_data->mcd_txdesc
305 #define sc_rxdesc	sc_control_data->mcd_rxdesc
306 
307 	/* software state for TX descs */
308 	struct mec_txsoft sc_txsoft[MEC_NTXDESC];
309 
310 	int sc_txpending;		/* number of TX requests pending */
311 	int sc_txdirty;			/* first dirty TX descriptor */
312 	int sc_txlast;			/* last used TX descriptor */
313 
314 	int sc_rxptr;			/* next ready RX buffer */
315 
316 	krndsource_t sc_rnd_source; /* random source */
317 #ifdef MEC_EVENT_COUNTERS
318 	struct evcnt sc_ev_txpkts;	/* TX packets queued total */
319 	struct evcnt sc_ev_txdpad;	/* TX packets padded in txdesc buf */
320 	struct evcnt sc_ev_txdbuf;	/* TX packets copied to txdesc buf */
321 	struct evcnt sc_ev_txptr1;	/* TX packets using concat ptr1 */
322 	struct evcnt sc_ev_txptr1a;	/* TX packets  w/ptr1  ~160bytes */
323 	struct evcnt sc_ev_txptr1b;	/* TX packets  w/ptr1  ~256bytes */
324 	struct evcnt sc_ev_txptr1c;	/* TX packets  w/ptr1  ~512bytes */
325 	struct evcnt sc_ev_txptr1d;	/* TX packets  w/ptr1 ~1024bytes */
326 	struct evcnt sc_ev_txptr1e;	/* TX packets  w/ptr1 >1024bytes */
327 	struct evcnt sc_ev_txptr2;	/* TX packets using concat ptr1,2 */
328 	struct evcnt sc_ev_txptr2a;	/* TX packets  w/ptr2  ~160bytes */
329 	struct evcnt sc_ev_txptr2b;	/* TX packets  w/ptr2  ~256bytes */
330 	struct evcnt sc_ev_txptr2c;	/* TX packets  w/ptr2  ~512bytes */
331 	struct evcnt sc_ev_txptr2d;	/* TX packets  w/ptr2 ~1024bytes */
332 	struct evcnt sc_ev_txptr2e;	/* TX packets  w/ptr2 >1024bytes */
333 	struct evcnt sc_ev_txptr3;	/* TX packets using concat ptr1,2,3 */
334 	struct evcnt sc_ev_txptr3a;	/* TX packets  w/ptr3  ~160bytes */
335 	struct evcnt sc_ev_txptr3b;	/* TX packets  w/ptr3  ~256bytes */
336 	struct evcnt sc_ev_txptr3c;	/* TX packets  w/ptr3  ~512bytes */
337 	struct evcnt sc_ev_txptr3d;	/* TX packets  w/ptr3 ~1024bytes */
338 	struct evcnt sc_ev_txptr3e;	/* TX packets  w/ptr3 >1024bytes */
339 	struct evcnt sc_ev_txmbuf;	/* TX packets copied to new mbufs */
340 	struct evcnt sc_ev_txmbufa;	/* TX packets  w/mbuf  ~160bytes */
341 	struct evcnt sc_ev_txmbufb;	/* TX packets  w/mbuf  ~256bytes */
342 	struct evcnt sc_ev_txmbufc;	/* TX packets  w/mbuf  ~512bytes */
343 	struct evcnt sc_ev_txmbufd;	/* TX packets  w/mbuf ~1024bytes */
344 	struct evcnt sc_ev_txmbufe;	/* TX packets  w/mbuf >1024bytes */
345 	struct evcnt sc_ev_txptrs;	/* TX packets using ptrs total */
346 	struct evcnt sc_ev_txptrc0;	/* TX packets  w/ptrs no hdr chain */
347 	struct evcnt sc_ev_txptrc1;	/* TX packets  w/ptrs  1 hdr chain */
348 	struct evcnt sc_ev_txptrc2;	/* TX packets  w/ptrs  2 hdr chains */
349 	struct evcnt sc_ev_txptrc3;	/* TX packets  w/ptrs  3 hdr chains */
350 	struct evcnt sc_ev_txptrc4;	/* TX packets  w/ptrs  4 hdr chains */
351 	struct evcnt sc_ev_txptrc5;	/* TX packets  w/ptrs  5 hdr chains */
352 	struct evcnt sc_ev_txptrc6;	/* TX packets  w/ptrs >5 hdr chains */
353 	struct evcnt sc_ev_txptrh0;	/* TX packets  w/ptrs  ~8bytes hdr */
354 	struct evcnt sc_ev_txptrh1;	/* TX packets  w/ptrs ~16bytes hdr */
355 	struct evcnt sc_ev_txptrh2;	/* TX packets  w/ptrs ~32bytes hdr */
356 	struct evcnt sc_ev_txptrh3;	/* TX packets  w/ptrs ~64bytes hdr */
357 	struct evcnt sc_ev_txptrh4;	/* TX packets  w/ptrs ~80bytes hdr */
358 	struct evcnt sc_ev_txptrh5;	/* TX packets  w/ptrs ~96bytes hdr */
359 	struct evcnt sc_ev_txdstall;	/* TX stalled due to no txdesc */
360 	struct evcnt sc_ev_txempty;	/* TX empty interrupts */
361 	struct evcnt sc_ev_txsent;	/* TX sent interrupts */
362 #endif
363 };
364 
365 #define MEC_CDTXADDR(sc, x)	((sc)->sc_cddma + MEC_CDTXOFF(x))
366 #define MEC_CDRXADDR(sc, x)	((sc)->sc_cddma + MEC_CDRXOFF(x))
367 
368 #define MEC_TXDESCSYNC(sc, x, ops)					\
369 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
370 	    MEC_CDTXOFF(x), MEC_TXDESCSIZE, (ops))
371 #define MEC_TXCMDSYNC(sc, x, ops)					\
372 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
373 	    MEC_CDTXOFF(x), sizeof(uint64_t), (ops))
374 
375 #define MEC_RXSTATSYNC(sc, x, ops)					\
376 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
377 	    MEC_CDRXOFF(x), sizeof(uint64_t), (ops))
378 #define MEC_RXBUFSYNC(sc, x, len, ops)					\
379 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
380 	    MEC_CDRXOFF(x) + MEC_RXD_BUFOFFSET,				\
381 	    MEC_ETHER_ALIGN + (len), (ops))
382 
383 /* XXX these values should be moved to <net/if_ether.h> ? */
384 #define ETHER_PAD_LEN	(ETHER_MIN_LEN - ETHER_CRC_LEN)
385 #define MEC_ETHER_ALIGN	2
386 
387 static int	mec_match(device_t, cfdata_t, void *);
388 static void	mec_attach(device_t, device_t, void *);
389 
390 static int	mec_mii_readreg(device_t, int, int);
391 static void	mec_mii_writereg(device_t, int, int, int);
392 static int	mec_mii_wait(struct mec_softc *);
393 static void	mec_statchg(struct ifnet *);
394 
395 static int	mec_init(struct ifnet * ifp);
396 static void	mec_start(struct ifnet *);
397 static void	mec_watchdog(struct ifnet *);
398 static void	mec_tick(void *);
399 static int	mec_ioctl(struct ifnet *, u_long, void *);
400 static void	mec_reset(struct mec_softc *);
401 static void	mec_setfilter(struct mec_softc *);
402 static int	mec_intr(void *arg);
403 static void	mec_stop(struct ifnet *, int);
404 static void	mec_rxintr(struct mec_softc *);
405 static void	mec_rxcsum(struct mec_softc *, struct mbuf *, uint16_t,
406 		    uint32_t);
407 static void	mec_txintr(struct mec_softc *, uint32_t);
408 static bool	mec_shutdown(device_t, int);
409 
410 CFATTACH_DECL_NEW(mec, sizeof(struct mec_softc),
411     mec_match, mec_attach, NULL, NULL);
412 
413 static int mec_matched = 0;
414 
415 static int
416 mec_match(device_t parent, cfdata_t cf, void *aux)
417 {
418 
419 	/* allow only one device */
420 	if (mec_matched)
421 		return 0;
422 
423 	mec_matched = 1;
424 	return 1;
425 }
426 
427 static void
428 mec_attach(device_t parent, device_t self, void *aux)
429 {
430 	struct mec_softc *sc = device_private(self);
431 	struct mace_attach_args *maa = aux;
432 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
433 	uint64_t address, command;
434 	const char *macaddr;
435 	struct mii_softc *child;
436 	bus_dma_segment_t seg;
437 	int i, err, rseg;
438 	bool mac_is_fake;
439 
440 	sc->sc_dev = self;
441 	sc->sc_st = maa->maa_st;
442 	if (bus_space_subregion(sc->sc_st, maa->maa_sh,
443 	    maa->maa_offset, 0,	&sc->sc_sh) != 0) {
444 		aprint_error(": can't map i/o space\n");
445 		return;
446 	}
447 
448 	/* set up DMA structures */
449 	sc->sc_dmat = maa->maa_dmat;
450 
451 	/*
452 	 * Allocate the control data structures, and create and load the
453 	 * DMA map for it.
454 	 */
455 	if ((err = bus_dmamem_alloc(sc->sc_dmat,
456 	    sizeof(struct mec_control_data), MEC_CONTROL_DATA_ALIGN, 0,
457 	    &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
458 		aprint_error(": unable to allocate control data, error = %d\n",
459 		    err);
460 		goto fail_0;
461 	}
462 	/*
463 	 * XXX needs re-think...
464 	 * control data structures contain whole RX data buffer, so
465 	 * BUS_DMA_COHERENT (which disables cache) may cause some performance
466 	 * issue on copying data from the RX buffer to mbuf on normal memory,
467 	 * though we have to make sure all bus_dmamap_sync(9) ops are called
468 	 * properly in that case.
469 	 */
470 	if ((err = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
471 	    sizeof(struct mec_control_data),
472 	    (void **)&sc->sc_control_data, /*BUS_DMA_COHERENT*/ 0)) != 0) {
473 		aprint_error(": unable to map control data, error = %d\n", err);
474 		goto fail_1;
475 	}
476 	memset(sc->sc_control_data, 0, sizeof(struct mec_control_data));
477 
478 	if ((err = bus_dmamap_create(sc->sc_dmat,
479 	    sizeof(struct mec_control_data), 1,
480 	    sizeof(struct mec_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
481 		aprint_error(": unable to create control data DMA map,"
482 		    " error = %d\n", err);
483 		goto fail_2;
484 	}
485 	if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
486 	    sc->sc_control_data, sizeof(struct mec_control_data), NULL,
487 	    BUS_DMA_NOWAIT)) != 0) {
488 		aprint_error(": unable to load control data DMA map,"
489 		    " error = %d\n", err);
490 		goto fail_3;
491 	}
492 
493 	/* create TX buffer DMA maps */
494 	for (i = 0; i < MEC_NTXDESC; i++) {
495 		if ((err = bus_dmamap_create(sc->sc_dmat,
496 		    MCLBYTES, MEC_NTXSEG, MCLBYTES, PAGE_SIZE, 0,
497 		    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
498 			aprint_error(": unable to create tx DMA map %d,"
499 			    " error = %d\n", i, err);
500 			goto fail_4;
501 		}
502 	}
503 
504 	callout_init(&sc->sc_tick_ch, 0);
505 
506 	/* get Ethernet address from ARCBIOS */
507 	if ((macaddr = arcbios_GetEnvironmentVariable("eaddr")) == NULL) {
508 		aprint_error(": unable to get MAC address!\n");
509 		goto fail_4;
510 	}
511 	/*
512 	 * On some machines the DS2502 chip storing the serial number/
513 	 * mac address is on the pci riser board - if this board is
514 	 * missing, ARCBIOS will not know a good ethernet address (but
515 	 * otherwise the machine will work fine).
516 	 */
517 	mac_is_fake = false;
518 	if (strcmp(macaddr, "ff:ff:ff:ff:ff:ff") == 0) {
519 		uint32_t ui = 0;
520 		const char * netaddr =
521 			arcbios_GetEnvironmentVariable("netaddr");
522 
523 		/*
524 		 * Create a MAC address by abusing the "netaddr" env var
525 		 */
526 		sc->sc_enaddr[0] = 0xf2;
527 		sc->sc_enaddr[1] = 0x0b;
528 		sc->sc_enaddr[2] = 0xa4;
529 		if (netaddr) {
530 			mac_is_fake = true;
531 			while (*netaddr) {
532 				int v = 0;
533 				while (*netaddr && *netaddr != '.') {
534 					if (*netaddr >= '0' && *netaddr <= '9')
535 						v = v*10 + (*netaddr - '0');
536 					netaddr++;
537 				}
538 				ui <<= 8;
539 				ui |= v;
540 				if (*netaddr == '.')
541 					netaddr++;
542 			}
543 		}
544 		memcpy(sc->sc_enaddr+3, ((uint8_t *)&ui)+1, 3);
545 	}
546 	if (!mac_is_fake)
547 		ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr);
548 
549 	/* set the Ethernet address */
550 	address = 0;
551 	for (i = 0; i < ETHER_ADDR_LEN; i++) {
552 		address = address << 8;
553 		address |= sc->sc_enaddr[i];
554 	}
555 	bus_space_write_8(sc->sc_st, sc->sc_sh, MEC_STATION, address);
556 
557 	/* reset device */
558 	mec_reset(sc);
559 
560 	command = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_MAC_CONTROL);
561 
562 	aprint_normal(": MAC-110 Ethernet, rev %u\n",
563 	    (u_int)((command & MEC_MAC_REVISION) >> MEC_MAC_REVISION_SHIFT));
564 
565 	if (mac_is_fake)
566 		aprint_normal_dev(self,
567 		    "could not get ethernet address from firmware"
568 		    " - generated one from the \"netaddr\" environment"
569 		    " variable\n");
570 	aprint_normal_dev(self, "Ethernet address %s\n",
571 	    ether_sprintf(sc->sc_enaddr));
572 
573 	/* Done, now attach everything */
574 
575 	sc->sc_mii.mii_ifp = ifp;
576 	sc->sc_mii.mii_readreg = mec_mii_readreg;
577 	sc->sc_mii.mii_writereg = mec_mii_writereg;
578 	sc->sc_mii.mii_statchg = mec_statchg;
579 
580 	/* Set up PHY properties */
581 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
582 	ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange,
583 	    ether_mediastatus);
584 	mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
585 	    MII_OFFSET_ANY, 0);
586 
587 	child = LIST_FIRST(&sc->sc_mii.mii_phys);
588 	if (child == NULL) {
589 		/* No PHY attached */
590 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL,
591 		    0, NULL);
592 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_MANUAL);
593 	} else {
594 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
595 		sc->sc_phyaddr = child->mii_phy;
596 	}
597 
598 	strcpy(ifp->if_xname, device_xname(self));
599 	ifp->if_softc = sc;
600 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
601 	ifp->if_ioctl = mec_ioctl;
602 	ifp->if_start = mec_start;
603 	ifp->if_watchdog = mec_watchdog;
604 	ifp->if_init = mec_init;
605 	ifp->if_stop = mec_stop;
606 	ifp->if_mtu = ETHERMTU;
607 	IFQ_SET_READY(&ifp->if_snd);
608 
609 	/* mec has dumb RX cksum support */
610 	ifp->if_capabilities = IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx;
611 
612 	/* We can support 802.1Q VLAN-sized frames. */
613 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
614 
615 	/* attach the interface */
616 	if_attach(ifp);
617 	if_deferred_start_init(ifp, NULL);
618 	ether_ifattach(ifp, sc->sc_enaddr);
619 
620 	/* establish interrupt */
621 	cpu_intr_establish(maa->maa_intr, maa->maa_intrmask, mec_intr, sc);
622 
623 	rnd_attach_source(&sc->sc_rnd_source, device_xname(self),
624 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
625 
626 #ifdef MEC_EVENT_COUNTERS
627 	evcnt_attach_dynamic(&sc->sc_ev_txpkts , EVCNT_TYPE_MISC,
628 	    NULL, device_xname(self), "TX pkts queued total");
629 	evcnt_attach_dynamic(&sc->sc_ev_txdpad , EVCNT_TYPE_MISC,
630 	    NULL, device_xname(self), "TX pkts padded in txdesc buf");
631 	evcnt_attach_dynamic(&sc->sc_ev_txdbuf , EVCNT_TYPE_MISC,
632 	    NULL, device_xname(self), "TX pkts copied to txdesc buf");
633 	evcnt_attach_dynamic(&sc->sc_ev_txptr1 , EVCNT_TYPE_MISC,
634 	    NULL, device_xname(self), "TX pkts using concat ptr1");
635 	evcnt_attach_dynamic(&sc->sc_ev_txptr1a , EVCNT_TYPE_MISC,
636 	    NULL, device_xname(self), "TX pkts  w/ptr1  ~160bytes");
637 	evcnt_attach_dynamic(&sc->sc_ev_txptr1b , EVCNT_TYPE_MISC,
638 	    NULL, device_xname(self), "TX pkts  w/ptr1  ~256bytes");
639 	evcnt_attach_dynamic(&sc->sc_ev_txptr1c , EVCNT_TYPE_MISC,
640 	    NULL, device_xname(self), "TX pkts  w/ptr1  ~512bytes");
641 	evcnt_attach_dynamic(&sc->sc_ev_txptr1d , EVCNT_TYPE_MISC,
642 	    NULL, device_xname(self), "TX pkts  w/ptr1 ~1024bytes");
643 	evcnt_attach_dynamic(&sc->sc_ev_txptr1e , EVCNT_TYPE_MISC,
644 	    NULL, device_xname(self), "TX pkts  w/ptr1 >1024bytes");
645 	evcnt_attach_dynamic(&sc->sc_ev_txptr2 , EVCNT_TYPE_MISC,
646 	    NULL, device_xname(self), "TX pkts using concat ptr1,2");
647 	evcnt_attach_dynamic(&sc->sc_ev_txptr2a , EVCNT_TYPE_MISC,
648 	    NULL, device_xname(self), "TX pkts  w/ptr2  ~160bytes");
649 	evcnt_attach_dynamic(&sc->sc_ev_txptr2b , EVCNT_TYPE_MISC,
650 	    NULL, device_xname(self), "TX pkts  w/ptr2  ~256bytes");
651 	evcnt_attach_dynamic(&sc->sc_ev_txptr2c , EVCNT_TYPE_MISC,
652 	    NULL, device_xname(self), "TX pkts  w/ptr2  ~512bytes");
653 	evcnt_attach_dynamic(&sc->sc_ev_txptr2d , EVCNT_TYPE_MISC,
654 	    NULL, device_xname(self), "TX pkts  w/ptr2 ~1024bytes");
655 	evcnt_attach_dynamic(&sc->sc_ev_txptr2e , EVCNT_TYPE_MISC,
656 	    NULL, device_xname(self), "TX pkts  w/ptr2 >1024bytes");
657 	evcnt_attach_dynamic(&sc->sc_ev_txptr3 , EVCNT_TYPE_MISC,
658 	    NULL, device_xname(self), "TX pkts using concat ptr1,2,3");
659 	evcnt_attach_dynamic(&sc->sc_ev_txptr3a , EVCNT_TYPE_MISC,
660 	    NULL, device_xname(self), "TX pkts  w/ptr3  ~160bytes");
661 	evcnt_attach_dynamic(&sc->sc_ev_txptr3b , EVCNT_TYPE_MISC,
662 	    NULL, device_xname(self), "TX pkts  w/ptr3  ~256bytes");
663 	evcnt_attach_dynamic(&sc->sc_ev_txptr3c , EVCNT_TYPE_MISC,
664 	    NULL, device_xname(self), "TX pkts  w/ptr3  ~512bytes");
665 	evcnt_attach_dynamic(&sc->sc_ev_txptr3d , EVCNT_TYPE_MISC,
666 	    NULL, device_xname(self), "TX pkts  w/ptr3 ~1024bytes");
667 	evcnt_attach_dynamic(&sc->sc_ev_txptr3e , EVCNT_TYPE_MISC,
668 	    NULL, device_xname(self), "TX pkts  w/ptr3 >1024bytes");
669 	evcnt_attach_dynamic(&sc->sc_ev_txmbuf , EVCNT_TYPE_MISC,
670 	    NULL, device_xname(self), "TX pkts copied to new mbufs");
671 	evcnt_attach_dynamic(&sc->sc_ev_txmbufa , EVCNT_TYPE_MISC,
672 	    NULL, device_xname(self), "TX pkts  w/mbuf  ~160bytes");
673 	evcnt_attach_dynamic(&sc->sc_ev_txmbufb , EVCNT_TYPE_MISC,
674 	    NULL, device_xname(self), "TX pkts  w/mbuf  ~256bytes");
675 	evcnt_attach_dynamic(&sc->sc_ev_txmbufc , EVCNT_TYPE_MISC,
676 	    NULL, device_xname(self), "TX pkts  w/mbuf  ~512bytes");
677 	evcnt_attach_dynamic(&sc->sc_ev_txmbufd , EVCNT_TYPE_MISC,
678 	    NULL, device_xname(self), "TX pkts  w/mbuf ~1024bytes");
679 	evcnt_attach_dynamic(&sc->sc_ev_txmbufe , EVCNT_TYPE_MISC,
680 	    NULL, device_xname(self), "TX pkts  w/mbuf >1024bytes");
681 	evcnt_attach_dynamic(&sc->sc_ev_txptrs , EVCNT_TYPE_MISC,
682 	    NULL, device_xname(self), "TX pkts using ptrs total");
683 	evcnt_attach_dynamic(&sc->sc_ev_txptrc0 , EVCNT_TYPE_MISC,
684 	    NULL, device_xname(self), "TX pkts  w/ptrs no hdr chain");
685 	evcnt_attach_dynamic(&sc->sc_ev_txptrc1 , EVCNT_TYPE_MISC,
686 	    NULL, device_xname(self), "TX pkts  w/ptrs  1 hdr chain");
687 	evcnt_attach_dynamic(&sc->sc_ev_txptrc2 , EVCNT_TYPE_MISC,
688 	    NULL, device_xname(self), "TX pkts  w/ptrs  2 hdr chains");
689 	evcnt_attach_dynamic(&sc->sc_ev_txptrc3 , EVCNT_TYPE_MISC,
690 	    NULL, device_xname(self), "TX pkts  w/ptrs  3 hdr chains");
691 	evcnt_attach_dynamic(&sc->sc_ev_txptrc4 , EVCNT_TYPE_MISC,
692 	    NULL, device_xname(self), "TX pkts  w/ptrs  4 hdr chains");
693 	evcnt_attach_dynamic(&sc->sc_ev_txptrc5 , EVCNT_TYPE_MISC,
694 	    NULL, device_xname(self), "TX pkts  w/ptrs  5 hdr chains");
695 	evcnt_attach_dynamic(&sc->sc_ev_txptrc6 , EVCNT_TYPE_MISC,
696 	    NULL, device_xname(self), "TX pkts  w/ptrs >5 hdr chains");
697 	evcnt_attach_dynamic(&sc->sc_ev_txptrh0 , EVCNT_TYPE_MISC,
698 	    NULL, device_xname(self), "TX pkts  w/ptrs  ~8bytes hdr");
699 	evcnt_attach_dynamic(&sc->sc_ev_txptrh1 , EVCNT_TYPE_MISC,
700 	    NULL, device_xname(self), "TX pkts  w/ptrs ~16bytes hdr");
701 	evcnt_attach_dynamic(&sc->sc_ev_txptrh2 , EVCNT_TYPE_MISC,
702 	    NULL, device_xname(self), "TX pkts  w/ptrs ~32bytes hdr");
703 	evcnt_attach_dynamic(&sc->sc_ev_txptrh3 , EVCNT_TYPE_MISC,
704 	    NULL, device_xname(self), "TX pkts  w/ptrs ~64bytes hdr");
705 	evcnt_attach_dynamic(&sc->sc_ev_txptrh4 , EVCNT_TYPE_MISC,
706 	    NULL, device_xname(self), "TX pkts  w/ptrs ~80bytes hdr");
707 	evcnt_attach_dynamic(&sc->sc_ev_txptrh5 , EVCNT_TYPE_MISC,
708 	    NULL, device_xname(self), "TX pkts  w/ptrs ~96bytes hdr");
709 	evcnt_attach_dynamic(&sc->sc_ev_txdstall , EVCNT_TYPE_MISC,
710 	    NULL, device_xname(self), "TX stalled due to no txdesc");
711 	evcnt_attach_dynamic(&sc->sc_ev_txempty , EVCNT_TYPE_MISC,
712 	    NULL, device_xname(self), "TX empty interrupts");
713 	evcnt_attach_dynamic(&sc->sc_ev_txsent , EVCNT_TYPE_MISC,
714 	    NULL, device_xname(self), "TX sent interrupts");
715 #endif
716 
717 	/* set shutdown hook to reset interface on powerdown */
718 	if (pmf_device_register1(self, NULL, NULL, mec_shutdown))
719 		pmf_class_network_register(self, ifp);
720 	else
721 		aprint_error_dev(self, "couldn't establish power handler\n");
722 
723 	return;
724 
725 	/*
726 	 * Free any resources we've allocated during the failed attach
727 	 * attempt.  Do this in reverse order and fall though.
728 	 */
729  fail_4:
730 	for (i = 0; i < MEC_NTXDESC; i++) {
731 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
732 			bus_dmamap_destroy(sc->sc_dmat,
733 			    sc->sc_txsoft[i].txs_dmamap);
734 	}
735 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
736  fail_3:
737 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
738  fail_2:
739 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
740 	    sizeof(struct mec_control_data));
741  fail_1:
742 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
743  fail_0:
744 	return;
745 }
746 
747 static int
748 mec_mii_readreg(device_t self, int phy, int reg)
749 {
750 	struct mec_softc *sc = device_private(self);
751 	bus_space_tag_t st = sc->sc_st;
752 	bus_space_handle_t sh = sc->sc_sh;
753 	uint64_t val;
754 	int i;
755 
756 	if (mec_mii_wait(sc) != 0)
757 		return 0;
758 
759 	bus_space_write_8(st, sh, MEC_PHY_ADDRESS,
760 	    (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER));
761 	delay(25);
762 	bus_space_write_8(st, sh, MEC_PHY_READ_INITIATE, 1);
763 	delay(25);
764 	mec_mii_wait(sc);
765 
766 	for (i = 0; i < 20; i++) {
767 		delay(30);
768 
769 		val = bus_space_read_8(st, sh, MEC_PHY_DATA);
770 
771 		if ((val & MEC_PHY_DATA_BUSY) == 0)
772 			return val & MEC_PHY_DATA_VALUE;
773 	}
774 	return 0;
775 }
776 
777 static void
778 mec_mii_writereg(device_t self, int phy, int reg, int val)
779 {
780 	struct mec_softc *sc = device_private(self);
781 	bus_space_tag_t st = sc->sc_st;
782 	bus_space_handle_t sh = sc->sc_sh;
783 
784 	if (mec_mii_wait(sc) != 0) {
785 		printf("timed out writing %x: %x\n", reg, val);
786 		return;
787 	}
788 
789 	bus_space_write_8(st, sh, MEC_PHY_ADDRESS,
790 	    (phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER));
791 
792 	delay(60);
793 
794 	bus_space_write_8(st, sh, MEC_PHY_DATA, val & MEC_PHY_DATA_VALUE);
795 
796 	delay(60);
797 
798 	mec_mii_wait(sc);
799 }
800 
801 static int
802 mec_mii_wait(struct mec_softc *sc)
803 {
804 	uint32_t busy;
805 	int i, s;
806 
807 	for (i = 0; i < 100; i++) {
808 		delay(30);
809 
810 		s = splhigh();
811 		busy = bus_space_read_8(sc->sc_st, sc->sc_sh, MEC_PHY_DATA);
812 		splx(s);
813 
814 		if ((busy & MEC_PHY_DATA_BUSY) == 0)
815 			return 0;
816 #if 0
817 		if (busy == 0xffff) /* XXX ? */
818 			return 0;
819 #endif
820 	}
821 
822 	printf("%s: MII timed out\n", device_xname(sc->sc_dev));
823 	return 1;
824 }
825 
826 static void
827 mec_statchg(struct ifnet *ifp)
828 {
829 	struct mec_softc *sc = ifp->if_softc;
830 	bus_space_tag_t st = sc->sc_st;
831 	bus_space_handle_t sh = sc->sc_sh;
832 	uint32_t control;
833 
834 	control = bus_space_read_8(st, sh, MEC_MAC_CONTROL);
835 	control &= ~(MEC_MAC_IPGT | MEC_MAC_IPGR1 | MEC_MAC_IPGR2 |
836 	    MEC_MAC_FULL_DUPLEX | MEC_MAC_SPEED_SELECT);
837 
838 	/* must also set IPG here for duplex stuff ... */
839 	if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) {
840 		control |= MEC_MAC_FULL_DUPLEX;
841 	} else {
842 		/* set IPG */
843 		control |= MEC_MAC_IPG_DEFAULT;
844 	}
845 
846 	bus_space_write_8(st, sh, MEC_MAC_CONTROL, control);
847 }
848 
849 static int
850 mec_init(struct ifnet *ifp)
851 {
852 	struct mec_softc *sc = ifp->if_softc;
853 	bus_space_tag_t st = sc->sc_st;
854 	bus_space_handle_t sh = sc->sc_sh;
855 	struct mec_rxdesc *rxd;
856 	int i, rc;
857 
858 	/* cancel any pending I/O */
859 	mec_stop(ifp, 0);
860 
861 	/* reset device */
862 	mec_reset(sc);
863 
864 	/* setup filter for multicast or promisc mode */
865 	mec_setfilter(sc);
866 
867 	/* set the TX ring pointer to the base address */
868 	bus_space_write_8(st, sh, MEC_TX_RING_BASE, MEC_CDTXADDR(sc, 0));
869 
870 	sc->sc_txpending = 0;
871 	sc->sc_txdirty = 0;
872 	sc->sc_txlast = MEC_NTXDESC - 1;
873 
874 	/* put RX buffers into FIFO */
875 	for (i = 0; i < MEC_NRXDESC; i++) {
876 		rxd = &sc->sc_rxdesc[i];
877 		rxd->rxd_stat = 0;
878 		MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);
879 		MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD);
880 		bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i));
881 	}
882 	sc->sc_rxptr = 0;
883 
884 #if 0	/* XXX no info */
885 	bus_space_write_8(st, sh, MEC_TIMER, 0);
886 #endif
887 
888 	/*
889 	 * MEC_DMA_TX_INT_ENABLE will be set later otherwise it causes
890 	 * spurious interrupts when TX buffers are empty
891 	 */
892 	bus_space_write_8(st, sh, MEC_DMA_CONTROL,
893 	    (MEC_RXD_DMAOFFSET << MEC_DMA_RX_DMA_OFFSET_SHIFT) |
894 	    (MEC_NRXDESC << MEC_DMA_RX_INT_THRESH_SHIFT) |
895 	    MEC_DMA_TX_DMA_ENABLE | /* MEC_DMA_TX_INT_ENABLE | */
896 	    MEC_DMA_RX_DMA_ENABLE | MEC_DMA_RX_INT_ENABLE);
897 
898 	callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc);
899 
900 	if ((rc = ether_mediachange(ifp)) != 0)
901 		return rc;
902 
903 	ifp->if_flags |= IFF_RUNNING;
904 	ifp->if_flags &= ~IFF_OACTIVE;
905 	mec_start(ifp);
906 
907 	return 0;
908 }
909 
910 static void
911 mec_reset(struct mec_softc *sc)
912 {
913 	bus_space_tag_t st = sc->sc_st;
914 	bus_space_handle_t sh = sc->sc_sh;
915 	uint64_t control;
916 
917 	/* stop DMA first */
918 	bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0);
919 
920 	/* reset chip */
921 	bus_space_write_8(st, sh, MEC_MAC_CONTROL, MEC_MAC_CORE_RESET);
922 	delay(1000);
923 	bus_space_write_8(st, sh, MEC_MAC_CONTROL, 0);
924 	delay(1000);
925 
926 	/* Default to 100/half and let auto-negotiation work its magic */
927 	control = MEC_MAC_SPEED_SELECT | MEC_MAC_FILTER_MATCHMULTI |
928 	    MEC_MAC_IPG_DEFAULT;
929 
930 	bus_space_write_8(st, sh, MEC_MAC_CONTROL, control);
931 	/* stop DMA again for sanity */
932 	bus_space_write_8(st, sh, MEC_DMA_CONTROL, 0);
933 
934 	DPRINTF(MEC_DEBUG_RESET, ("mec: control now %llx\n",
935 	    bus_space_read_8(st, sh, MEC_MAC_CONTROL)));
936 }
937 
938 static void
939 mec_start(struct ifnet *ifp)
940 {
941 	struct mec_softc *sc = ifp->if_softc;
942 	struct mbuf *m0, *m;
943 	struct mec_txdesc *txd;
944 	struct mec_txsoft *txs;
945 	bus_dmamap_t dmamap;
946 	bus_space_tag_t st = sc->sc_st;
947 	bus_space_handle_t sh = sc->sc_sh;
948 	int error, firsttx, nexttx, opending;
949 	int len, bufoff, buflen, nsegs, align, resid, pseg, nptr, slen, i;
950 	uint32_t txdcmd;
951 
952 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
953 		return;
954 
955 	/*
956 	 * Remember the previous txpending and the first transmit descriptor.
957 	 */
958 	opending = sc->sc_txpending;
959 	firsttx = MEC_NEXTTX(sc->sc_txlast);
960 
961 	DPRINTF(MEC_DEBUG_START,
962 	    ("%s: opending = %d, firsttx = %d\n", __func__, opending, firsttx));
963 
964 	while (sc->sc_txpending < MEC_NTXDESC - 1) {
965 		/* Grab a packet off the queue. */
966 		IFQ_POLL(&ifp->if_snd, m0);
967 		if (m0 == NULL)
968 			break;
969 		m = NULL;
970 
971 		/*
972 		 * Get the next available transmit descriptor.
973 		 */
974 		nexttx = MEC_NEXTTX(sc->sc_txlast);
975 		txd = &sc->sc_txdesc[nexttx];
976 		txs = &sc->sc_txsoft[nexttx];
977 		dmamap = txs->txs_dmamap;
978 		txs->txs_flags = 0;
979 
980 		buflen = 0;
981 		bufoff = 0;
982 		resid = 0;
983 		nptr = 0;	/* XXX gcc */
984 		pseg = 0;	/* XXX gcc */
985 
986 		len = m0->m_pkthdr.len;
987 
988 		DPRINTF(MEC_DEBUG_START,
989 		    ("%s: len = %d, nexttx = %d, txpending = %d\n",
990 		    __func__, len, nexttx, sc->sc_txpending));
991 
992 		if (len <= MEC_TXD_BUFSIZE) {
993 			/*
994 			 * If a TX packet will fit into small txdesc buffer,
995 			 * just copy it into there. Maybe it's faster than
996 			 * checking alignment and calling bus_dma(9) etc.
997 			 */
998 			DPRINTF(MEC_DEBUG_START, ("%s: short packet\n",
999 			    __func__));
1000 			IFQ_DEQUEUE(&ifp->if_snd, m0);
1001 
1002 			/*
1003 			 * I don't know if MEC chip does auto padding,
1004 			 * but do it manually for safety.
1005 			 */
1006 			if (len < ETHER_PAD_LEN) {
1007 				MEC_EVCNT_INCR(&sc->sc_ev_txdpad);
1008 				bufoff = MEC_TXD_BUFSTART(ETHER_PAD_LEN);
1009 				m_copydata(m0, 0, len, txd->txd_buf + bufoff);
1010 				memset(txd->txd_buf + bufoff + len, 0,
1011 				    ETHER_PAD_LEN - len);
1012 				len = buflen = ETHER_PAD_LEN;
1013 			} else {
1014 				MEC_EVCNT_INCR(&sc->sc_ev_txdbuf);
1015 				bufoff = MEC_TXD_BUFSTART(len);
1016 				m_copydata(m0, 0, len, txd->txd_buf + bufoff);
1017 				buflen = len;
1018 			}
1019 		} else {
1020 			/*
1021 			 * If the packet won't fit the static buffer in txdesc,
1022 			 * we have to use the concatenate pointers to handle it.
1023 			 */
1024 			DPRINTF(MEC_DEBUG_START, ("%s: long packet\n",
1025 			    __func__));
1026 			txs->txs_flags = MEC_TXS_TXDPTR;
1027 
1028 			/*
1029 			 * Call bus_dmamap_load_mbuf(9) first to see
1030 			 * how many chains the TX mbuf has.
1031 			 */
1032 			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
1033 			    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1034 			if (error == 0) {
1035 				/*
1036 				 * Check chains which might contain headers.
1037 				 * They might be so much fragmented and
1038 				 * it's better to copy them into txdesc buffer
1039 				 * since they would be small enough.
1040 				 */
1041 				nsegs = dmamap->dm_nsegs;
1042 				for (pseg = 0; pseg < nsegs; pseg++) {
1043 					slen = dmamap->dm_segs[pseg].ds_len;
1044 					if (buflen + slen >
1045 					    MEC_TXD_BUFSIZE1 - MEC_TXD_ALIGN)
1046 						break;
1047 					buflen += slen;
1048 				}
1049 				/*
1050 				 * Check if the rest chains can be fit into
1051 				 * the concatinate pointers.
1052 				 */
1053 				align = dmamap->dm_segs[pseg].ds_addr &
1054 				    MEC_TXD_ALIGNMASK;
1055 				if (align > 0) {
1056 					/*
1057 					 * If the first chain isn't uint64_t
1058 					 * aligned, append the unaligned part
1059 					 * into txdesc buffer too.
1060 					 */
1061 					resid = MEC_TXD_ALIGN - align;
1062 					buflen += resid;
1063 					for (; pseg < nsegs; pseg++) {
1064 						slen =
1065 						  dmamap->dm_segs[pseg].ds_len;
1066 						if (slen > resid)
1067 							break;
1068 						resid -= slen;
1069 					}
1070 				} else if (pseg == 0) {
1071 					/*
1072 					 * In this case, the first chain is
1073 					 * uint64_t aligned but it's too long
1074 					 * to put into txdesc buf.
1075 					 * We have to put some data into
1076 					 * txdesc buf even in this case,
1077 					 * so put MEC_TXD_ALIGN bytes there.
1078 					 */
1079 					buflen = resid = MEC_TXD_ALIGN;
1080 				}
1081 				nptr = nsegs - pseg;
1082 				if (nptr <= MEC_NTXPTR) {
1083 					bufoff = MEC_TXD_BUFSTART(buflen);
1084 
1085 					/*
1086 					 * Check if all the rest chains are
1087 					 * uint64_t aligned.
1088 					 */
1089 					align = 0;
1090 					for (i = pseg + 1; i < nsegs; i++)
1091 						align |=
1092 						    dmamap->dm_segs[i].ds_addr
1093 						    & MEC_TXD_ALIGNMASK;
1094 					if (align != 0) {
1095 						/* chains are not aligned */
1096 						error = -1;
1097 					}
1098 				} else {
1099 					/* The TX mbuf chains doesn't fit. */
1100 					error = -1;
1101 				}
1102 				if (error == -1)
1103 					bus_dmamap_unload(sc->sc_dmat, dmamap);
1104 			}
1105 			if (error != 0) {
1106 				/*
1107 				 * The TX mbuf chains can't be put into
1108 				 * the concatinate buffers. In this case,
1109 				 * we have to allocate a new contiguous mbuf
1110 				 * and copy data into it.
1111 				 *
1112 				 * Even in this case, the Ethernet header in
1113 				 * the TX mbuf might be unaligned and trailing
1114 				 * data might be word aligned, so put 2 byte
1115 				 * (MEC_ETHER_ALIGN) padding at the top of the
1116 				 * allocated mbuf and copy TX packets.
1117 				 * 6 bytes (MEC_ALIGN_BYTES - MEC_ETHER_ALIGN)
1118 				 * at the top of the new mbuf won't be uint64_t
1119 				 * alignd, but we have to put some data into
1120 				 * txdesc buffer anyway even if the buffer
1121 				 * is uint64_t aligned.
1122 				 */
1123 				DPRINTF(MEC_DEBUG_START|MEC_DEBUG_TXSEGS,
1124 				    ("%s: re-allocating mbuf\n", __func__));
1125 
1126 				MGETHDR(m, M_DONTWAIT, MT_DATA);
1127 				if (m == NULL) {
1128 					printf("%s: unable to allocate "
1129 					    "TX mbuf\n",
1130 					    device_xname(sc->sc_dev));
1131 					break;
1132 				}
1133 				if (len > (MHLEN - MEC_ETHER_ALIGN)) {
1134 					MCLGET(m, M_DONTWAIT);
1135 					if ((m->m_flags & M_EXT) == 0) {
1136 						printf("%s: unable to allocate "
1137 						    "TX cluster\n",
1138 						    device_xname(sc->sc_dev));
1139 						m_freem(m);
1140 						break;
1141 					}
1142 				}
1143 				m->m_data += MEC_ETHER_ALIGN;
1144 
1145 				/*
1146 				 * Copy whole data (including unaligned part)
1147 				 * for following bpf_mtap().
1148 				 */
1149 				m_copydata(m0, 0, len, mtod(m, void *));
1150 				m->m_pkthdr.len = m->m_len = len;
1151 				error = bus_dmamap_load_mbuf(sc->sc_dmat,
1152 				    dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1153 				if (dmamap->dm_nsegs > 1) {
1154 					/* should not happen, but for sanity */
1155 					bus_dmamap_unload(sc->sc_dmat, dmamap);
1156 					error = -1;
1157 				}
1158 				if (error != 0) {
1159 					printf("%s: unable to load TX buffer, "
1160 					    "error = %d\n",
1161 					    device_xname(sc->sc_dev), error);
1162 					m_freem(m);
1163 					break;
1164 				}
1165 				/*
1166 				 * Only the first segment should be put into
1167 				 * the concatinate pointer in this case.
1168 				 */
1169 				pseg = 0;
1170 				nptr = 1;
1171 
1172 				/*
1173 				 * Set lenght of unaligned part which will be
1174 				 * copied into txdesc buffer.
1175 				 */
1176 				buflen = MEC_TXD_ALIGN - MEC_ETHER_ALIGN;
1177 				bufoff = MEC_TXD_BUFSTART(buflen);
1178 				resid = buflen;
1179 #ifdef MEC_EVENT_COUNTERS
1180 				MEC_EVCNT_INCR(&sc->sc_ev_txmbuf);
1181 				if (len <= 160)
1182 					MEC_EVCNT_INCR(&sc->sc_ev_txmbufa);
1183 				else if (len <= 256)
1184 					MEC_EVCNT_INCR(&sc->sc_ev_txmbufb);
1185 				else if (len <= 512)
1186 					MEC_EVCNT_INCR(&sc->sc_ev_txmbufc);
1187 				else if (len <= 1024)
1188 					MEC_EVCNT_INCR(&sc->sc_ev_txmbufd);
1189 				else
1190 					MEC_EVCNT_INCR(&sc->sc_ev_txmbufe);
1191 #endif
1192 			}
1193 #ifdef MEC_EVENT_COUNTERS
1194 			else {
1195 				MEC_EVCNT_INCR(&sc->sc_ev_txptrs);
1196 				if (nptr == 1) {
1197 					MEC_EVCNT_INCR(&sc->sc_ev_txptr1);
1198 					if (len <= 160)
1199 						MEC_EVCNT_INCR(
1200 						    &sc->sc_ev_txptr1a);
1201 					else if (len <= 256)
1202 						MEC_EVCNT_INCR(
1203 						    &sc->sc_ev_txptr1b);
1204 					else if (len <= 512)
1205 						MEC_EVCNT_INCR(
1206 						    &sc->sc_ev_txptr1c);
1207 					else if (len <= 1024)
1208 						MEC_EVCNT_INCR(
1209 						    &sc->sc_ev_txptr1d);
1210 					else
1211 						MEC_EVCNT_INCR(
1212 						    &sc->sc_ev_txptr1e);
1213 				} else if (nptr == 2) {
1214 					MEC_EVCNT_INCR(&sc->sc_ev_txptr2);
1215 					if (len <= 160)
1216 						MEC_EVCNT_INCR(
1217 						    &sc->sc_ev_txptr2a);
1218 					else if (len <= 256)
1219 						MEC_EVCNT_INCR(
1220 						    &sc->sc_ev_txptr2b);
1221 					else if (len <= 512)
1222 						MEC_EVCNT_INCR(
1223 						    &sc->sc_ev_txptr2c);
1224 					else if (len <= 1024)
1225 						MEC_EVCNT_INCR(
1226 						    &sc->sc_ev_txptr2d);
1227 					else
1228 						MEC_EVCNT_INCR(
1229 						    &sc->sc_ev_txptr2e);
1230 				} else if (nptr == 3) {
1231 					MEC_EVCNT_INCR(&sc->sc_ev_txptr3);
1232 					if (len <= 160)
1233 						MEC_EVCNT_INCR(
1234 						    &sc->sc_ev_txptr3a);
1235 					else if (len <= 256)
1236 						MEC_EVCNT_INCR(
1237 						    &sc->sc_ev_txptr3b);
1238 					else if (len <= 512)
1239 						MEC_EVCNT_INCR(
1240 						    &sc->sc_ev_txptr3c);
1241 					else if (len <= 1024)
1242 						MEC_EVCNT_INCR(
1243 						    &sc->sc_ev_txptr3d);
1244 					else
1245 						MEC_EVCNT_INCR(
1246 						    &sc->sc_ev_txptr3e);
1247 				}
1248 				if (pseg == 0)
1249 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc0);
1250 				else if (pseg == 1)
1251 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc1);
1252 				else if (pseg == 2)
1253 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc2);
1254 				else if (pseg == 3)
1255 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc3);
1256 				else if (pseg == 4)
1257 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc4);
1258 				else if (pseg == 5)
1259 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc5);
1260 				else
1261 					MEC_EVCNT_INCR(&sc->sc_ev_txptrc6);
1262 				if (buflen <= 8)
1263 					MEC_EVCNT_INCR(&sc->sc_ev_txptrh0);
1264 				else if (buflen <= 16)
1265 					MEC_EVCNT_INCR(&sc->sc_ev_txptrh1);
1266 				else if (buflen <= 32)
1267 					MEC_EVCNT_INCR(&sc->sc_ev_txptrh2);
1268 				else if (buflen <= 64)
1269 					MEC_EVCNT_INCR(&sc->sc_ev_txptrh3);
1270 				else if (buflen <= 80)
1271 					MEC_EVCNT_INCR(&sc->sc_ev_txptrh4);
1272 				else
1273 					MEC_EVCNT_INCR(&sc->sc_ev_txptrh5);
1274 			}
1275 #endif
1276 			m_copydata(m0, 0, buflen, txd->txd_buf + bufoff);
1277 
1278 			IFQ_DEQUEUE(&ifp->if_snd, m0);
1279 			if (m != NULL) {
1280 				m_freem(m0);
1281 				m0 = m;
1282 			}
1283 
1284 			/*
1285 			 * sync the DMA map for TX mbuf
1286 			 */
1287 			bus_dmamap_sync(sc->sc_dmat, dmamap, buflen,
1288 			    len - buflen, BUS_DMASYNC_PREWRITE);
1289 		}
1290 
1291 		/*
1292 		 * Pass packet to bpf if there is a listener.
1293 		 */
1294 		bpf_mtap(ifp, m0, BPF_D_OUT);
1295 		MEC_EVCNT_INCR(&sc->sc_ev_txpkts);
1296 
1297 		/*
1298 		 * setup the transmit descriptor.
1299 		 */
1300 		txdcmd = TXCMD_BUFSTART(MEC_TXDESCSIZE - buflen) | (len - 1);
1301 
1302 		/*
1303 		 * Set MEC_TXCMD_TXINT every MEC_NTXDESC_INTR packets
1304 		 * if more than half txdescs have been queued
1305 		 * because TX_EMPTY interrupts will rarely happen
1306 		 * if TX queue is so stacked.
1307 		 */
1308 		if (sc->sc_txpending > (MEC_NTXDESC / 2) &&
1309 		    (nexttx & (MEC_NTXDESC_INTR - 1)) == 0)
1310 			txdcmd |= MEC_TXCMD_TXINT;
1311 
1312 		if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) {
1313 			bus_dma_segment_t *segs = dmamap->dm_segs;
1314 
1315 			DPRINTF(MEC_DEBUG_TXSEGS,
1316 			    ("%s: nsegs = %d, pseg = %d, nptr = %d\n",
1317 			    __func__, dmamap->dm_nsegs, pseg, nptr));
1318 
1319 			switch (nptr) {
1320 			case 3:
1321 				KASSERT((segs[pseg + 2].ds_addr &
1322 				    MEC_TXD_ALIGNMASK) == 0);
1323 				txdcmd |= MEC_TXCMD_PTR3;
1324 				txd->txd_ptr[2] =
1325 				    TXPTR_LEN(segs[pseg + 2].ds_len - 1) |
1326 				    segs[pseg + 2].ds_addr;
1327 				/* FALLTHROUGH */
1328 			case 2:
1329 				KASSERT((segs[pseg + 1].ds_addr &
1330 				    MEC_TXD_ALIGNMASK) == 0);
1331 				txdcmd |= MEC_TXCMD_PTR2;
1332 				txd->txd_ptr[1] =
1333 				    TXPTR_LEN(segs[pseg + 1].ds_len - 1) |
1334 				    segs[pseg + 1].ds_addr;
1335 				/* FALLTHROUGH */
1336 			case 1:
1337 				txdcmd |= MEC_TXCMD_PTR1;
1338 				txd->txd_ptr[0] =
1339 				    TXPTR_LEN(segs[pseg].ds_len - resid - 1) |
1340 				    (segs[pseg].ds_addr + resid);
1341 				break;
1342 			default:
1343 				panic("%s: impossible nptr in %s",
1344 				    device_xname(sc->sc_dev), __func__);
1345 				/* NOTREACHED */
1346 			}
1347 			/*
1348 			 * Store a pointer to the packet so we can
1349 			 * free it later.
1350 			 */
1351 			txs->txs_mbuf = m0;
1352 		} else {
1353 			/*
1354 			 * In this case all data are copied to buffer in txdesc,
1355 			 * we can free TX mbuf here.
1356 			 */
1357 			m_freem(m0);
1358 		}
1359 		txd->txd_cmd = txdcmd;
1360 
1361 		DPRINTF(MEC_DEBUG_START,
1362 		    ("%s: txd_cmd    = 0x%016llx\n",
1363 		    __func__, txd->txd_cmd));
1364 		DPRINTF(MEC_DEBUG_START,
1365 		    ("%s: txd_ptr[0] = 0x%016llx\n",
1366 		    __func__, txd->txd_ptr[0]));
1367 		DPRINTF(MEC_DEBUG_START,
1368 		    ("%s: txd_ptr[1] = 0x%016llx\n",
1369 		    __func__, txd->txd_ptr[1]));
1370 		DPRINTF(MEC_DEBUG_START,
1371 		    ("%s: txd_ptr[2] = 0x%016llx\n",
1372 		    __func__, txd->txd_ptr[2]));
1373 		DPRINTF(MEC_DEBUG_START,
1374 		    ("%s: len = %d (0x%04x), buflen = %d (0x%02x)\n",
1375 		    __func__, len, len, buflen, buflen));
1376 
1377 		/* sync TX descriptor */
1378 		MEC_TXDESCSYNC(sc, nexttx,
1379 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1380 
1381 		/* start TX */
1382 		bus_space_write_8(st, sh, MEC_TX_RING_PTR, MEC_NEXTTX(nexttx));
1383 
1384 		/* advance the TX pointer. */
1385 		sc->sc_txpending++;
1386 		sc->sc_txlast = nexttx;
1387 	}
1388 
1389 	if (sc->sc_txpending == MEC_NTXDESC - 1) {
1390 		/* No more slots; notify upper layer. */
1391 		MEC_EVCNT_INCR(&sc->sc_ev_txdstall);
1392 		ifp->if_flags |= IFF_OACTIVE;
1393 	}
1394 
1395 	if (sc->sc_txpending != opending) {
1396 		/*
1397 		 * If the transmitter was idle,
1398 		 * reset the txdirty pointer and re-enable TX interrupt.
1399 		 */
1400 		if (opending == 0) {
1401 			sc->sc_txdirty = firsttx;
1402 			bus_space_write_8(st, sh, MEC_TX_ALIAS,
1403 			    MEC_TX_ALIAS_INT_ENABLE);
1404 		}
1405 
1406 		/* Set a watchdog timer in case the chip flakes out. */
1407 		ifp->if_timer = 5;
1408 	}
1409 }
1410 
1411 static void
1412 mec_stop(struct ifnet *ifp, int disable)
1413 {
1414 	struct mec_softc *sc = ifp->if_softc;
1415 	struct mec_txsoft *txs;
1416 	int i;
1417 
1418 	DPRINTF(MEC_DEBUG_STOP, ("%s\n", __func__));
1419 
1420 	ifp->if_timer = 0;
1421 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1422 
1423 	callout_stop(&sc->sc_tick_ch);
1424 	mii_down(&sc->sc_mii);
1425 
1426 	/* release any TX buffers */
1427 	for (i = 0; i < MEC_NTXDESC; i++) {
1428 		txs = &sc->sc_txsoft[i];
1429 		if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) {
1430 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1431 			m_freem(txs->txs_mbuf);
1432 			txs->txs_mbuf = NULL;
1433 		}
1434 	}
1435 }
1436 
1437 static int
1438 mec_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1439 {
1440 	int s, error;
1441 
1442 	s = splnet();
1443 
1444 	error = ether_ioctl(ifp, cmd, data);
1445 	if (error == ENETRESET) {
1446 		/*
1447 		 * Multicast list has changed; set the hardware filter
1448 		 * accordingly.
1449 		 */
1450 		if (ifp->if_flags & IFF_RUNNING)
1451 			error = mec_init(ifp);
1452 		else
1453 			error = 0;
1454 	}
1455 
1456 	/* Try to get more packets going. */
1457 	mec_start(ifp);
1458 
1459 	splx(s);
1460 	return error;
1461 }
1462 
1463 static void
1464 mec_watchdog(struct ifnet *ifp)
1465 {
1466 	struct mec_softc *sc = ifp->if_softc;
1467 
1468 	printf("%s: device timeout\n", device_xname(sc->sc_dev));
1469 	ifp->if_oerrors++;
1470 
1471 	mec_init(ifp);
1472 }
1473 
1474 static void
1475 mec_tick(void *arg)
1476 {
1477 	struct mec_softc *sc = arg;
1478 	int s;
1479 
1480 	s = splnet();
1481 	mii_tick(&sc->sc_mii);
1482 	splx(s);
1483 
1484 	callout_reset(&sc->sc_tick_ch, hz, mec_tick, sc);
1485 }
1486 
1487 static void
1488 mec_setfilter(struct mec_softc *sc)
1489 {
1490 	struct ethercom *ec = &sc->sc_ethercom;
1491 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1492 	struct ether_multi *enm;
1493 	struct ether_multistep step;
1494 	bus_space_tag_t st = sc->sc_st;
1495 	bus_space_handle_t sh = sc->sc_sh;
1496 	uint64_t mchash;
1497 	uint32_t control, hash;
1498 	int mcnt;
1499 
1500 	control = bus_space_read_8(st, sh, MEC_MAC_CONTROL);
1501 	control &= ~MEC_MAC_FILTER_MASK;
1502 
1503 	if (ifp->if_flags & IFF_PROMISC) {
1504 		control |= MEC_MAC_FILTER_PROMISC;
1505 		bus_space_write_8(st, sh, MEC_MULTICAST, 0xffffffffffffffffULL);
1506 		bus_space_write_8(st, sh, MEC_MAC_CONTROL, control);
1507 		return;
1508 	}
1509 
1510 	mcnt = 0;
1511 	mchash = 0;
1512 	ETHER_FIRST_MULTI(step, ec, enm);
1513 	while (enm != NULL) {
1514 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1515 			/* set allmulti for a range of multicast addresses */
1516 			control |= MEC_MAC_FILTER_ALLMULTI;
1517 			bus_space_write_8(st, sh, MEC_MULTICAST,
1518 			    0xffffffffffffffffULL);
1519 			bus_space_write_8(st, sh, MEC_MAC_CONTROL, control);
1520 			return;
1521 		}
1522 
1523 #define mec_calchash(addr)	(ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
1524 
1525 		hash = mec_calchash(enm->enm_addrlo);
1526 		mchash |= 1 << hash;
1527 		mcnt++;
1528 		ETHER_NEXT_MULTI(step, enm);
1529 	}
1530 
1531 	ifp->if_flags &= ~IFF_ALLMULTI;
1532 
1533 	if (mcnt > 0)
1534 		control |= MEC_MAC_FILTER_MATCHMULTI;
1535 
1536 	bus_space_write_8(st, sh, MEC_MULTICAST, mchash);
1537 	bus_space_write_8(st, sh, MEC_MAC_CONTROL, control);
1538 }
1539 
1540 static int
1541 mec_intr(void *arg)
1542 {
1543 	struct mec_softc *sc = arg;
1544 	bus_space_tag_t st = sc->sc_st;
1545 	bus_space_handle_t sh = sc->sc_sh;
1546 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1547 	uint32_t statreg, statack, txptr;
1548 	int handled, sent;
1549 
1550 	DPRINTF(MEC_DEBUG_INTR, ("%s: called\n", __func__));
1551 
1552 	handled = sent = 0;
1553 
1554 	for (;;) {
1555 		statreg = bus_space_read_8(st, sh, MEC_INT_STATUS);
1556 
1557 		DPRINTF(MEC_DEBUG_INTR,
1558 		    ("%s: INT_STAT = 0x%08x\n", __func__, statreg));
1559 
1560 		statack = statreg & MEC_INT_STATUS_MASK;
1561 		if (statack == 0)
1562 			break;
1563 		bus_space_write_8(st, sh, MEC_INT_STATUS, statack);
1564 
1565 		handled = 1;
1566 
1567 		if (statack &
1568 		    (MEC_INT_RX_THRESHOLD |
1569 		     MEC_INT_RX_FIFO_UNDERFLOW)) {
1570 			mec_rxintr(sc);
1571 		}
1572 
1573 		if (statack &
1574 		    (MEC_INT_TX_EMPTY |
1575 		     MEC_INT_TX_PACKET_SENT |
1576 		     MEC_INT_TX_ABORT)) {
1577 			txptr = (statreg & MEC_INT_TX_RING_BUFFER_ALIAS)
1578 			    >> MEC_INT_TX_RING_BUFFER_SHIFT;
1579 			mec_txintr(sc, txptr);
1580 			sent = 1;
1581 			if ((statack & MEC_INT_TX_EMPTY) != 0) {
1582 				/*
1583 				 * disable TX interrupt to stop
1584 				 * TX empty interrupt
1585 				 */
1586 				bus_space_write_8(st, sh, MEC_TX_ALIAS, 0);
1587 				DPRINTF(MEC_DEBUG_INTR,
1588 				    ("%s: disable TX_INT\n", __func__));
1589 			}
1590 #ifdef MEC_EVENT_COUNTERS
1591 			if ((statack & MEC_INT_TX_EMPTY) != 0)
1592 				MEC_EVCNT_INCR(&sc->sc_ev_txempty);
1593 			if ((statack & MEC_INT_TX_PACKET_SENT) != 0)
1594 				MEC_EVCNT_INCR(&sc->sc_ev_txsent);
1595 #endif
1596 		}
1597 
1598 		if (statack &
1599 		    (MEC_INT_TX_LINK_FAIL |
1600 		     MEC_INT_TX_MEM_ERROR |
1601 		     MEC_INT_TX_ABORT |
1602 		     MEC_INT_RX_DMA_UNDERFLOW)) {
1603 			printf("%s: %s: interrupt status = 0x%08x\n",
1604 			    device_xname(sc->sc_dev), __func__, statreg);
1605 			mec_init(ifp);
1606 			break;
1607 		}
1608 	}
1609 
1610 	if (sent) {
1611 		/* try to get more packets going */
1612 		if_schedule_deferred_start(ifp);
1613 	}
1614 
1615 	if (handled)
1616 		rnd_add_uint32(&sc->sc_rnd_source, statreg);
1617 
1618 	return handled;
1619 }
1620 
1621 static void
1622 mec_rxintr(struct mec_softc *sc)
1623 {
1624 	bus_space_tag_t st = sc->sc_st;
1625 	bus_space_handle_t sh = sc->sc_sh;
1626 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1627 	struct mbuf *m;
1628 	struct mec_rxdesc *rxd;
1629 	uint64_t rxstat;
1630 	u_int len;
1631 	int i;
1632 	uint32_t crc;
1633 
1634 	DPRINTF(MEC_DEBUG_RXINTR, ("%s: called\n", __func__));
1635 
1636 	for (i = sc->sc_rxptr;; i = MEC_NEXTRX(i)) {
1637 		rxd = &sc->sc_rxdesc[i];
1638 
1639 		MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_POSTREAD);
1640 		rxstat = rxd->rxd_stat;
1641 
1642 		DPRINTF(MEC_DEBUG_RXINTR,
1643 		    ("%s: rxstat = 0x%016llx, rxptr = %d\n",
1644 		    __func__, rxstat, i));
1645 		DPRINTF(MEC_DEBUG_RXINTR, ("%s: rxfifo = 0x%08x\n",
1646 		    __func__, (u_int)bus_space_read_8(st, sh, MEC_RX_FIFO)));
1647 
1648 		if ((rxstat & MEC_RXSTAT_RECEIVED) == 0) {
1649 			MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);
1650 			break;
1651 		}
1652 
1653 		len = rxstat & MEC_RXSTAT_LEN;
1654 
1655 		if (len < ETHER_MIN_LEN ||
1656 		    len > (MCLBYTES - MEC_ETHER_ALIGN)) {
1657 			/* invalid length packet; drop it. */
1658 			DPRINTF(MEC_DEBUG_RXINTR,
1659 			    ("%s: wrong packet\n", __func__));
1660  dropit:
1661 			ifp->if_ierrors++;
1662 			rxd->rxd_stat = 0;
1663 			MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);
1664 			bus_space_write_8(st, sh, MEC_MCL_RX_FIFO,
1665 			    MEC_CDRXADDR(sc, i));
1666 			continue;
1667 		}
1668 
1669 		/*
1670 		 * If 802.1Q VLAN MTU is enabled, ignore the bad packet error.
1671 		 */
1672 		if ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) != 0)
1673 			rxstat &= ~MEC_RXSTAT_BADPACKET;
1674 
1675 		if (rxstat &
1676 		    (MEC_RXSTAT_BADPACKET |
1677 		     MEC_RXSTAT_LONGEVENT |
1678 		     MEC_RXSTAT_INVALID   |
1679 		     MEC_RXSTAT_CRCERROR  |
1680 		     MEC_RXSTAT_VIOLATION)) {
1681 			printf("%s: mec_rxintr: status = 0x%016"PRIx64"\n",
1682 			    device_xname(sc->sc_dev), rxstat);
1683 			goto dropit;
1684 		}
1685 
1686 		/*
1687 		 * The MEC includes the CRC with every packet.  Trim
1688 		 * it off here.
1689 		 */
1690 		len -= ETHER_CRC_LEN;
1691 
1692 		/*
1693 		 * now allocate an mbuf (and possibly a cluster) to hold
1694 		 * the received packet.
1695 		 */
1696 		MGETHDR(m, M_DONTWAIT, MT_DATA);
1697 		if (m == NULL) {
1698 			printf("%s: unable to allocate RX mbuf\n",
1699 			    device_xname(sc->sc_dev));
1700 			goto dropit;
1701 		}
1702 		if (len > (MHLEN - MEC_ETHER_ALIGN)) {
1703 			MCLGET(m, M_DONTWAIT);
1704 			if ((m->m_flags & M_EXT) == 0) {
1705 				printf("%s: unable to allocate RX cluster\n",
1706 				    device_xname(sc->sc_dev));
1707 				m_freem(m);
1708 				m = NULL;
1709 				goto dropit;
1710 			}
1711 		}
1712 
1713 		/*
1714 		 * Note MEC chip seems to insert 2 byte padding at the top of
1715 		 * RX buffer, but we copy whole buffer to avoid unaligned copy.
1716 		 */
1717 		MEC_RXBUFSYNC(sc, i, len + ETHER_CRC_LEN, BUS_DMASYNC_POSTREAD);
1718 		memcpy(mtod(m, void *), rxd->rxd_buf, MEC_ETHER_ALIGN + len);
1719 		crc = be32dec(rxd->rxd_buf + MEC_ETHER_ALIGN + len);
1720 		MEC_RXBUFSYNC(sc, i, ETHER_MAX_LEN, BUS_DMASYNC_PREREAD);
1721 		m->m_data += MEC_ETHER_ALIGN;
1722 
1723 		/* put RX buffer into FIFO again */
1724 		rxd->rxd_stat = 0;
1725 		MEC_RXSTATSYNC(sc, i, BUS_DMASYNC_PREREAD);
1726 		bus_space_write_8(st, sh, MEC_MCL_RX_FIFO, MEC_CDRXADDR(sc, i));
1727 
1728 		m_set_rcvif(m, ifp);
1729 		m->m_pkthdr.len = m->m_len = len;
1730 		if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0)
1731 			mec_rxcsum(sc, m, RXSTAT_CKSUM(rxstat), crc);
1732 
1733 		/* Pass it on. */
1734 		if_percpuq_enqueue(ifp->if_percpuq, m);
1735 	}
1736 
1737 	/* update RX pointer */
1738 	sc->sc_rxptr = i;
1739 }
1740 
1741 static void
1742 mec_rxcsum(struct mec_softc *sc, struct mbuf *m, uint16_t rxcsum, uint32_t crc)
1743 {
1744 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1745 	struct ether_header *eh;
1746 	struct ip *ip;
1747 	struct udphdr *uh;
1748 	u_int len, pktlen, hlen;
1749 	uint32_t csum_data, dsum;
1750 	int csum_flags;
1751 	const uint16_t *dp;
1752 
1753 	csum_data = 0;
1754 	csum_flags = 0;
1755 
1756 	len = m->m_len;
1757 	if (len < ETHER_HDR_LEN + sizeof(struct ip))
1758 		goto out;
1759 	pktlen = len - ETHER_HDR_LEN;
1760 	eh = mtod(m, struct ether_header *);
1761 	if (ntohs(eh->ether_type) != ETHERTYPE_IP)
1762 		goto out;
1763 	ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN);
1764 	if (ip->ip_v != IPVERSION)
1765 		goto out;
1766 
1767 	hlen = ip->ip_hl << 2;
1768 	if (hlen < sizeof(struct ip))
1769 		goto out;
1770 
1771 	/*
1772 	 * Bail if too short, has random trailing garbage, truncated,
1773 	 * fragment, or has ethernet pad.
1774 	 */
1775 	if (ntohs(ip->ip_len) < hlen ||
1776 	    ntohs(ip->ip_len) != pktlen ||
1777 	    (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0)
1778 		goto out;
1779 
1780 	switch (ip->ip_p) {
1781 	case IPPROTO_TCP:
1782 		if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 ||
1783 		    pktlen < (hlen + sizeof(struct tcphdr)))
1784 			goto out;
1785 		csum_flags = M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR;
1786 		break;
1787 	case IPPROTO_UDP:
1788 		if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 ||
1789 		    pktlen < (hlen + sizeof(struct udphdr)))
1790 			goto out;
1791 		uh = (struct udphdr *)((uint8_t *)ip + hlen);
1792 		if (uh->uh_sum == 0)
1793 			goto out;	/* no checksum */
1794 		csum_flags = M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR;
1795 		break;
1796 	default:
1797 		goto out;
1798 	}
1799 
1800 	/*
1801 	 * The computed checksum includes Ethernet header, IP headers,
1802 	 * and CRC, so we have to deduct them.
1803 	 * Note IP header cksum should be 0xffff so we don't have to
1804 	 * dedecut them.
1805 	 */
1806 	dsum = 0;
1807 
1808 	/* deduct Ethernet header */
1809 	dp = (const uint16_t *)eh;
1810 	for (hlen = 0; hlen < (ETHER_HDR_LEN / sizeof(uint16_t)); hlen++)
1811 		dsum += ntohs(*dp++);
1812 
1813 	/* deduct CRC */
1814 	if (len & 1) {
1815 		dsum += (crc >> 24) & 0x00ff;
1816 		dsum += (crc >>  8) & 0xffff;
1817 		dsum += (crc <<  8) & 0xff00;
1818 	} else {
1819 		dsum += (crc >> 16) & 0xffff;
1820 		dsum += (crc >>  0) & 0xffff;
1821 	}
1822 	while (dsum >> 16)
1823 		dsum = (dsum >> 16) + (dsum & 0xffff);
1824 
1825 	csum_data = rxcsum;
1826 	csum_data += (uint16_t)~dsum;
1827 
1828 	while (csum_data >> 16)
1829 		csum_data = (csum_data >> 16) + (csum_data & 0xffff);
1830 
1831  out:
1832 	m->m_pkthdr.csum_flags = csum_flags;
1833 	m->m_pkthdr.csum_data = csum_data;
1834 }
1835 
1836 static void
1837 mec_txintr(struct mec_softc *sc, uint32_t txptr)
1838 {
1839 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1840 	struct mec_txdesc *txd;
1841 	struct mec_txsoft *txs;
1842 	bus_dmamap_t dmamap;
1843 	uint64_t txstat;
1844 	int i;
1845 	u_int col;
1846 
1847 	DPRINTF(MEC_DEBUG_TXINTR, ("%s: called\n", __func__));
1848 
1849 	for (i = sc->sc_txdirty; i != txptr && sc->sc_txpending != 0;
1850 	    i = MEC_NEXTTX(i), sc->sc_txpending--) {
1851 		txd = &sc->sc_txdesc[i];
1852 
1853 		MEC_TXCMDSYNC(sc, i,
1854 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1855 
1856 		txstat = txd->txd_stat;
1857 		DPRINTF(MEC_DEBUG_TXINTR,
1858 		    ("%s: dirty = %d, txstat = 0x%016llx\n",
1859 		    __func__, i, txstat));
1860 		if ((txstat & MEC_TXSTAT_SENT) == 0) {
1861 			MEC_TXCMDSYNC(sc, i, BUS_DMASYNC_PREREAD);
1862 			break;
1863 		}
1864 
1865 		txs = &sc->sc_txsoft[i];
1866 		if ((txs->txs_flags & MEC_TXS_TXDPTR) != 0) {
1867 			dmamap = txs->txs_dmamap;
1868 			bus_dmamap_sync(sc->sc_dmat, dmamap, 0,
1869 			    dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1870 			bus_dmamap_unload(sc->sc_dmat, dmamap);
1871 			m_freem(txs->txs_mbuf);
1872 			txs->txs_mbuf = NULL;
1873 		}
1874 
1875 		col = (txstat & MEC_TXSTAT_COLCNT) >> MEC_TXSTAT_COLCNT_SHIFT;
1876 		ifp->if_collisions += col;
1877 
1878 		if ((txstat & MEC_TXSTAT_SUCCESS) == 0) {
1879 			printf("%s: TX error: txstat = 0x%016"PRIx64"\n",
1880 			    device_xname(sc->sc_dev), txstat);
1881 			ifp->if_oerrors++;
1882 		} else
1883 			ifp->if_opackets++;
1884 	}
1885 
1886 	/* update the dirty TX buffer pointer */
1887 	sc->sc_txdirty = i;
1888 	DPRINTF(MEC_DEBUG_INTR,
1889 	    ("%s: sc_txdirty = %2d, sc_txpending = %2d\n",
1890 	    __func__, sc->sc_txdirty, sc->sc_txpending));
1891 
1892 	/* cancel the watchdog timer if there are no pending TX packets */
1893 	if (sc->sc_txpending == 0)
1894 		ifp->if_timer = 0;
1895 	if (sc->sc_txpending < MEC_NTXDESC - MEC_NTXDESC_RSVD)
1896 		ifp->if_flags &= ~IFF_OACTIVE;
1897 }
1898 
1899 static bool
1900 mec_shutdown(device_t self, int howto)
1901 {
1902 	struct mec_softc *sc = device_private(self);
1903 
1904 	mec_stop(&sc->sc_ethercom.ec_if, 1);
1905 	/* make sure to stop DMA etc. */
1906 	mec_reset(sc);
1907 
1908 	return true;
1909 }
1910